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Date: Sat, 2 Mar 2024 02:03:38 +0000
From: "Jason R Thorpe" <thorpej@netbsd.org>
Subject: CVS commit: pkgsrc/devel
To: pkgsrc-changes@NetBSD.org
Reply-To: thorpej@netbsd.org
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Module Name:	pkgsrc
Committed By:	thorpej
Date:		Sat Mar  2 02:03:38 UTC 2024

Modified Files:
	pkgsrc/devel: Makefile
Added Files:
	pkgsrc/devel/yosys: DESCR Makefile PLIST distinfo
	pkgsrc/devel/yosys/patches: patch-abc_Makefile patch-kernel_yosys.cc

Log Message:
Add a package for yosys:

The Yosys Open SYnthesis Suite is a framework for RTL synthesis tools. It
currently has extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.

Together with nextpnr-ice40 and icestorm, this forms a toolchain that can
be used to synthesize and program designs for Lattice iCE40-family FPGAs.


To generate a diff of this commit:
cvs rdiff -u -r1.4188 -r1.4189 pkgsrc/devel/Makefile
cvs rdiff -u -r0 -r1.1 pkgsrc/devel/yosys/DESCR pkgsrc/devel/yosys/Makefile \
    pkgsrc/devel/yosys/PLIST pkgsrc/devel/yosys/distinfo
cvs rdiff -u -r0 -r1.1 pkgsrc/devel/yosys/patches/patch-abc_Makefile \
    pkgsrc/devel/yosys/patches/patch-kernel_yosys.cc

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


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Modified files:

Index: pkgsrc/devel/Makefile
diff -u pkgsrc/devel/Makefile:1.4188 pkgsrc/devel/Makefile:1.4189
--- pkgsrc/devel/Makefile:1.4188	Thu Feb 29 07:51:25 2024
+++ pkgsrc/devel/Makefile	Sat Mar  2 02:03:37 2024
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.4188 2024/02/29 07:51:25 wiz Exp $
+# $NetBSD: Makefile,v 1.4189 2024/03/02 02:03:37 thorpej Exp $
 #
 
 COMMENT=	Development utilities
@@ -3606,6 +3606,7 @@ SUBDIR+=	xxhash
 SUBDIR+=	yajl
 SUBDIR+=	yarn
 SUBDIR+=	yasm
+SUBDIR+=	yosys
 SUBDIR+=	z80-asm
 SUBDIR+=	zeal
 SUBDIR+=	zig-mode

Added files:

Index: pkgsrc/devel/yosys/DESCR
diff -u /dev/null pkgsrc/devel/yosys/DESCR:1.1
--- /dev/null	Sat Mar  2 02:03:38 2024
+++ pkgsrc/devel/yosys/DESCR	Sat Mar  2 02:03:37 2024
@@ -0,0 +1,3 @@
+The Yosys Open SYnthesis Suite is a framework for RTL synthesis tools. It
+currently has extensive Verilog-2005 support and provides a basic set of
+synthesis algorithms for various application domains.
Index: pkgsrc/devel/yosys/Makefile
diff -u /dev/null pkgsrc/devel/yosys/Makefile:1.1
--- /dev/null	Sat Mar  2 02:03:38 2024
+++ pkgsrc/devel/yosys/Makefile	Sat Mar  2 02:03:37 2024
@@ -0,0 +1,78 @@
+# $NetBSD: Makefile,v 1.1 2024/03/02 02:03:37 thorpej Exp $
+
+YOSYS_VERSION=	0.38
+YOSYS_TAG=	yosys-${YOSYS_VERSION}
+ABC_DISTNAME=	abc-${YOSYS_TAG}
+DISTNAME=	${YOSYS_TAG}
+CATEGORIES=	devel
+MASTER_SITES=	${MASTER_SITE_GITHUB:=YosysHQ/}
+GITHUB_TAG=	${YOSYS_TAG}
+WRKSRC=		${WRKDIR}/yosys-${YOSYS_TAG}
+EXTRACT_SUFX=	.tar.gz		# needed early
+
+MAINTAINER=	thorpej@NetBSD.org
+HOMEPAGE=	https://github.com/YosysHQ/yosys
+COMMENT=	Yosys Open SYnthesis Suite
+LICENSE=	isc
+
+ONLY_FOR_COMPILER=	clang gcc
+USE_LANGUAGES=		c c++
+
+.include "../../mk/bsd.prefs.mk"
+.include "../../mk/compiler.mk"
+
+ABC_DISTFILE=	${ABC_DISTNAME}${EXTRACT_SUFX}
+DISTFILES=	${DEFAULT_DISTFILES}
+
+DISTFILES+=		${ABC_DISTFILE}
+SITES.${ABC_DISTFILE}=	-${MASTER_SITE_GITHUB:=YosysHQ/abc/archive/}${GITHUB_TAG}${EXTRACT_SUFX}
+
+EXTRACT_DIR.${ABC_DISTFILE}=		${WRKSRC}/abc
+EXTRACT_OPTS_TAR.${ABC_DISTFILE}=	--strip-components=1
+
+.if !empty(CC_VERSION:Mclang*)
+YOSYS_COMPILER=	clang
+.else
+YOSYS_COMPILER=	gcc
+.endif
+
+USE_TOOLS+=	gmake
+USE_TOOLS+=	bison
+USE_TOOLS+=	flex
+USE_TOOLS+=	gawk
+
+# The Apple developer tools include git, so we don't need to
+# depend on it explicitly in that case.
+.if ${OPSYS} != "Darwin"
+TOOL_DEPENDS+=	git-base>=2.39.3:../../devel/git-base
+.endif
+
+REPLACE_PYTHON+=	backends/smt2/*.py
+REPLACE_PYTHON+=	docs/source/*.py
+REPLACE_PYTHON+=	passes/pmgen/*.py
+REPLACE_PYTHON+=	techlibs/common/*.py
+REPLACE_PYTHON+=	techlibs/gatemate/*.py
+REPLACE_PYTHON+=	techlibs/gowin/*.py
+REPLACE_PYTHON+=	techlibs/lattice/*.py
+REPLACE_PYTHON+=	techlibs/nexus/*.py
+REPLACE_PYTHON+=	techlibs/xilinx/*.py
+REPLACE_PYTHON+=	tests/bram/*.py
+REPLACE_PYTHON+=	tests/fsm/*.py
+REPLACE_PYTHON+=	tests/opt_share/*.py
+REPLACE_PYTHON+=	tests/realmath/*.py
+REPLACE_PYTHON+=	tests/share/*.py
+REPLACE_PYTHON+=	tests/tools/*.py
+
+do-configure:
+	cd ${WRKSRC} && ${MAKE_PROGRAM} config-${YOSYS_COMPILER}
+
+.include "../../lang/python/application.mk"
+.include "../../lang/python/tool.mk"
+.include "../../lang/tcl/buildlink3.mk"
+.include "../../devel/boost-libs/buildlink3.mk"
+.include "../../devel/readline/buildlink3.mk"
+.include "../../devel/libffi/buildlink3.mk"
+.include "../../devel/pkgconf/buildlink3.mk"
+.include "../../graphics/graphviz/buildlink3.mk"
+.include "../../mk/dlopen.buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
Index: pkgsrc/devel/yosys/PLIST
diff -u /dev/null pkgsrc/devel/yosys/PLIST:1.1
--- /dev/null	Sat Mar  2 02:03:38 2024
+++ pkgsrc/devel/yosys/PLIST	Sat Mar  2 02:03:37 2024
@@ -0,0 +1,280 @@
+@comment $NetBSD: PLIST,v 1.1 2024/03/02 02:03:37 thorpej Exp $
+bin/yosys
+bin/yosys-abc
+bin/yosys-config
+bin/yosys-filterlib
+bin/yosys-smtbmc
+bin/yosys-witness
+share/yosys/abc9_map.v
+share/yosys/abc9_model.v
+share/yosys/abc9_unmap.v
+share/yosys/achronix/speedster22i/cells_map.v
+share/yosys/achronix/speedster22i/cells_sim.v
+share/yosys/adff2dff.v
+share/yosys/anlogic/arith_map.v
+share/yosys/anlogic/brams.txt
+share/yosys/anlogic/brams_map.v
+share/yosys/anlogic/cells_map.v
+share/yosys/anlogic/cells_sim.v
+share/yosys/anlogic/eagle_bb.v
+share/yosys/anlogic/lutrams.txt
+share/yosys/anlogic/lutrams_map.v
+share/yosys/cells.lib
+share/yosys/cmp2lcu.v
+share/yosys/cmp2lut.v
+share/yosys/cmp2softlogic.v
+share/yosys/coolrunner2/cells_counter_map.v
+share/yosys/coolrunner2/cells_latch.v
+share/yosys/coolrunner2/cells_sim.v
+share/yosys/coolrunner2/tff_extract.v
+share/yosys/coolrunner2/xc2_dff.lib
+share/yosys/dff2ff.v
+share/yosys/ecp5/arith_map.v
+share/yosys/ecp5/brams.txt
+share/yosys/ecp5/brams_map.v
+share/yosys/ecp5/cells_bb.v
+share/yosys/ecp5/cells_ff.vh
+share/yosys/ecp5/cells_io.vh
+share/yosys/ecp5/cells_map.v
+share/yosys/ecp5/cells_sim.v
+share/yosys/ecp5/dsp_map.v
+share/yosys/ecp5/latches_map.v
+share/yosys/ecp5/lutrams.txt
+share/yosys/ecp5/lutrams_map.v
+share/yosys/efinix/arith_map.v
+share/yosys/efinix/brams.txt
+share/yosys/efinix/brams_map.v
+share/yosys/efinix/cells_map.v
+share/yosys/efinix/cells_sim.v
+share/yosys/efinix/gbuf_map.v
+share/yosys/fabulous/arith_map.v
+share/yosys/fabulous/cells_map.v
+share/yosys/fabulous/ff_map.v
+share/yosys/fabulous/io_map.v
+share/yosys/fabulous/latches_map.v
+share/yosys/fabulous/prims.v
+share/yosys/fabulous/ram_regfile.txt
+share/yosys/fabulous/regfile_map.v
+share/yosys/gate2lut.v
+share/yosys/gatemate/arith_map.v
+share/yosys/gatemate/brams.txt
+share/yosys/gatemate/brams_init_20.vh
+share/yosys/gatemate/brams_init_40.vh
+share/yosys/gatemate/brams_map.v
+share/yosys/gatemate/cells_bb.v
+share/yosys/gatemate/cells_sim.v
+share/yosys/gatemate/inv_map.v
+share/yosys/gatemate/lut_map.v
+share/yosys/gatemate/lut_tree_cells.genlib
+share/yosys/gatemate/lut_tree_map.v
+share/yosys/gatemate/mul_map.v
+share/yosys/gatemate/mux_map.v
+share/yosys/gatemate/reg_map.v
+share/yosys/gowin/arith_map.v
+share/yosys/gowin/brams.txt
+share/yosys/gowin/brams_map.v
+share/yosys/gowin/cells_map.v
+share/yosys/gowin/cells_sim.v
+share/yosys/gowin/cells_xtra.v
+share/yosys/gowin/lutrams.txt
+share/yosys/gowin/lutrams_map.v
+share/yosys/greenpak4/cells_blackbox.v
+share/yosys/greenpak4/cells_latch.v
+share/yosys/greenpak4/cells_map.v
+share/yosys/greenpak4/cells_sim.v
+share/yosys/greenpak4/cells_sim_ams.v
+share/yosys/greenpak4/cells_sim_digital.v
+share/yosys/greenpak4/cells_sim_wip.v
+share/yosys/greenpak4/gp_dff.lib
+share/yosys/ice40/abc9_model.v
+share/yosys/ice40/arith_map.v
+share/yosys/ice40/brams.txt
+share/yosys/ice40/brams_map.v
+share/yosys/ice40/cells_map.v
+share/yosys/ice40/cells_sim.v
+share/yosys/ice40/dsp_map.v
+share/yosys/ice40/ff_map.v
+share/yosys/ice40/latches_map.v
+share/yosys/ice40/spram.txt
+share/yosys/ice40/spram_map.v
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
+share/yosys/include/backends/rtlil/rtlil_backend.h
+share/yosys/include/frontends/ast/ast.h
+share/yosys/include/frontends/ast/ast_binding.h
+share/yosys/include/frontends/blif/blifparse.h
+share/yosys/include/kernel/binding.h
+share/yosys/include/kernel/cellaigs.h
+share/yosys/include/kernel/celledges.h
+share/yosys/include/kernel/celltypes.h
+share/yosys/include/kernel/consteval.h
+share/yosys/include/kernel/constids.inc
+share/yosys/include/kernel/cost.h
+share/yosys/include/kernel/ff.h
+share/yosys/include/kernel/ffinit.h
+share/yosys/include/kernel/ffmerge.h
+share/yosys/include/kernel/fmt.h
+share/yosys/include/kernel/fstdata.h
+share/yosys/include/kernel/hashlib.h
+share/yosys/include/kernel/json.h
+share/yosys/include/kernel/log.h
+share/yosys/include/kernel/macc.h
+share/yosys/include/kernel/mem.h
+share/yosys/include/kernel/modtools.h
+share/yosys/include/kernel/qcsat.h
+share/yosys/include/kernel/register.h
+share/yosys/include/kernel/rtlil.h
+share/yosys/include/kernel/satgen.h
+share/yosys/include/kernel/sigtools.h
+share/yosys/include/kernel/timinginfo.h
+share/yosys/include/kernel/utils.h
+share/yosys/include/kernel/yosys.h
+share/yosys/include/kernel/yw.h
+share/yosys/include/libs/ezsat/ezminisat.h
+share/yosys/include/libs/ezsat/ezsat.h
+share/yosys/include/libs/fst/fstapi.h
+share/yosys/include/libs/json11/json11.hpp
+share/yosys/include/libs/sha1/sha1.h
+share/yosys/include/passes/fsm/fsmdata.h
+share/yosys/intel/common/altpll_bb.v
+share/yosys/intel/common/brams_m9k.txt
+share/yosys/intel/common/brams_map_m9k.v
+share/yosys/intel/common/ff_map.v
+share/yosys/intel/common/m9k_bb.v
+share/yosys/intel/cyclone10lp/cells_map.v
+share/yosys/intel/cyclone10lp/cells_sim.v
+share/yosys/intel/cycloneiv/cells_map.v
+share/yosys/intel/cycloneiv/cells_sim.v
+share/yosys/intel/cycloneive/cells_map.v
+share/yosys/intel/cycloneive/cells_sim.v
+share/yosys/intel/max10/cells_map.v
+share/yosys/intel/max10/cells_sim.v
+share/yosys/intel_alm/common/abc9_map.v
+share/yosys/intel_alm/common/abc9_model.v
+share/yosys/intel_alm/common/abc9_unmap.v
+share/yosys/intel_alm/common/alm_map.v
+share/yosys/intel_alm/common/alm_sim.v
+share/yosys/intel_alm/common/arith_alm_map.v
+share/yosys/intel_alm/common/bram_m10k.txt
+share/yosys/intel_alm/common/bram_m10k_map.v
+share/yosys/intel_alm/common/bram_m20k.txt
+share/yosys/intel_alm/common/bram_m20k_map.v
+share/yosys/intel_alm/common/dff_map.v
+share/yosys/intel_alm/common/dff_sim.v
+share/yosys/intel_alm/common/dsp_map.v
+share/yosys/intel_alm/common/dsp_sim.v
+share/yosys/intel_alm/common/lutram_mlab.txt
+share/yosys/intel_alm/common/megafunction_bb.v
+share/yosys/intel_alm/common/mem_sim.v
+share/yosys/intel_alm/common/misc_sim.v
+share/yosys/intel_alm/common/quartus_rename.v
+share/yosys/intel_alm/cyclonev/cells_sim.v
+share/yosys/lattice/arith_map_ccu2c.v
+share/yosys/lattice/arith_map_ccu2d.v
+share/yosys/lattice/brams_16kd.txt
+share/yosys/lattice/brams_8kc.txt
+share/yosys/lattice/brams_map_16kd.v
+share/yosys/lattice/brams_map_8kc.v
+share/yosys/lattice/ccu2c_sim.vh
+share/yosys/lattice/ccu2d_sim.vh
+share/yosys/lattice/cells_bb_ecp5.v
+share/yosys/lattice/cells_bb_xo2.v
+share/yosys/lattice/cells_bb_xo3.v
+share/yosys/lattice/cells_bb_xo3d.v
+share/yosys/lattice/cells_ff.vh
+share/yosys/lattice/cells_io.vh
+share/yosys/lattice/cells_map.v
+share/yosys/lattice/cells_sim_ecp5.v
+share/yosys/lattice/cells_sim_xo2.v
+share/yosys/lattice/cells_sim_xo3.v
+share/yosys/lattice/cells_sim_xo3d.v
+share/yosys/lattice/common_sim.vh
+share/yosys/lattice/dsp_map_18x18.v
+share/yosys/lattice/latches_map.v
+share/yosys/lattice/lutrams.txt
+share/yosys/lattice/lutrams_map.v
+share/yosys/mul2dsp.v
+share/yosys/nexus/arith_map.v
+share/yosys/nexus/brams.txt
+share/yosys/nexus/brams_map.v
+share/yosys/nexus/cells_map.v
+share/yosys/nexus/cells_sim.v
+share/yosys/nexus/cells_xtra.v
+share/yosys/nexus/dsp_map.v
+share/yosys/nexus/latches_map.v
+share/yosys/nexus/lrams.txt
+share/yosys/nexus/lrams_map.v
+share/yosys/nexus/lutrams.txt
+share/yosys/nexus/lutrams_map.v
+share/yosys/nexus/parse_init.vh
+share/yosys/pmux2mux.v
+share/yosys/python3/smtio.py
+share/yosys/python3/ywio.py
+share/yosys/quicklogic/common/cells_sim.v
+share/yosys/quicklogic/pp3/abc9_map.v
+share/yosys/quicklogic/pp3/abc9_model.v
+share/yosys/quicklogic/pp3/abc9_unmap.v
+share/yosys/quicklogic/pp3/cells_map.v
+share/yosys/quicklogic/pp3/cells_sim.v
+share/yosys/quicklogic/pp3/ffs_map.v
+share/yosys/quicklogic/pp3/latches_map.v
+share/yosys/quicklogic/pp3/lut_map.v
+share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+share/yosys/quicklogic/qlf_k6n10f/arith_map.v
+share/yosys/quicklogic/qlf_k6n10f/bram_types_sim.v
+share/yosys/quicklogic/qlf_k6n10f/brams_map.v
+share/yosys/quicklogic/qlf_k6n10f/brams_sim.v
+share/yosys/quicklogic/qlf_k6n10f/cells_sim.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v
+share/yosys/quicklogic/qlf_k6n10f/ffs_map.v
+share/yosys/quicklogic/qlf_k6n10f/libmap_brams.txt
+share/yosys/quicklogic/qlf_k6n10f/libmap_brams_map.v
+share/yosys/quicklogic/qlf_k6n10f/sram1024x18_mem.v
+share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v
+share/yosys/sf2/arith_map.v
+share/yosys/sf2/cells_map.v
+share/yosys/sf2/cells_sim.v
+share/yosys/simcells.v
+share/yosys/simlib.v
+share/yosys/smtmap.v
+share/yosys/techmap.v
+share/yosys/xilinx/abc9_model.v
+share/yosys/xilinx/arith_map.v
+share/yosys/xilinx/brams_defs.vh
+share/yosys/xilinx/brams_xc2v.txt
+share/yosys/xilinx/brams_xc2v_map.v
+share/yosys/xilinx/brams_xc3sda.txt
+share/yosys/xilinx/brams_xc3sda_map.v
+share/yosys/xilinx/brams_xc4v.txt
+share/yosys/xilinx/brams_xc4v_map.v
+share/yosys/xilinx/brams_xc5v_map.v
+share/yosys/xilinx/brams_xc6v_map.v
+share/yosys/xilinx/brams_xcu_map.v
+share/yosys/xilinx/brams_xcv.txt
+share/yosys/xilinx/brams_xcv_map.v
+share/yosys/xilinx/cells_map.v
+share/yosys/xilinx/cells_sim.v
+share/yosys/xilinx/cells_xtra.v
+share/yosys/xilinx/ff_map.v
+share/yosys/xilinx/lut_map.v
+share/yosys/xilinx/lutrams_xc5v.txt
+share/yosys/xilinx/lutrams_xc5v_map.v
+share/yosys/xilinx/lutrams_xcu.txt
+share/yosys/xilinx/lutrams_xcv.txt
+share/yosys/xilinx/lutrams_xcv_map.v
+share/yosys/xilinx/mux_map.v
+share/yosys/xilinx/urams.txt
+share/yosys/xilinx/urams_map.v
+share/yosys/xilinx/xc3s_mult_map.v
+share/yosys/xilinx/xc3sda_dsp_map.v
+share/yosys/xilinx/xc4v_dsp_map.v
+share/yosys/xilinx/xc5v_dsp_map.v
+share/yosys/xilinx/xc6s_dsp_map.v
+share/yosys/xilinx/xc7_dsp_map.v
+share/yosys/xilinx/xcu_dsp_map.v
Index: pkgsrc/devel/yosys/distinfo
diff -u /dev/null pkgsrc/devel/yosys/distinfo:1.1
--- /dev/null	Sat Mar  2 02:03:38 2024
+++ pkgsrc/devel/yosys/distinfo	Sat Mar  2 02:03:37 2024
@@ -0,0 +1,10 @@
+$NetBSD: distinfo,v 1.1 2024/03/02 02:03:37 thorpej Exp $
+
+BLAKE2s (abc-yosys-0.38.tar.gz) = 4bfbb01053192c417143c922de5a4f1d823aba17a6f818a20cacddb56772f486
+SHA512 (abc-yosys-0.38.tar.gz) = 4f13454658a538085b5aebec0c92aa32f45fd0fa2777fa2180471120af336dd17b4007fab4597bdff787d29581635b698be373e81a504b9998576b0e55c8a191
+Size (abc-yosys-0.38.tar.gz) = 6142623 bytes
+BLAKE2s (yosys-0.38.tar.gz) = bf794aef85cd8133d2ef4a47b802c6fb0a9c0744df2aa3c63f2fb2905f38d3ce
+SHA512 (yosys-0.38.tar.gz) = d41b81593a717bfd71c3120bb823a8bfb739f485e1a1ca3055e743e3f9f7406aa3c883a5a001183613f9ac05aaee222dafe39a594ead68c1c2fd74c3b2a84038
+Size (yosys-0.38.tar.gz) = 2709217 bytes
+SHA1 (patch-abc_Makefile) = b4cbe6b905f26e8bf7980e230edc87e12efced99
+SHA1 (patch-kernel_yosys.cc) = 2b55d9e10350506ece747309ad22c2a003f714f8

Index: pkgsrc/devel/yosys/patches/patch-abc_Makefile
diff -u /dev/null pkgsrc/devel/yosys/patches/patch-abc_Makefile:1.1
--- /dev/null	Sat Mar  2 02:03:38 2024
+++ pkgsrc/devel/yosys/patches/patch-abc_Makefile	Sat Mar  2 02:03:37 2024
@@ -0,0 +1,20 @@
+$NetBSD: patch-abc_Makefile,v 1.1 2024/03/02 02:03:37 thorpej Exp $
+
+Also skip -ldl and -lrt on NetBSD.
+
+--- abc/Makefile.orig	2024-03-01 23:09:30.203342910 +0000
++++ abc/Makefile	2024-03-01 23:10:15.700143598 +0000
+@@ -137,11 +137,11 @@ endif
+ 
+ # LIBS := -ldl -lrt
+ LIBS += -lm
+-ifneq ($(OS), $(filter $(OS), FreeBSD OpenBSD))
++ifneq ($(OS), $(filter $(OS), FreeBSD OpenBSD NetBSD))
+   LIBS += -ldl
+ endif
+ 
+-ifneq ($(OS), $(filter $(OS), FreeBSD OpenBSD Darwin))
++ifneq ($(OS), $(filter $(OS), FreeBSD OpenBSD NetBSD Darwin))
+    LIBS += -lrt
+ endif
+ 
Index: pkgsrc/devel/yosys/patches/patch-kernel_yosys.cc
diff -u /dev/null pkgsrc/devel/yosys/patches/patch-kernel_yosys.cc:1.1
--- /dev/null	Sat Mar  2 02:03:38 2024
+++ pkgsrc/devel/yosys/patches/patch-kernel_yosys.cc	Sat Mar  2 02:03:37 2024
@@ -0,0 +1,24 @@
+$NetBSD: patch-kernel_yosys.cc,v 1.1 2024/03/02 02:03:37 thorpej Exp $
+
+On NetBSD, also use KERN_PROC_PATHNAME to get the path to the executable.
+
+--- kernel/yosys.cc.orig	2024-02-29 13:30:05.586482076 +0000
++++ kernel/yosys.cc	2024-02-29 13:30:54.466426964 +0000
+@@ -55,7 +55,7 @@
+ #  include <glob.h>
+ #endif
+ 
+-#ifdef __FreeBSD__
++#if defined(__FreeBSD__) || defined(__NetBSD__)
+ #  include <sys/sysctl.h>
+ #endif
+ 
+@@ -917,7 +917,7 @@ std::string proc_self_dirname()
+ 		buflen--;
+ 	return std::string(path, buflen);
+ }
+-#elif defined(__FreeBSD__)
++#elif defined(__FreeBSD__) || defined(__NetBSD__)
+ std::string proc_self_dirname()
+ {
+ 	int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PATHNAME, -1};


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