Thu Dec 27 16:01:54 2018 UTC ()
async is a keyword for Python 3.7+, so rename it. Bump revision
(joerg)
diff -r1.24 -r1.25 pkgsrc/cad/py-MyHDL/Makefile
diff -r1.10 -r1.11 pkgsrc/cad/py-MyHDL/distinfo
diff -r0 -r1.1 pkgsrc/cad/py-MyHDL/patches/patch-myhdl___always__seq.py
diff -r0 -r1.1 pkgsrc/cad/py-MyHDL/patches/patch-myhdl_conversion___toVHDL.py
--- pkgsrc/cad/py-MyHDL/Makefile 2016/10/09 03:15:57 1.24
+++ pkgsrc/cad/py-MyHDL/Makefile 2018/12/27 16:01:54 1.25
@@ -1,8 +1,9 @@
-# $NetBSD: Makefile,v 1.24 2016/10/09 03:15:57 kamil Exp $
+# $NetBSD: Makefile,v 1.25 2018/12/27 16:01:54 joerg Exp $
.include "Makefile.common"
PKGNAME= ${PYPKGPREFIX}-${DISTNAME:S/myhdl/MyHDL/}
+PKGREVISION= 1
MAINTAINER= pkgsrc-users@NetBSD.org
COMMENT= Hardware description in Python
--- pkgsrc/cad/py-MyHDL/distinfo 2018/04/12 15:08:58 1.10
+++ pkgsrc/cad/py-MyHDL/distinfo 2018/12/27 16:01:54 1.11
@@ -1,6 +1,8 @@
-$NetBSD: distinfo,v 1.10 2018/04/12 15:08:58 mef Exp $
+$NetBSD: distinfo,v 1.11 2018/12/27 16:01:54 joerg Exp $
SHA1 (myhdl-0.10.tar.gz) = d766a1a556e9dce23af07d1b378fbcc6e3b86494
RMD160 (myhdl-0.10.tar.gz) = 234d3f3c5d2d84e548e317e1b85bc28efbfd7b14
SHA512 (myhdl-0.10.tar.gz) = b250c8b09a2cfbd2a70da60d567c8bcb09747c3e8df536cdd28ad49a8a6fbe5a28395295a6ed6046ced745b617fb3804ceb0f83d9b34db7c70701148ae7db25b
Size (myhdl-0.10.tar.gz) = 1205466 bytes
+SHA1 (patch-myhdl___always__seq.py) = 2ba91a28a40f5582a7ab509ee8e619ce92333e92
+SHA1 (patch-myhdl_conversion___toVHDL.py) = 85651035475d908749306dfd57895060582a2051
$NetBSD: patch-myhdl___always__seq.py,v 1.1 2018/12/27 16:01:54 joerg Exp $
--- myhdl/_always_seq.py.orig 2018-12-25 21:39:40.951802739 +0000
+++ myhdl/_always_seq.py
@@ -45,7 +45,7 @@ _error.EmbeddedFunction = "embedded func
class ResetSignal(_Signal):
- def __init__(self, val, active, async):
+ def __init__(self, val, active, is_async):
""" Construct a ResetSignal.
This is to be used in conjunction with the always_seq decorator,
@@ -53,7 +53,7 @@ class ResetSignal(_Signal):
"""
_Signal.__init__(self, bool(val))
self.active = bool(active)
- self.async = async
+ self.is_async = is_async
def always_seq(edge, reset):
@@ -91,8 +91,8 @@ class _AlwaysSeq(_Always):
if reset is not None:
self.genfunc = self.genfunc_reset
active = self.reset.active
- async = self.reset.async
- if async:
+ is_async = self.reset.is_async
+ if is_async:
if active:
senslist.append(reset.posedge)
else:
$NetBSD: patch-myhdl_conversion___toVHDL.py,v 1.1 2018/12/27 16:01:54 joerg Exp $
--- myhdl/conversion/_toVHDL.py.orig 2018-12-25 21:40:10.283137098 +0000
+++ myhdl/conversion/_toVHDL.py
@@ -1838,12 +1838,12 @@ class _ConvertAlwaysSeqVisitor(_ConvertV
senslist = self.tree.senslist
edge = senslist[0]
reset = self.tree.reset
- async = reset is not None and reset.async
+ is_async = reset is not None and reset.is_async
sigregs = self.tree.sigregs
varregs = self.tree.varregs
self.write("%s: process (" % self.tree.name)
self.write(edge.sig)
- if async:
+ if is_async:
self.write(', ')
self.write(reset)
self.write(") is")
@@ -1853,7 +1853,7 @@ class _ConvertAlwaysSeqVisitor(_ConvertV
self.writeline()
self.write("begin")
self.indent()
- if not async:
+ if not is_async:
self.writeline()
self.write("if %s then" % edge._toVHDL())
self.indent()
@@ -1870,7 +1870,7 @@ class _ConvertAlwaysSeqVisitor(_ConvertV
self.write("%s := %s;" % (n, _convertInitVal(reg, init)))
self.dedent()
self.writeline()
- if async:
+ if is_async:
self.write("elsif %s then" % edge._toVHDL())
else:
self.write("else")
@@ -1881,7 +1881,7 @@ class _ConvertAlwaysSeqVisitor(_ConvertV
self.writeline()
self.write("end if;")
self.dedent()
- if not async:
+ if not is_async:
self.writeline()
self.write("end if;")
self.dedent()