Wed Mar 18 17:45:25 2020 UTC ()
Not really C++11 ready. Don't define bool/true/false for C++.


(joerg)
diff -r1.1 -r1.2 pkgsrc/cad/veriwell/Makefile
diff -r1.1 -r1.2 pkgsrc/cad/veriwell/distinfo
diff -r0 -r1.1 pkgsrc/cad/veriwell/patches/patch-src_acc__user.h
cvs diff -r1.1 -r1.2 pkgsrc/cad/veriwell/Makefile (expand / switch to unified diff)

--- pkgsrc/cad/veriwell/Makefile 2016/10/09 13:14:06 1.1
+++ pkgsrc/cad/veriwell/Makefile 2020/03/18 17:45:25 1.2
@@ -1,18 +1,18 @@ @@ -1,18 +1,18 @@
1# $NetBSD: Makefile,v 1.1 2016/10/09 13:14:06 kamil Exp $ 1# $NetBSD: Makefile,v 1.2 2020/03/18 17:45:25 joerg Exp $
2 2
3DISTNAME= veriwell-2.8.7 3DISTNAME= veriwell-2.8.7
4CATEGORIES= cad 4CATEGORIES= cad
5MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=veriwell/} 5MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=veriwell/}
6 6
7MAINTAINER= pkgsrc-users@NetBSD.org 7MAINTAINER= pkgsrc-users@NetBSD.org
8HOMEPAGE= https://sourceforge.net/projects/veriwell/ 8HOMEPAGE= https://sourceforge.net/projects/veriwell/
9COMMENT= Verilog Simulator 9COMMENT= Verilog Simulator
10LICENSE= gnu-gpl-v2 10LICENSE= gnu-gpl-v2
11 11
12GNU_CONFIGURE= yes 12GNU_CONFIGURE= yes
13USE_LANGUAGES= c c++ 13USE_LANGUAGES= c c++03
14 14
15TEST_TARGET= check 15TEST_TARGET= check
16 16
17.include "../../devel/zlib/buildlink3.mk" 17.include "../../devel/zlib/buildlink3.mk"
18.include "../../mk/bsd.pkg.mk" 18.include "../../mk/bsd.pkg.mk"
cvs diff -r1.1 -r1.2 pkgsrc/cad/veriwell/distinfo (expand / switch to unified diff)

--- pkgsrc/cad/veriwell/distinfo 2016/10/09 13:14:06 1.1
+++ pkgsrc/cad/veriwell/distinfo 2020/03/18 17:45:25 1.2
@@ -1,6 +1,7 @@ @@ -1,6 +1,7 @@
1$NetBSD: distinfo,v 1.1 2016/10/09 13:14:06 kamil Exp $ 1$NetBSD: distinfo,v 1.2 2020/03/18 17:45:25 joerg Exp $
2 2
3SHA1 (veriwell-2.8.7.tar.gz) = 9ef4e6a25a4fd65db325a89ed89b199547fabbd6 3SHA1 (veriwell-2.8.7.tar.gz) = 9ef4e6a25a4fd65db325a89ed89b199547fabbd6
4RMD160 (veriwell-2.8.7.tar.gz) = 3d86c40b353f701d61cab301e0f7c3ec136c88e7 4RMD160 (veriwell-2.8.7.tar.gz) = 3d86c40b353f701d61cab301e0f7c3ec136c88e7
5SHA512 (veriwell-2.8.7.tar.gz) = c0858ce71bd8cfef989e96899bc0d5fc0c919d8248cad0bebde7faf31073cde0423ddb168cf0fabb9f7b46ced7b953ad392627b7e1ad5ea1e7ef75f9524717a8 5SHA512 (veriwell-2.8.7.tar.gz) = c0858ce71bd8cfef989e96899bc0d5fc0c919d8248cad0bebde7faf31073cde0423ddb168cf0fabb9f7b46ced7b953ad392627b7e1ad5ea1e7ef75f9524717a8
6Size (veriwell-2.8.7.tar.gz) = 875596 bytes 6Size (veriwell-2.8.7.tar.gz) = 875596 bytes
 7SHA1 (patch-src_acc__user.h) = 308c237f63ecb8a856ab7640ea1e00a57ce34378
File Added: pkgsrc/cad/veriwell/patches/patch-src_acc__user.h
$NetBSD: patch-src_acc__user.h,v 1.1 2020/03/18 17:45:25 joerg Exp $

--- src/acc_user.h.orig	2020-03-18 16:17:15.862134072 +0000
+++ src/acc_user.h
@@ -30,10 +30,12 @@
 
 typedef int *handle;
 
+#ifndef __cplusplus
 #define bool int
 #define true 1
-#define TRUE 1
 #define false 0
+#endif
+#define TRUE 1
 #define FALSE 0
 
 #define global extern
@@ -41,7 +43,7 @@ typedef int *handle;
 #define local static
 #define null 0L
 
-extern bool acc_error_flag;
+extern int acc_error_flag;
 
 
 /**********************************************************************/