Sat Jan 16 16:49:36 2021 UTC ()
Provide the correct ASID and VA for the unaligned exception. This patch
has been applied upstream.
Bump PKGREVISION
(skrll)
diff -r1.69 -r1.70 pkgsrc/emulators/gxemul/Makefile
diff -r1.61 -r1.62 pkgsrc/emulators/gxemul/distinfo
diff -r0 -r1.1 pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__mips__instr__loadstore.cc
--- pkgsrc/emulators/gxemul/Makefile 2020/10/07 13:25:20 1.69
+++ pkgsrc/emulators/gxemul/Makefile 2021/01/16 16:49:36 1.70
@@ -1,7 +1,7 @@
-# $NetBSD: Makefile,v 1.69 2020/10/07 13:25:20 ryoon Exp $
+# $NetBSD: Makefile,v 1.70 2021/01/16 16:49:36 skrll Exp $
DISTNAME= gxemul-0.6.2
-PKGREVISION= 1
+PKGREVISION= 2
CATEGORIES= emulators
MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=gxemul/}
--- pkgsrc/emulators/gxemul/distinfo 2020/10/07 00:43:04 1.61
+++ pkgsrc/emulators/gxemul/distinfo 2021/01/16 16:49:36 1.62
@@ -1,10 +1,11 @@
-$NetBSD: distinfo,v 1.61 2020/10/07 00:43:04 thorpej Exp $
+$NetBSD: distinfo,v 1.62 2021/01/16 16:49:36 skrll Exp $
SHA1 (gxemul-0.6.2.tar.gz) = aabaeba783e70be952ab0056bf84d0f2b70c2155
RMD160 (gxemul-0.6.2.tar.gz) = ccac73d82446f89792b1fc803bee623813f3aab2
SHA512 (gxemul-0.6.2.tar.gz) = 4f389c509f9ecf39603ceed50e899e2bee285d3fefac9b3214076115ee71b5a7a68d1d92690b6debc8de5cf5f0303da83b3cc921a5c0b5eb4c7ad89baa730b59
Size (gxemul-0.6.2.tar.gz) = 5897883 bytes
SHA1 (patch-doc_networking.html) = dd7a1519a678196fd5a835317a32ba483630ece8
+SHA1 (patch-src_cpus_cpu__mips__instr__loadstore.cc) = 378c514ddf3b93279b2c479f21b77447d83d5afd
SHA1 (patch-src_devices_dev_dec21143.cc) = 52f36741038c76a2dbafc7da6737e816aed5c9f9
SHA1 (patch-src_devices_dev_ether.cc) = 00221e09530743e81faedcc75ee951fa853d0e2c
SHA1 (patch-src_devices_dev_le.cc) = a728e8008a7a9f33aaf95811a33ebac2cb86e80e
$NetBSD: patch-src_cpus_cpu__mips__instr__loadstore.cc,v 1.1 2021/01/16 16:49:36 skrll Exp $
--- src/cpus/cpu_mips_instr_loadstore.cc.orig 2021-01-16 16:33:52.314709654 +0000
+++ src/cpus/cpu_mips_instr_loadstore.cc
@@ -58,6 +58,30 @@ void LS_GENERIC_N(struct cpu *cpu, struc
/* Check alignment: */
if (addr & (LS_SIZE - 1)) {
#if 1
+ uint64_t vaddr_vpn2=0, vaddr_asid=0;
+
+ int exc_model = cpu->cd.mips.cpu_type.exc_model;
+ struct mips_coproc *cp0 = cpu->cd.mips.coproc[0];
+
+ if (exc_model == EXC3K) {
+ vaddr_asid = (cp0->reg[COP0_ENTRYHI] &
+ R2K3K_ENTRYHI_ASID_MASK) >>
+ R2K3K_ENTRYHI_ASID_SHIFT;
+ vaddr_vpn2 = (addr & R2K3K_ENTRYHI_VPN_MASK) >>
+ R2K3K_ENTRYHI_VPN_SHIFT;
+ } else {
+ vaddr_asid = cp0->reg[COP0_ENTRYHI] & ENTRYHI_ASID;
+
+ if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) {
+ vaddr_vpn2 = (addr &
+ ENTRYHI_VPN2_MASK_R10K) >>
+ ENTRYHI_VPN2_SHIFT;
+ } else {
+ vaddr_vpn2 = (addr & ENTRYHI_VPN2_MASK) >>
+ ENTRYHI_VPN2_SHIFT;
+ }
+ }
+
/* Cause an address alignment exception: */
mips_cpu_exception(cpu,
#ifdef LS_LOAD
@@ -65,7 +89,7 @@ void LS_GENERIC_N(struct cpu *cpu, struc
#else
EXCEPTION_ADES,
#endif
- 0, addr, 0, 0, 0, 0);
+ 0, addr, 0, vaddr_vpn2, vaddr_asid, 0);
#else
fatal("{ mips dyntrans alignment exception, size = %i,"
" addr = %016"PRIx64", pc = %016"PRIx64" }\n", LS_SIZE,