various updates for the new pkgsrc u-boot world order.

the whole u-boot package builds with the patches and distinfos
moved into the new places.


(mrg)

$NetBSD: distinfo-2020.04,v 1.1 2021/04/18 08:54:55 mrg Exp $

SHA1 (BPI-R2-HEAD1-512b.img) = ef5ae9707d39654b8d931a0bd8c0825318591e69
RMD160 (BPI-R2-HEAD1-512b.img) = 098f7c260353034a3d286d2113698c16605cd4b4
SHA512 (BPI-R2-HEAD1-512b.img) = cd37dd2c3e12033fbc9a4601ef6be54be70a3f6f19fedc79acbc246fc58e66bd1d1e492611632d3a5bb7bc3b8ed0f9900c7e218d4a15252eb7381d4da28af012
Size (BPI-R2-HEAD1-512b.img) = 1536 bytes
SHA1 (BPI-R2-HEAD440-0k.img) = a597caa991bcd9693e2f2223f9c247657a89187b
RMD160 (BPI-R2-HEAD440-0k.img) = a26ecd89e81aad4274fcf784c5fdcb214168273a
SHA512 (BPI-R2-HEAD440-0k.img) = 1d194649c21fb922f2b0e2f59edbf41dc22c260580a8f25aee0fa1d4ec1cbb7b3a9bf8dc56c9743ec8676b408d4109c2026001b105b1d3caef819b95ca360451
Size (BPI-R2-HEAD440-0k.img) = 440 bytes
SHA1 (preloader_iotg7623Np1_sd_1600M.bin) = 51f2d73d6e1e47f9b961ec86b1cd624c8bc5e5d9
RMD160 (preloader_iotg7623Np1_sd_1600M.bin) = bd13434a35e35ef334fb713ea5d2caec7ca0f663
SHA512 (preloader_iotg7623Np1_sd_1600M.bin) = 5a5f580956ed9cc558c4b8b75f9dbeba6299d9950bbdbae8f5064d1d60ae7cb42ff89c9dd7f1bddebb955183780f88a731d8c2b71d61970c07e8356a9cc093a5
Size (preloader_iotg7623Np1_sd_1600M.bin) = 91996 bytes
SHA1 (u-boot-2020.04.tar.bz2) = 0821ce2dac9bbd9ec5883779ddad78b8610366e3
RMD160 (u-boot-2020.04.tar.bz2) = 8f13836ea4d9d7235aa83f6b713b76e047ce27f1
SHA512 (u-boot-2020.04.tar.bz2) = e04fe54883149123730605b084324ac0d1d72ce6913467bbe587a5a2675bcf7bb393405d9a446dc0c64ba42abc1e862ae5a132e9e51aa7390e2e9fce045af8d8
Size (u-boot-2020.04.tar.bz2) = 15065656 bytes
SHA1 (patch-include_configs_mt7623.h) = 47cf1bd28c15fb54fd86e135afbaf1495c5acbb1
SHA1 (patch-include_image.h) = 46f9efc0b9bbeea407e18f2b7e02b265dc0b58e1

$NetBSD: patch-arch_arm_cpu_armv8_Kconfig,v 1.1 2021/04/18 08:54:55 mrg Exp $

--- arch/arm/cpu/armv8/Kconfig.orig	2018-08-06 22:28:00.000000000 +0000
+++ arch/arm/cpu/armv8/Kconfig
@@ -130,6 +130,10 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
 	  A value 0 or no definition of it works for single cluster system.
 	  System with multi-cluster should difine their own exact value.
 
+config ARMV8_SWITCH_TO_EL1
+	bool "Switch to EL1 before booting kernel"
+	default n
+
 if SYS_HAS_ARMV8_SECURE_BASE
 
 config ARMV8_SECURE_BASE

$NetBSD: patch-lib_bch.c,v 1.1 2021/04/18 08:54:55 mrg Exp $

u-boot: fix build on macos

--- lib/bch.c.orig	2018-08-06 22:28:00.000000000 +0000
+++ lib/bch.c
@@ -61,8 +61,10 @@
 #include <linux/bitops.h>
 #else
 #include <errno.h>
-#if defined(__FreeBSD__)
+#if defined(__FreeBSD__) || defined(__NetBSD__)
 #include <sys/endian.h>
+#elif defined(__APPLE__)
+#include <machine/endian.h>
 #else
 #include <endian.h>
 #endif
@@ -71,7 +73,11 @@
 #include <string.h>
 
 #undef cpu_to_be32
+#if defined(__APPLE__)
+#define cpu_to_be32 htonl
+#else
 #define cpu_to_be32 htobe32
+#endif
 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
 #define kmalloc(size, flags)	malloc(size)
 #define kzalloc(size, flags)	calloc(1, size)
@@ -117,7 +123,7 @@ struct gf_poly_deg1 {
 };
 
 #ifdef USE_HOSTCC
-#if !defined(__DragonFly__) && !defined(__FreeBSD__)
+#if !defined(__DragonFly__) && !defined(__FreeBSD__) && !defined(__APPLE__)
 static int fls(int x)
 {
 	int r = 32;

$NetBSD: patch-arch_arm_cpu_armv8_Kconfig,v 1.1 2021/04/18 08:54:55 mrg Exp $

--- arch/arm/cpu/armv8/Kconfig.orig	2018-01-23 06:50:34.000000000 +0000
+++ arch/arm/cpu/armv8/Kconfig
@@ -132,6 +132,10 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
 	  A value 0 or no definition of it works for single cluster system.
 	  System with multi-cluster should difine their own exact value.
 
+config ARMV8_SWITCH_TO_EL1
+	bool "Switch to EL1 before booting kernel"
+	default n
+
 if SYS_HAS_ARMV8_SECURE_BASE
 
 config ARMV8_SECURE_BASE

$NetBSD: patch-lib_bch.c,v 1.1 2021/04/18 08:54:55 mrg Exp $

--- lib/bch.c.orig	2018-01-23 06:50:34.000000000 +0000
+++ lib/bch.c
@@ -61,8 +61,11 @@
 #include <linux/bitops.h>
 #else
 #include <errno.h>
-#if defined(__FreeBSD__)
+#if defined(__FreeBSD__) || defined(__NetBSD__)
 #include <sys/endian.h>
+#elif defined(__APPLE__)
+#include <machine/endian.h>
+#define htobe32 htonl
 #else
 #include <endian.h>
 #endif
@@ -117,7 +120,7 @@ struct gf_poly_deg1 {
 };
 
 #ifdef USE_HOSTCC
-#if !defined(__DragonFly__) && !defined(__FreeBSD__)
+#if !defined(__DragonFly__) && !defined(__FreeBSD__) && !defined(__APPLE__)
 static int fls(int x)
 {
 	int r = 32;

$NetBSD: patch-arch_arm_dts_Makefile,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

diff --git arch/arm/dts/Makefile arch/arm/dts/Makefile
index 5a64fcc5a7..affedfd666 100644
--- arch/arm/dts/Makefile
+++ arch/arm/dts/Makefile
@@ -116,6 +116,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 	rk3399-nanopi-m4.dtb \
 	rk3399-nanopi-neo4.dtb \
 	rk3399-orangepi.dtb \
+	rk3399-pinebook-pro.dtb \
 	rk3399-puma-ddr1333.dtb \
 	rk3399-puma-ddr1600.dtb \
 	rk3399-puma-ddr1866.dtb \

$NetBSD: patch-arch_arm_dts_rk3399-pinebook-pro-u-boot.dtsi,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

diff --git arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
new file mode 100644
index 0000000000..9b0cb7010f
--- /dev/null
+++ arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+	};
+};
+
+&pmugrf {
+	u-boot,dm-pre-reloc;
+};
+
+&spiflash {
+        u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+        u-boot,dm-pre-reloc;
+};

$NetBSD: patch-arch_arm_dts_rk3399-pinebook-pro.dts,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

commit 2778aa7cb70946c4729ed6ae13dea5bd1cc688dc
Author: dhivael <dhivael.git@eno.space>
Date:   Sat Jan 11 15:02:44 2020 +0100

    rk3399: pinebook: fix sdcard boot from emmc
    
    booting from emmc does not set all DT properties required for the sd
    slot to function properly. this is a copy of the linux DT configuration
    for the slot now.

commit fd41e9330cf1635fa3bf4dabdfac42ee1bba963c
Author: Emmanuel Vadot <manu@freebsd.org>
Date:   Tue Dec 31 22:13:03 2019 +0100

     PBP: Add regulator needed for usb
    
    The schematics indicate that the vcc3v3_s0 voltage is controlled by
    the LDO2 of the RK808 but this isn't true.
    It's controller by a gpio (named lcdvcc_en).
    Remove the name from the RK808 regulator and add a regulator-fixed
    controller by this gpio.
    
    Signed-off-by: Emmanuel Vadot <manu@freebsd.org>


--- arch/arm/dts/rk3399-pinebook-pro.dts.orig	2020-01-13 16:59:26.353181190 -0800
+++ arch/arm/dts/rk3399-pinebook-pro.dts	2020-01-13 23:16:08.263344492 -0800
@@ -0,0 +1,660 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "Pine64 Pinebook Pro";
+	compatible = "pine64,pinebook-pro", "rockchip,rk3399";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	aliases {
+		spi0 = &spi1;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pwms = <&pwm0 0 740740 0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwrbtn>;
+
+		power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	/*
+	leds {
+		status = "okay";
+		compatible = "gpio-leds";
+
+		work-led {
+			label = "work";
+			gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		};
+
+		standby-led {
+			label = "standby";
+			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+		};
+	};
+	*/
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		power-off-delay-us = <500000>;
+		post-power-on-delay-ms = <100>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+
+	/* switched by pmic_sleep */
+	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc5v0_host";
+	};
+
+	vcc5v0_usb3_host: vcc5v0-usb3-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_usb3_drv>;
+		regulator-name = "vcc5v0_usb3_host";
+		regulator-always-on;
+	};
+
+	vcc3v3_s0: vcc3v3-s0-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcdvcc_en>;
+		regulator-name = "vcc3v3_s0";
+		regulator-always-on;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-init-microvolt = <950000>;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc_sys>;
+		vcc10-supply = <&vcc_sys>;
+		vcc11-supply = <&vcc_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_touch: LDO_REG2 {
+				regulator-name = "vcc3v0_touch";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			unused: SWITCH_REG2 {
+				regulator-name = "SWITCH_REG2";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_gpio>;
+		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_gpio>;
+		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+};
+
+&i2c4 {
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+
+	fusb0: typec-portc@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		vbus-supply = <&vcc5v0_usb3_host>;
+		status = "okay";
+	};
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc1v8_dvp>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	pmu1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&pinctrl {
+	buttons {
+		pwrbtn: pwrbtn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	fusb302x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_gpio: vsel1-gpio {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_gpio: vsel2-gpio {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb-typec {
+		vcc5v0_typec_en: vcc5v0_typec_en {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		host_usb3_drv: host-usb3-drv {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		/* Shared between LCD and usb */
+		lcdvcc_en: lcdvcc-en {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	sd-uhs-sdr104;
+	max-frequency = <20000000>;
+	vqmmc-supply = <&vcc_sdio>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <25000000>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	phy-supply = <&vcc3v3_s0>;
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	phy-supply = <&vcc3v3_s0>;
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&spi1 {
+	status = "okay";
+
+	spiflash: spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <10000000>;
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			loader@8000 {
+				label = "loader";
+				reg = <0x0 0x3F8000>;
+			};
+
+			env@3f8000 {
+				label = "env";
+				reg = <0x3F8000 0x8000>;
+			};
+
+			vendor@7c0000 {
+				label = "vendor";
+				reg = <0x7C0000 0x40000>;
+			};
+		};
+	};
+};

$NetBSD: patch-arch_arm_mach-rockchip_rk3399_Kconfig,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

--- arch/arm/mach-rockchip/rk3399/Kconfig.orig	2019-12-16 04:39:56.000000000 -0800
+++ arch/arm/mach-rockchip/rk3399/Kconfig	2020-01-03 09:31:11.465329801 -0800
@@ -81,6 +81,13 @@
 	   * GPIO expansion ports
 	   * DC 12V/2A
 
+config TARGET_PINEBOOK_PRO_RK3399
+	bool "Pinebook Pro"
+	help
+	  Pinebook Pro is a laptop based on the Rockchip rk3399 SoC
+	  with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port,
+	  1920*1080 screen and all the usual laptop features.
+
 endchoice
 
 config ROCKCHIP_BOOT_MODE_REG
@@ -113,6 +120,7 @@
 config SPL_STACK_R_ADDR
 	default 0x04000000
 
+source "board/pine64/pinebook_pro_rk3399/Kconfig"
 source "board/rockchip/evb_rk3399/Kconfig"
 source "board/theobroma-systems/puma_rk3399/Kconfig"
 source "board/vamrs/rock960_rk3399/Kconfig"

$NetBSD: patch-arch_arm_mach-rockchip_rk3399_rk3399.c,v 1.1 2021/04/18 08:54:55 mrg Exp $

adjusted by mrg to restrict to CONFIG_TARGET_PINEBOOK_PRO_RK3399.


Author: dhivael <dhivael.git@eno.space>
Date:   Sat Jan 11 15:04:46 2020 +0100

    rk3399: light pinebook power and standby leds during early boot
    
    this is a hack, but it works for now.


--- arch/arm/mach-rockchip/rk3399/rk3399.c.orig	2019-12-16 04:39:56.000000000 -0800
+++ arch/arm/mach-rockchip/rk3399/rk3399.c	2020-01-13 23:15:15.174280309 -0800
@@ -15,6 +15,8 @@
 #include <asm/arch-rockchip/grf_rk3399.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <power/regulator.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -117,6 +119,9 @@
 	struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
 	struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
 #endif
+#ifdef CONFIG_TARGET_PINEBOOK_PRO_RK3399
+	struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
+#endif
 
 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
 	/* Enable early UART0 on the RK3399 */
@@ -149,6 +154,16 @@
 	spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
 
+#ifdef CONFIG_TARGET_PINEBOOK_PRO_RK3399
+	{
+		// set GPIO0_A2/B3 to GPIO_ACTIVE_HIGH
+		// set GPIO0_A2/B3 to OUTPUT
+		int mask = (1UL << RK_PA2) | (1UL << RK_PB3);
+		setbits_le32(&gpio->swport_dr, mask);
+		setbits_le32(&gpio->swport_ddr, mask);
+	}
+#endif
+
 	/* Enable early UART2 channel C on the RK3399 */
 	rk_clrsetreg(&grf->gpio4c_iomux,
 		     GRF_GPIO4C3_SEL_MASK,

$NetBSD: patch-board_pine64_pinebook_pro_rk3399_Kconfig,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

diff --git board/pine64/pinebook_pro_rk3399/Kconfig board/pine64/pinebook_pro_rk3399/Kconfig
new file mode 100644
index 0000000000..c37c643d6f
--- /dev/null
+++ board/pine64/pinebook_pro_rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PINEBOOK_PRO_RK3399
+
+config SYS_BOARD
+	default "pinebook_pro_rk3399"
+
+config SYS_VENDOR
+	default "pine64"
+
+config SYS_CONFIG_NAME
+	default "pinebook_pro_rk3399"
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+
+endif

$NetBSD: patch-board_pine64_pinebook_pro_rk3399_MAINTAINERS,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

diff --git board/pine64/pinebook_pro_rk3399/MAINTAINERS board/pine64/pinebook_pro_rk3399/MAINTAINERS
new file mode 100644
index 0000000000..58400ebd28
--- /dev/null
+++ board/pine64/pinebook_pro_rk3399/MAINTAINERS
@@ -0,0 +1,8 @@
+PINEBOOK_PRO
+M:	Peter Robinson <pbrobinson at gmail.com>
+S:	Maintained
+F:	board/pine64/pinebook_pro_rk3399/
+F:	include/configs/pinebook_pro_rk3399.h
+F:	arch/arm/dts/rk3399-pinebook-pro.dts
+F:	arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
+F:	configs/pinebook_pro-rk3399_defconfig

$NetBSD: patch-board_pine64_pinebook_pro_rk3399_Makefile,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

diff --git board/pine64/pinebook_pro_rk3399/Makefile board/pine64/pinebook_pro_rk3399/Makefile
new file mode 100644
index 0000000000..2f692a12a6
--- /dev/null
+++ board/pine64/pinebook_pro_rk3399/Makefile
@@ -0,0 +1 @@
+obj-y	+= pinebook-pro-rk3399.o

$NetBSD: patch-board_pine64_pinebook_pro_rk3399_pinebook-pro-rk3399.c,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

diff --git board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c
new file mode 100644
index 0000000000..b1a2ed3b77
--- /dev/null
+++ board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <syscon.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-internal.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+#include <asm/arch-rockchip/periph.h>
+#include <power/regulator.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+#define RK3399_CPUID_OFF  0x7
+#define RK3399_CPUID_LEN  0x10
+
+static int fix_lcd_backling_pull_mode(void)
+{
+#include <asm/arch-rockchip/grf_rk3399.h>
+
+#define PMU_GRF_BASE	0xff320000
+
+	// set pull of GPIO1_A0
+	struct rk3399_pmugrf_regs * const pmugrf = (void *)PMU_GRF_BASE;
+	rk_clrsetreg(&pmugrf->gpio1_p[0], 3 << (2 * 0), 0 << (2 * 0));
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int board_early_init_f(void)
+{
+	struct udevice *regulator;
+	int ret;
+
+	ret = regulator_get_by_platname("vcc5v0_host", &regulator);
+	if (ret) {
+		debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
+		goto out;
+	}
+
+	ret = regulator_set_enable(regulator, true);
+	if (ret)
+		debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret);
+
+	fix_lcd_backling_pull_mode();
+
+out:
+	return 0;
+}
+#endif
+
+static void setup_serial(void)
+{
+#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
+	struct udevice *dev;
+	int ret, i;
+	u8 cpuid[RK3399_CPUID_LEN];
+	u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2];
+	char cpuid_str[RK3399_CPUID_LEN * 2 + 1];
+	u64 serialno;
+	char serialno_str[16];
+
+	/* retrieve the device */
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_GET_DRIVER(rockchip_efuse), &dev);
+	if (ret) {
+		debug("%s: could not find efuse device\n", __func__);
+		return;
+	}
+
+	/* read the cpu_id range from the efuses */
+	ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid));
+	if (ret) {
+		debug("%s: reading cpuid from the efuses failed\n",
+		      __func__);
+		return;
+	}
+
+	memset(cpuid_str, 0, sizeof(cpuid_str));
+	for (i = 0; i < 16; i++)
+		sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
+
+	debug("cpuid: %s\n", cpuid_str);
+
+	/*
+	 * Mix the cpuid bytes using the same rules as in
+	 *   ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
+	 */
+	for (i = 0; i < 8; i++) {
+		low[i] = cpuid[1 + (i << 1)];
+		high[i] = cpuid[i << 1];
+	}
+
+	serialno = crc32_no_comp(0, low, 8);
+	serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
+	snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
+
+	env_set("cpuid#", cpuid_str);
+	env_set("serial#", serialno_str);
+#endif
+
+	return;
+}
+
+#define GRF_IO_VSEL_BT565_SHIFT 0
+#define PMUGRF_CON0_VSEL_SHIFT 8
+
+#ifdef CONFIG_MISC_INIT_R
+static void setup_iodomain(void)
+{
+	struct rk3399_grf_regs *grf =
+	   syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	struct rk3399_pmugrf_regs *pmugrf =
+	   syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+	/* BT565 is in 1.8v domain */
+	rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
+
+	/* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
+	rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
+}
+
+int misc_init_r(void)
+{
+	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_length = 0x10;
+	u8 cpuid[cpuid_length];
+	int ret;
+
+	setup_iodomain();
+
+	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+	if (ret)
+		return ret;
+
+	ret = rockchip_cpuid_set(cpuid, cpuid_length);
+	if (ret)
+		return ret;
+
+	ret = rockchip_setup_macaddr();
+
+	setup_serial();
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *serial_string;
+	u64 serial = 0;
+
+	serial_string = env_get("serial#");
+
+	if (serial_string)
+		serial = simple_strtoull(serial_string, NULL, 16);
+
+	serialnr->high = (u32)(serial >> 32);
+	serialnr->low = (u32)(serial & 0xffffffff);
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = 0xfe800000,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.dis_u2_susphy_quirk = 1,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	return dwc3_uboot_init(&dwc3_device_data);
+}
+#endif

$NetBSD: patch-configs-pinebook_pro-rk3399_defconfig,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

reduce pinebook_pro bootdelay to 2
put uboot at 256K.


--- configs/pinebook_pro-rk3399_defconfig.orig	2020-01-13 16:59:26.374914888 -0800
+++ configs/pinebook_pro-rk3399_defconfig	2020-01-13 23:15:39.294542172 -0800
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_PINEBOOK_PRO_RK3399=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_BOOTDELAY=2
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USB_XHCI_ROCKCHIP is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

$NetBSD: patch-configs_rock64-rk3328_defconfig,v 1.1 2021/04/18 08:54:55 mrg Exp $

Put u-boot at 256KB.

--- configs/rock64-rk3328_defconfig.orig	2019-12-16 04:39:56.000000000 -0800
+++ configs/rock64-rk3328_defconfig	2020-01-09 12:47:03.348721688 -0800
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_ROCKCHIP_RK3328=y
 CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_TPL_LIBCOMMON_SUPPORT=y

$NetBSD: patch-configs_rockpro64-rk3399_defconfig,v 1.1 2021/04/18 08:54:55 mrg Exp $

Put u-boot at 256KB.

--- configs/rockpro64-rk3399_defconfig.orig	2019-12-16 04:39:56.000000000 -0800
+++ configs/rockpro64-rk3399_defconfig	2020-01-09 12:44:48.889763217 -0800
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_TARGET_ROCKPRO64_RK3399=y

$NetBSD: patch-include-configs-pinebook_pro_rk3399.h,v 1.1 2021/04/18 08:54:55 mrg Exp $

Pinebook Pro support from https://patchwork.ozlabs.org/patch/1194525/

diff --git include/configs/pinebook_pro_rk3399.h include/configs/pinebook_pro_rk3399.h
new file mode 100644
index 0000000000..f383becbf8
--- /dev/null
+++ include/configs/pinebook_pro_rk3399.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd
+ * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __PINEBOOKPRO_RK3399_H
+#define __PINEBOOKPRO_RK3399_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdin=serial,usbkbd\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3399_common.h>
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#endif
+
+#undef CONFIG_SYS_SPI_U_BOOT_OFFS
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	1024 * 512
+
+#define SDRAM_BANK_SIZE			(2UL << 30)
+
+#endif

$NetBSD: patch-include_configs_rockchip-common.h,v 1.1 2021/04/18 08:54:55 mrg Exp $

Author: dhivael <dhivael.git@eno.space>
Date:   Sat Jan 11 15:04:04 2020 +0100

    rockchip: move usb0 after mmc1 in default boot order
	
    now that we support booting from USB we should prefer USB boot over eMMC
    boot. we still try to boot from SD cards first.

commit 908d441fefc2203affe1bb0d79f75f611888fc1f
Author: dhivael <dhivael.git@eno.space>
Date:   Sat Jan 11 15:04:04 2020 +0100

    rockchip: move usb0 after mmc1 in default boot order
    
    now that we support booting from USB we should prefer USB boot over eMMC
    boot. we still try to boot from SD cards first.


--- include/configs/rockchip-common.h.orig	2019-12-16 04:39:56.000000000 -0800
+++ include/configs/rockchip-common.h	2020-01-13 23:17:05.743249968 -0800
@@ -13,11 +13,10 @@
 
 /* First try to boot from SD (index 0), then eMMC (index 1) */
 #if CONFIG_IS_ENABLED(CMD_MMC)
-	#define BOOT_TARGET_MMC(func) \
-		func(MMC, mmc, 0) \
-		func(MMC, mmc, 1)
+	#define BOOT_TARGET_MMC(func, idx) \
+		func(MMC, mmc, idx)
 #else
-	#define BOOT_TARGET_MMC(func)
+	#define BOOT_TARGET_MMC(func, idx)
 #endif
 
 #if CONFIG_IS_ENABLED(CMD_USB)
@@ -39,8 +38,9 @@
 #endif
 
 #define BOOT_TARGET_DEVICES(func) \
-	BOOT_TARGET_MMC(func) \
+	BOOT_TARGET_MMC(func, 1) \
 	BOOT_TARGET_USB(func) \
+	BOOT_TARGET_MMC(func, 0) \
 	BOOT_TARGET_PXE(func) \
 	BOOT_TARGET_DHCP(func)
 

$NetBSD: patch-include_configs_mt7623.h,v 1.1 2021/04/18 08:54:55 mrg Exp $

Set the bootm_size, kernel_addr_r, fdt_addr_r, scriptaddr, pxefile_addr_r,
ramdisk_addr_r, and fdtfile environment varibles.

--- include/configs/mt7623.h.orig	2020-04-13 15:02:18.000000000 +0000
+++ include/configs/mt7623.h	2020-06-20 17:33:23.538928996 +0000
@@ -42,14 +42,39 @@
 #define MMC_SUPPORTS_TUNING
 
 /* DRAM */
+#define SDRAM_OFFSET(x) 0x8##x
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 
 /* This is needed for kernel booting */
 #define FDT_HIGH			"fdt_high=0xac000000\0"
 
+/*
+ * 128M RAM (256M minimum minus 64MB heap + 64MB for u-boot, stack, fb, etc.
+ * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end.
+ */
+#define BOOTM_SIZE     __stringify(0xa000000)
+#define KERNEL_ADDR_R  __stringify(SDRAM_OFFSET(4000000))
+#define FDT_ADDR_R     __stringify(SDRAM_OFFSET(5000000))
+#define SCRIPT_ADDR_R  __stringify(SDRAM_OFFSET(5100000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(5200000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(5300000))
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=" BOOTM_SIZE "\0" \
+	"kernel_addr_r=" KERNEL_ADDR_R "\0" \
+	"fdt_addr_r=" FDT_ADDR_R "\0" \
+	"scriptaddr=" SCRIPT_ADDR_R "\0" \
+	"pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
+	"ramdisk_addr_r=" RAMDISK_ADDR_R "\0"
+
+#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+
 /* Extra environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS	\
-	FDT_HIGH
+	FDT_HIGH \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"fdtfile=" FDTFILE "\0"
 
 /* Ethernet */
 #define CONFIG_IPADDR			192.168.1.1

$NetBSD: patch-include_image.h,v 1.1 2021/04/18 08:54:55 mrg Exp $

Ensure the correct byte order macros are used when image.h is included
in a host tool.

--- include/image.h.orig	2020-06-20 13:48:00.000000000 +0000
+++ include/image.h	2020-06-20 13:51:12.000000000 +0000
@@ -16,7 +16,6 @@
 #define __IMAGE_H__
 
 #include "compiler.h"
-#include <asm/byteorder.h>
 #include <stdbool.h>
 
 /* Define this to avoid #ifdefs later on */
@@ -26,6 +25,13 @@ struct fdt_region;
 #ifdef USE_HOSTCC
 #include <sys/types.h>
 
+#include <endian.h>
+#if _BYTE_ORDER == _BIG_ENDIAN
+#  include <linux/byteorder/big_endian.h>
+#else
+#  include <linux/byteorder/little_endian.h>
+#endif
+
 /* new uImage format support enabled on host */
 #define IMAGE_ENABLE_FIT	1
 #define IMAGE_ENABLE_OF_LIBFDT	1
@@ -40,6 +46,7 @@ struct fdt_region;
 
 #else
 
+#include <asm/byteorder.h>
 #include <lmb.h>
 #include <asm/u-boot.h>
 #include <command.h>