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2009-07-14 copyright

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## Starting application at 0x21000000 ...

NetBSD/evbarm STR81xx/91xx
physmemory: 8192 pages at 0x00000000 -> 0x01ffffff
freestart = 0x002a2000, free_pages = 7518 (0x00001d5e)
Allocating page tables
initarm: kernel_l1pt: 0xc02a4000:0x2a4000
initarm: kernel_pt_table:
        0xc02a2000:0x2a2000
        0xc02a3000:0x2a3000
        0xc02a8000:0x2a8000
        0xc02a9000:0x2a9000
        0xc02aa000:0x2aa000
        0xc02ab000:0x2ab000
        0xc02ac000:0x2ac000
        0xc02ad000:0x2ad000
        0xc02ae000:0x2ae000
        0xc02af000:0x2af000
        0xc02b0000:0x2b0000
        0xc02b1000:0x2b1000
        0xc02b2000:0x2b2000
        0xc02b3000:0x2b3000
        0xc02b4000:0x2b4000
FIQ stack: p0x002b6000 v0xc02b6000
IRQ stack: p0x002b7000 v0xc02b7000
ABT stack: p0x002b8000 v0xc02b8000
UND stack: p0x002b9000 v0xc02b9000
SVC stack: p0x002ba000 v0xc02ba000
Creating L1 page table at 0x002a4000
Mapping kernel
Constructing L2 page tables
Mapping the vector page
switching to new L1 page table  @0x2a4000...done.
init subsystems: stacks vectors undefined page pmap irq done.
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 5.99.15 (STR81xx) #305: Tue Jul 14 21:19:27 JST 2009
        ryo@falsie:/src/cvs/NetBSD/sys/arch/evbarm/compile/STR81xx
total memory = 32768 KB
avail memory = 28612 KB
mainbus0 (root)
cpu0 at mainbus0: FA526 rev 1 (ARMv4 core)
cpu0: DC disabled IC enabled WB enabled LABT
cpu0: 8KB/16B 2-way Instruction cache
cpu0: 8KB/16B 2-way write-back-locking-B Data cache
panic: config_devalloc: star
Stopped in pid 0.1 (system) at  netbsd:cpu_Debugger+0x4:        mov     r15, r14

db> 
db> 
db> reboot

The operating system has halted.
Please press any key to reboot.

rebooting...

CPUのデータキャッシュ(CPU_CONTROL_DC_ENABLE)をOFFにしたら動いた。
そもそもNetBSDのFA526サポートはちゃんと動いてるのか疑惑ががが

ちなみにdata cache enableのままだと、vmをallocした個所を触ってfaultしてdata_abort_handler内でpmapがTLB埋めてreturnした後、再度同じアドレスでfault、という風にループしてた。
TLB設定した後にcache invalidateしてやればcache enableでも動くんじゃなかろうか。まぁいいや。些末な問題っぽいので後にしよ。
…というか動かなかったのオレジャネーーーーーーーーーーーーーー!!!!!!!

panic: config_devalloc: star は何かポカしてるだけだろう。
さて、これでやっと割り込みで遊べるお。


EOF