/* $NetBSD$ */ /*- * Copyright (c) 2009 SHIMIZU Ryo * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _STARREG_H_ #define _STARREG_H_ /* * Reference: * - Equuleus Series: STR813X/CNS213X, STR818X/CNS218X Network Access Processor DataSheet * http://www.cnusers.org/index.php?option=com_remository&Itemid=32&func=fileinfo&id=96 * * - Orion Series: STR91XX/CNS11XX Broadband Home Gateway Processor Data Sheet * http://www.cnusers.org/index.php?option=com_remository&Itemid=32&func=fileinfo&id=77 */ #define STAR_PCLK 43750000 /* PCLK=43.75MHz */ /* * STR81xx, STR91xx Memory Map */ #define STRxxxx_ALIAS_MEMORY 0x00000000 /* STR81xx, STR91xx */ #define STR91xx_FLASH_SRAM_MEMORY 0x10000000 /* --- , STR91xx */ #define STR81xx_FLASH_SRAM_MEMORY_BANK0 0x10000000 /* STR81xx, --- */ #define STR81xx_FLASH_SRAM_MEMORY_BANK1 0x11000000 /* STR81xx, --- */ #define STR81xx_FLASH_SRAM_MEMORY_BANK2 0x12000000 /* STR81xx, --- */ #define STR81xx_FLASH_SRAM_MEMORY_BANK3 0x13000000 /* STR81xx, --- */ #define STR81xx_IDE_DEVICE_REGISTER_SPACE 0x18000000 /* STR81xx, --- */ #define STRxxxx_DDR_SDRAM_MEMORY 0x20000000 /* STR81xx, STR91xx */ #define STR81xx_SPI_SERIAL_FLASH_MEMORY 0x30000000 /* STR81xx, --- */ #define STR91xx_STATIC_MEMORY_CONTROL_REGISTER 0x30000000 /* --- , STR91xx */ #define STR91xx_DDR_SDRAM_CONTROL_REGISTER 0x40000000 /* --- , STR91xx */ #define STRxxxx_GENERIC_DMA_REGISTER 0x60000000 /* STR81xx, STR91xx */ #define STR81xx_NIC_REGISTER 0x70000000 /* STR81xx, --- */ #define STR91xx_SWITCH_AND_HNAT_REGISTER 0x70000000 /* --- , STR91xx */ #define STR81xx_SPI_PCM_TWI_IS_REGISTER 0x71000000 /* STR81xx, --- */ #define STR81xx_SDR_DDR_SDRAM_CONTROL_REGISTER 0x72000000 /* STR81xx, --- */ #define STR81xx_STATIC_MEMORY_CONTROL_REGISTER 0x73000000 /* STR81xx, --- */ #define STR81xx_IDE_CONTROL_REGISTER 0x74000000 /* STR81xx, --- */ #define STRxxxx_MISC_REGISTER 0x76000000 /* STR81xx, STR91xx */ #define STRxxxx_POWER_MANAGEMENT_REGISTER 0x77000000 /* STR81xx, STR91xx */ #define STRxxxx_UART0_REGISTER 0x78000000 /* STR81xx, STR91xx */ #define STR81xx_UART1_REGISTER 0x78800000 /* STR81xx, --- */ #define STRxxxx_TIMER_REGISTER 0x79000000 /* STR81xx, STR91xx */ #define STRxxxx_WATCH_DOG_TIMER_REGISTER 0x7A000000 /* STR81xx, STR91xx */ #define STRxxxx_REAL_TIME_CLOCK_REGISTER 0x7B000000 /* STR81xx, STR91xx */ #define STRxxxx_GPIOA_REGISTER 0x7C000000 /* STR81xx, STR91xx */ #define STR81xx_GPIOB_REGISTER 0x7C800000 /* STR81xx, --- */ #define STR91xx_INTERRUPT_CONTROL_REGISTER 0x7D000000 /* --- , STR91xx */ #define STR91xx_PCMCIA_CONTROL_REGISTER 0x80000000 /* --- , STR91xx */ #define STR91xx_PCMCIA_ATTRIBUTE_MEMORY 0x90000000 /* --- , STR91xx */ #define STR91xx_PCMCIA_COMMON_MEMORY 0x94000000 /* --- , STR91xx */ #define STR91xx_PCMCIA_IO_SPACE 0x98000000 /* --- , STR91xx */ #define STRxxxx_PCI_CONFIGURATION_DATA_REGISTER 0xA0000000 /* STR81xx, STR91xx */ #define STRxxxx_PCI_CONFIGURATION_ADDR_REGISTER 0xA4000000 /* STR81xx, STR91xx */ #define STRxxxx_PCI_IO_SPACE 0xA8000000 /* STR81xx, STR91xx */ #define STRxxxx_PCI_MEMORY_SPACE 0xB0000000 /* STR81xx, STR91xx */ #define STRxxxx_USB11_CONFIGURATION_REGISTER 0xC0000000 /* STR81xx, STR91xx */ #define STRxxxx_USB11_OPERATION_REGISTER 0xC4000000 /* STR81xx, STR91xx */ #define STRxxxx_USB20_CONFIGURATION_REGISTER 0xC8000000 /* STR81xx, STR91xx */ #define STRxxxx_USB20_OPERATION_REGISTER 0xCC000000 /* STR81xx, STR91xx */ #define STR81xx_USB11_20_DEVICE_REGISTER 0xD0000000 /* STR81xx, --- */ #define STR81xx_INTERRUPT_CONTROL_REGISTER 0xFFFFF000 /* STR81xx, --- */ /* * Peripheral Interrupts Source Mapping */ #define STAR_IRQ_TIMER1 0 /* STR81xx, STR91xx */ #define STAR_IRQ_TIMER2 1 /* STR81xx, STR91xx */ #define STAR_IRQ_CPUFREQ_CLKPWR 2 /* STR81xx, STR91xx */ #define STAR_IRQ_WDOG 3 /* STR81xx, STR91xx */ #define STAR_IRQ_GPIO 4 /* STR81xx, STR91xx */ #define STAR_IRQ_PCIEXT0 5 /* STR81xx, STR91xx */ #define STAR_IRQ_PCIEXT1 6 /* STR81xx, STR91xx */ #define STAR_IRQ_PCIEXT2 7 /* STR81xx, STR91xx */ #define STAR_IRQ_PCIBRIDGE 8 /* STR81xx, STR91xx */ #define STAR_IRQ_UART0 9 /* STR81xx, --- */ #define STAR_IRQ_UART1 10 /* STR81xx, STR91xx */ #define STAR_IRQ_DMA 11 /* STR81xx, STR91xx */ #define STAR_IRQ_DMAERR 12 /* STR81xx, STR91xx */ #define STAR_IRQ_PCMCIA 13 /* --- , STR91xx */ #define STAR_IRQ_RTC 14 /* STR81xx, STR91xx */ #define STAR_IRQ_PCM_EXTINT 15 /* STR81xx , STR91xx */ #define STAR_IRQ_USB 16 /* STR81xx, --- */ #define STAR_IRQ_IDE 17 /* STR81xx, --- */ #define STAR_IRQ_NIC_MIB 18 /* STR81xx, STR91xx */ #define STAR_IRQ_NIC_TX 19 /* STR81xx, STR91xx */ #define STAR_IRQ_NIC_RX 20 /* STR81xx, STR91xx */ #define STAR_IRQ_NIC_EMPTY 21 /* STR81xx, STR91xx */ #define STAR_IRQ_NIC_FULL 22 /* STR81xx, STR91xx */ #define STAR_IRQ_USB11 23 /* STR81xx, STR91xx */ #define STAR_IRQ_USB20 24 /* STR81xx, STR91xx */ #define STAR_IRQ_I2S 25 /* STR81xx, --- */ #define STAR_IRQ_SPI 26 /* STR81xx, --- */ #define STAR_IRQ_TWI 27 /* STR81xx, --- */ #define STAR_IRQ_USB_VBUS 28 /* STR81xx, --- */ #define STAR_IRQ_EXT_GPIOA0 29 /* STR81xx, --- */ #define STAR_IRQ_EXT_GPIOA1 30 /* STR81xx, --- */ #define STAR_IRQ_HSDMA 31 /* STR81xx, --- */ #define STAR_IRQ_START 0 #define STAR_NIRQ 32 #define STAR_UART_SIZE 0x20 #define STAR_UART_FREQ 14745600L /* 14.7456MHz */ /* * STRxxxx - Timer Registers (0x79000000) */ #define STAR_TIMER1_COUNTER 0x79000000 /* if up/down to 0, would be reloaded */ #define STAR_TIMER1_LOAD 0x79000004 /* if up/down to 0, reload this value */ #define STAR_TIMER1_MATCH1 0x79000008 /* Match1 interrupt when counter is equal to */ #define STAR_TIMER1_MATCH2 0x7900000c /* Match2 interrupt when counter is equal to */ #define STAR_TIMER2_COUNTER 0x79000010 /* same as TIMER1 */ #define STAR_TIMER2_LOAD 0x79000014 #define STAR_TIMER2_MATCH1 0x79000018 #define STAR_TIMER2_MATCH2 0x7900001c #define STAR_TIMER_CTRL 0x79000030 # define STAR_TIMER_CTRL_TM1_DECREMENT 0x00000400 /* RW: 0:Up, 1:Down */ # define STAR_TIMER_CTRL_TM2_DECREMENT 0x00000200 /* RW: 0:Up, 1:Down */ # define STAR_TIMER_CTRL_TM2OVERFLOWENABLE 0x00000020 /* RW: 0:Disable, 1:Enable */ # define STAR_TIMER_CTRL_TM2CLOCK_1KHZ 0x00000010 /* RW: 0:PCLK, 1:1KHz */ # define STAR_TIMER_CTRL_TM2ENABLE 0x00000008 /* RW: 0:Disable, 1:Enable */ # define STAR_TIMER_CTRL_TM1OVERFLOWENABLE 0x00000004 /* RW: 0:Disable, 1:Enable */ # define STAR_TIMER_CTRL_TM1CLOCK_1KHZ 0x00000002 /* RW: 0:PCLK, 1:1KHz */ # define STAR_TIMER_CTRL_TM1ENABLE 0x00000001 /* RW: 0:Disable, 1:Enable */ #define STAR_TIMER_INT_STATUS 0x79000034 #define STAR_TIMER_INT_MASK 0x79000038 # define STAR_TIMER_INT_TM2OVERFLOW 0x00000020 # define STAR_TIMER_INT_TM2MATCH2 0x00000010 # define STAR_TIMER_INT_TM2MATCH1 0x00000008 # define STAR_TIMER_INT_TM1OVERFLOW 0x00000004 # define STAR_TIMER_INT_TM1MATCH2 0x00000002 # define STAR_TIMER_INT_TM1MATCH1 0x00000001 #define STAR_TIMER_FREERUN 0x79000040 /* Timer3 100KHz Free Running Counter [31:0] bit */ #define STAR_TIMER_FREERUN_CTRL 0x79000044 # define STAR_TIMER_FREERUN_TM3RUN 0000020000 /* RW: 0:stop, 1:run */ # define STAR_TIMER_FREERUN_TM3RESET 0x00010000 /* WCt */ # define STAR_TIMER_FREERUN_TM3HI 0x0000ffff /* RO 100KHz Free Running Counter [47:32] bit */ /* * STR81xx - Vector Interrupt Control Registers (0xFFFFF000) */ #define EQUULEUS_INT_STATUS 0xFFFFF000 /* RO: IRQ bitmapped 0:noactive, 1:active */ #define EQUULEUS_INT_CLEAR 0xFFFFF004 /* WC: IRQ bitmapped 0:noeffect, 1:clearactive */ #define EQUULEUS_INT_MASK 0xFFFFF008 /* RW: IRQ bitmapped 0:unmasked, 1:masked */ #define EQUULEUS_INT_MASKCLEAR 0xFFFFF00C /* WO: IRQ bitmapped 0:noeffect, 1:clearmask */ #define EQUULEUS_INT_TRIGMODE 0xFFFFF010 /* RW: 0:LevelTrigger, 1:EdgeTrigger */ #define EQUULEUS_INT_TRIGLEVEL 0xFFFFF014 /* RW: 0:HighLevelTrigger, 1:LowLevelTrigger */ #define EQUULEUS_INT_FIQSEL 0xFFFFF018 /* RW: 0:IRQ, 1:FIQ */ #define EQUULEUS_INT_IRQSTATUS 0xFFFFF01C /* RO: 0:Inactive, 1:Active */ #define EQUULEUS_INT_FIQSTATUS 0xFFFFF020 /* RO: 0:Inactive, 1:Active */ #define EQUULEUS_INT_SOFTINT 0xFFFFF024 /* RW: 0:Inactive, 1:Active(Enable) */ #define EQUULEUS_INT_SOFTCLEAR 0xFFFFF028 /* WO: 0:noeffect, 1:Disable */ #define EQUULEUS_INT_SOFTPRIOMASK 0xFFFFF02C /* RW: 0x00-0xFF */ #define EQUULEUS_INT_PWRINTSEL 0xFFFFF034 /* RW: 0:no wakeup intr, 1:selected wakeup intr */ #define EQUULEUS_INT_VECTORADDR(n) (0xFFFFF040 + (n) * 4) #define EQUULEUS_INT_PRIORITY(n) (0xFFFFF0C0 + (n) * 4) /* 0-7 */ #define EQUULEUS_INT_IRQVECTOR 0xFFFFF140 /* RW: address of current active ISR */ #define EQUULEUS_INT_VIC_EN 0xFFFFF144 /* RW: 0:Disable VIC, 1:Enable VIC */ /* * STR91xx - Interrupt Controller (0x7D000000) */ #define ORION_INT_STATUS 0x7D000000 /* RO: IRQ bitmapped */ #define ORION_INT_MASK 0x7D000004 /* RW: IRQ bitmapped */ #define ORION_INT_CLEAR 0x7D000008 /* WO: IRQ bitmapped */ #define ORION_INT_TRIGMODE 0x7D00000c /* RW: 0:LevelTrigger, 1:EdgeTrigger */ #define ORION_INT_TRIGLEVEL 0x7D000010 /* RW: 0:HighLevelTrigger, 1:LowLevelTrigger */ #define ORION_INT_IRQSTATUS 0x7D000014 /* RO: 0:Inactive, 1:Active */ #define ORION_INT_FIQSEL 0x7D000018 /* RW: 0:IRQ, 1:FIQ */ #define STAR_REG_READ32(addr) (*(volatile uint32_t *)(addr)) #define STAR_REG_WRITE32(addr, value) ((*(volatile uint32_t *)(addr)) = (value)) #endif /* _STARREG_H_ */