 @@ -1,14 +1,14 @@
-/*	$NetBSD: bcm53xx_board.c,v 1.25 2018/07/31 06:46:25 skrll Exp $	*/
+/*	$NetBSD: bcm53xx_board.c,v 1.25.30.1 2024/02/16 12:07:07 skrll Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -26,27 +26,27 @@
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "opt_arm_debug.h"
 #include "opt_broadcom.h"
 #include "arml2cc.h"
 #define	_ARM32_BUS_DMA_PRIVATE
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.25 2018/07/31 06:46:25 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.25.30.1 2024/02/16 12:07:07 skrll Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <prop/proplib.h>
 #include <net/if.h>
 #include <net/if_ether.h>
 #define CCA_PRIVATE
 #define CRU_PRIVATE
 @@ -318,66 +318,66 @@ bcm53xx_lcpll_clock_init(struct bcm53xx_
 	clk->clk_sdio = clk->clk_lcpll / ch1_mdiv;	// LCPLL CH1
 	clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv;	// LCPLL CH2
 	clk->clk_axi = clk->clk_lcpll / ch3_mdiv;	// LCPLL CH3
+}
 static void
 bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control)
+{
 	const uint32_t pdiv = bcm53xx_value_wrap(usb2_control,
 	    USB2_CONTROL_PDIV);
 	const uint32_t ndiv = bcm53xx_value_wrap(usb2_control,
 	    USB2_CONTROL_NDIV_INT);
 	uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv;
 	if (usb_ref != USB2_REF_CLK) {
 		/*
 		 * USB Reference Clock isn't 1.92GHz.  So we need to modify
 		 * USB2_CONTROL to produce it.
 		 */
 		uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv;
 		usb2_control &= ~USB2_CONTROL_NDIV_INT;
 		usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT);
 		// Allow Clocks to be modified
 		bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
 		    CRU_BASE + CRU_CLKSET_KEY, CRU_CLKSET_KEY_MAGIC);
 		// Update USB2 clock generator
 		bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
 		    CRU_BASE + CRU_USB2_CONTROL, usb2_control);
 		// Prevent Clock modification
 		bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
 		    CRU_BASE + CRU_CLKSET_KEY, 0);
 		usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv;
+	}
 	clk->clk_usb_ref = usb_ref;
+}
 static void
 bcm53xx_clock_init(struct bcm53xx_clock_info *clk)
+{
 	clk->clk_ref = BCM53XX_REF_CLK;
 	clk->clk_sys = 8*clk->clk_ref;
+}
 /*
  * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2)
  */
 static void
 bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status,
     uint32_t pll_dividers)
+{
 	const bool clocking_4x = (pll_status & PLL_STATUS_CLOCKING_4X) != 0;
 	u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV);
 	u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV);
 	u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV);
 	pdiv = ((pdiv - (clocking_4x ? 1 : 5)) & 7) + 1;
 	clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ);
 	clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div);
+}
 @@ -392,27 +392,27 @@ bcm53xx_get_cpu_freq(struct bcm53xx_cloc
 	policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2);
 	if (policy == CLK_POLICY_REF_CLK) {
 		clk->clk_cpu = clk->clk_ref;
 		clk->clk_apb = clk->clk_cpu;
 		return;
+	}
 	if (policy == CLK_POLICY_SYS_CLK) {
 		clk->clk_cpu = clk->clk_sys;
 		clk->clk_apb = clk->clk_cpu / 4;
 		return;
+	}
 	const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV);
 	const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT);
 	const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC);
 	// const u_int apb_clk_div = __SHIFTOUT(apb_clk_div, CLK_APB_DIV_VALUE)+1;
 	const u_int cpu_div = (policy == CLK_POLICY_ARM_PLL_CH0) ? 4 : 2;
 	clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div;
 	clk->clk_apb = clk->clk_cpu / 4;
+}
 struct bcm53xx_chip_state {
 	uint32_t bcs_lcpll_control1;
 @@ -595,33 +595,33 @@ bcm53xx_cpu_hatch(struct cpu_info *ci)
 #endif
 void
 bcm53xx_device_register(device_t self, void *aux)
+{
 	prop_dictionary_t dict = device_properties(self);
 	if (device_is_a(self, "armperiph")
 	    && device_is_a(device_parent(self), "mainbus")) {
 		/*
 		 * XXX KLUDGE ALERT XXX
 		 * The iot mainbus supplies is completely wrong since it scales
 		 * addresses by 2.  The simplest remedy is to replace with our
 		 * bus space used for the armcore registers (which armperiph uses).
 		 */
 		struct mainbus_attach_args * const mb = aux;
 		mb->mb_iot = bcm53xx_armcore_bst;
 		return;
+	}
 	/*
 	 * We need to tell the A9 Global/Watchdog Timer
 	 * what frequency it runs at.
 	 */
 	if (device_is_a(self, "arma9tmr") || device_is_a(self, "a9wdt")) {
 		/*
 		 * This clock always runs at (arm_clk div 2) and only goes
 		 * to timers that are part of the A9 MP core subsystem.
 		 */
                 prop_dictionary_set_uint32(dict, "frequency",
 		    cpu_softc.cpu_clk.clk_cpu / 2);
 		return;
+	}
 @@ -639,28 +639,28 @@ bcm53xx_device_register(device_t self, v
+		}
 		prop_object_release(pd);
+	}
+}
 #ifdef SRAB_BASE
 static kmutex_t srab_lock __cacheline_aligned;
 void
 bcm53xx_srab_init(void)
+{
 	mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM);
 	bcm53xx_srab_write_4(0x0079, 0x90);	// reset switch
 	for (u_int port = 0; port < 8; port++) {
 		/* per port control: no stp */
 		bcm53xx_srab_write_4(port, 0x00);
+	}
 	bcm53xx_srab_write_4(0x0008, 0x1c);	// IMP port (enab UC/MC/BC)
 	bcm53xx_srab_write_4(0x000e, 0xbb);	// IMP port force-link 1G
 	bcm53xx_srab_write_4(0x005d, 0x7b);	// port5 force-link 1G
 	bcm53xx_srab_write_4(0x005f, 0x7b);	// port7 force-link 1G
 	bcm53xx_srab_write_4(0x000b, 0x7);	// management mode
 	bcm53xx_srab_write_4(0x0203, 0x0);	// disable BRCM tag
 	bcm53xx_srab_write_4(0x0200, 0x80);	// enable IMP=port8
+}
 static inline void

 @@ -25,51 +25,51 @@
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "opt_broadcom.h"
 #include "locators.h"
 #define CRU_PRIVATE
 #define IDM_PRIVATE
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_idm.c,v 1.3 2012/12/12 00:01:28 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_idm.c,v 1.3.70.1 2024/02/16 12:07:08 skrll Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <arm/mainbus/mainbus.h>
 #include <arm/broadcom/bcm53xx_reg.h>
 #include <arm/broadcom/bcm53xx_var.h>
 struct idm_info {
 	bus_size_t idm_offset;
 	const char *idm_name;
 	int idm_port;
 	bool (*idm_unreset)(bus_space_tag_t, bus_space_handle_t,
 	    const struct idm_info *);
 };
 static bool
 bcmeth_unreset(bus_space_tag_t bst, bus_space_handle_t bsh,
     const struct idm_info *idm)
+{
 	/*
 	 * To enable any GMAC, we must enable all off them.
 	 */
 	static const bus_size_t regoff[] = {
 		IDM_BASE + IDM_AMAC0_BASE,
 		IDM_BASE + IDM_AMAC1_BASE,
 		IDM_BASE + IDM_AMAC2_BASE,
 		IDM_BASE + IDM_AMAC3_BASE,
 	};
 	static bool bcmeth_init_done;
 	if (!bcmeth_init_done) {
 		for (size_t idx = 0; idx < __arraycount(regoff); idx++) {
 			const bus_size_t off = regoff[idx];

 @@ -24,27 +24,27 @@
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #define _ARM32_BUS_DMA_PRIVATE
 #define PCIE_PRIVATE
 #include "locators.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_pax.c,v 1.22 2021/08/07 16:18:43 thorpej Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_pax.c,v 1.22.6.1 2024/02/16 12:07:08 skrll Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/kmem.h>
 #include <sys/systm.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pciconf.h>
 #include <arm/locore.h>
 @@ -261,58 +261,58 @@ bcmpax_ccb_attach(device_t parent, devic
 	sc->sc_pba_flags |= PCI_FLAGS_MRL_OKAY;
 	sc->sc_pba_flags |= PCI_FLAGS_MRM_OKAY;
 	sc->sc_pba_flags |= PCI_FLAGS_MWI_OKAY;
 	// sc->sc_pba_flags |= PCI_FLAGS_MSI_OKAY;
 	// sc->sc_pba_flags |= PCI_FLAGS_MSIX_OKAY;
 	for (size_t i = 0; i < loc->loc_nintrs; i++) {
 		sc->sc_ih[i] = intr_establish(loc->loc_intrs[0] + i, IPL_VM,
 		    IST_LEVEL, bcmpax_intr, sc);
 		if (sc->sc_ih[i] == NULL) {
 			aprint_error_dev(self,
 			    "failed to establish interrupt #%zu (%zu)\n", i,
 			    loc->loc_intrs[0] + i);
 			while (i-- > 0) {
 				intr_disestablish(sc->sc_ih[i]);
+			}
 			return;
+		}
+	}
 	aprint_normal_dev(self, "interrupting on irqs %d-%d\n",
 	     loc->loc_intrs[0], loc->loc_intrs[0] + loc->loc_nintrs - 1);
 	/*
 	 * Enable INTA-INTD
 	 */
 	bcmpax_write_4(sc, PCIE_SYS_RC_INTX_EN, 0x0f);
 	int offset;
 	const bool ok = pci_get_capability(&sc->sc_pc, 0, PCI_CAP_PCIEXPRESS,
 	    &offset, NULL);
 	KASSERT(ok);
 	/*
 	 * This will force the device to negotiate to a max of gen1.
 	 */
 	if (cf->cf_flags & 1) {
 		bcmpax_conf_write(sc, 0, offset + PCIE_LCSR2, 1);
+	}
 	/*
 	 * Now we wait (.25 sec) for the link to come up.
 	 */
 	offset += PCIE_LCSR;
 	for (size_t timo = 0;; timo++) {
 		const pcireg_t lcsr = bcmpax_conf_read(sc, 0, offset);
 		sc->sc_linkup = __SHIFTOUT(lcsr, PCIE_LCSR_NLW) != 0
 		    && (1 || (lcsr & PCIE_LCSR_DLACTIVE) != 0);
 		if (sc->sc_linkup || timo == 250) {
 			aprint_debug_dev(self,
 			    "lcsr=%#x nlw=%jd linkup=%d, timo=%zu\n",
 			    lcsr, __SHIFTOUT(lcsr, PCIE_LCSR_NLW),
 			    sc->sc_linkup, timo);
 			break;
+		}
 		DELAY(1000);
+	}
 	if (sc->sc_linkup) {
 @@ -350,27 +350,27 @@ bcmpax_ccb_attach(device_t parent, devic
 		    base, size);
 		error = pci_configure_bus(&sc->sc_pc, pcires,
 , arm_pcache.dcache_line_size);
 		pciconf_resource_fini(pcires);
 		if (error) {
 			aprint_normal_dev(self, "configuration failed\n");
 			return;
+		}
+	}
 	struct pcibus_attach_args pba;
 	memset(&pba, 0, sizeof(pba));
 	pba.pba_flags = sc->sc_pba_flags;
 	pba.pba_flags |= PCI_FLAGS_MEM_OKAY;
 	pba.pba_memt = sc->sc_bst;
 	pba.pba_dmat = sc->sc_dmat;
 	pba.pba_pc = &sc->sc_pc;
 	pba.pba_bus = 0;
 	config_found(self, &pba, pcibusprint, CFARGS_NONE);
+}
 static void
 bcmpax_attach_hook(device_t parent, device_t self,
     struct pcibus_attach_args *pba)
 @@ -387,54 +387,54 @@ bcmpax_bus_maxdevs(void *v, int bus)
 	return bus ? 0 : 1;
+}
 static void
 bcmpax_decompose_tag(void *v, pcitag_t tag, int *busp, int *devp, int *funcp)
+{
 	if (busp)
 		*busp = __SHIFTOUT(tag, CFG_ADDR_BUS);
 	if (devp)
 		*devp = __SHIFTOUT(tag, CFG_ADDR_DEV);
 	if (funcp)
 		*funcp = __SHIFTOUT(tag, CFG_ADDR_FUNC);
+}
 static pcitag_t
 bcmpax_make_tag(void *v, int bus, int dev, int func)
+{
 	return __SHIFTIN(bus, CFG_ADDR_BUS)
 	   | __SHIFTIN(dev, CFG_ADDR_DEV)
 	   | __SHIFTIN(func, CFG_ADDR_FUNC)
 	   | (bus == 0 ? CFG_ADDR_TYPE0 : CFG_ADDR_TYPE1);
+}
 static inline bus_size_t
 bcmpax_conf_addr_write(struct bcmpax_softc *sc, pcitag_t tag)
+{
 	if ((tag & (CFG_ADDR_BUS|CFG_ADDR_DEV)) == 0) {
 		uint32_t reg = __SHIFTOUT(tag, CFG_ADDR_REG);
 		uint32_t func = __SHIFTOUT(tag, CFG_ADDR_FUNC);
 		bcmpax_write_4(sc, PCIE_CFG_IND_ADDR,
 		    __SHIFTIN(func, CFG_IND_ADDR_FUNC)
 		    | __SHIFTIN(reg, CFG_IND_ADDR_REG));
 		dsb(sy);
 		return PCIE_CFG_IND_DATA;
+	}
 	if (sc->sc_linkup) {
 		bcmpax_write_4(sc, PCIE_CFG_ADDR, tag);
 		dsb(sy);
 		return PCIE_CFG_DATA;
+	}
 	return 0;
+}
 static pcireg_t
 bcmpax_conf_read(void *v, pcitag_t tag, int reg)
+{
 	struct bcmpax_softc * const sc = v;
 	if ((unsigned int)reg >= PCI_CONF_SIZE)
 		return 0xffffffff;
 	/*
 	 * Even in RC mode, the PCI Express Root Complex return itself

 @@ -1,14 +1,14 @@
-/* $NetBSD: bcm53xx_reg.h,v 1.19 2022/03/24 08:08:04 andvar Exp $ */
+/* $NetBSD: bcm53xx_reg.h,v 1.19.4.1 2024/02/16 12:07:08 skrll Exp $ */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -328,37 +328,37 @@
 #define CRUCTL_QSPI_CLK_SEL	__BITS(2,1)
 #define QSPI_CLK_25MHZ		0	// iproc_ref_clk
 #define QSPI_CLK_50MHZ		1	// iproc_sdio_clk / 4
 #define QSPI_CLK_31dot25MHZ	2	// iproc_clk250 / 8
 #define QSPI_CLK_62dot5MHZ	3	// iproc_clk250 / 4
 #define CRUCTL_SW_RESET		__BIT(0)
 #define CRU_GENPLL_CONTROL5		0x1154
 #define GENPLL_CONTROL5_NDIV_INT	__BITS(29,20)	// = (n ? n : 1024)
 #define GENPLL_CONTROL5_NDIV_FRAC	__BITS(19,0)	// = 1 / n
 #define CRU_GENPLL_CONTROL6		0x1158
 #define GENPLL_CONTROL6_PDIV		__BITS(26,24)	// = (n ? n : 8)
 #define GENPLL_CONTROL6_CH0_MDIV	__BITS(23,16)	// = (n ? n : 256), clk_mac
 #define GENPLL_CONTROL6_CH1_MDIV	__BITS(15,8)	// = (n ? n : 256), clk_robo
 #define GENPLL_CONTROL6_CH2_MDIV	__BITS(7,0)	// = (n ? n : 256), clf_usb2
 #define CRU_GENPLL_CONTROL7		0x115c
 #define GENPLL_CONTROL7_CH3_MDIV	__BITS(23,16)	// = (n ? n : 256), clk_iproc
 #define USB2_REF_CLK			(1920*1000*1000)
 #define CRU_USB2_CONTROL		0x1164
 #define USB2_CONTROL_KA			__BITS(24,22)
 #define USB2_CONTROL_KI			__BITS(31,19)
 #define USB2_CONTROL_KP			__BITS(18,15)
 #define USB2_CONTROL_PDIV		__BITS(14,12)	// = (n ? n : 8)
 #define USB2_CONTROL_NDIV_INT		__BITS(11,2)	// = (n ? n : 1024)
 #define USB2_CONTROL_PLL_PCIEUSB3_RESET	__BIT(1)	// inverted 1=normal
 #define USB2_CONTROL_PLL_USB2_RESET	__BIT(0)	// inverted 1=normal
 #define CRU_CLKSET_KEY			0x1180
 #define CRU_CLKSET_KEY_MAGIC		0xea68
 #define CRU_GPIO_SELECT		0x11c0 	// CRU GPIO Select
 #define CRU_GPIO_DRIVE_SEL2	0x11c4
 #define CRU_GPIO_DRIVE_SEL1	0x11c8
 #define CRU_GPIO_DRIVE_SEL0	0x11cc
 #define CRU_GPIO_INPUT_DISABLE	0x11d0
 #define CRU_GPIO_HYSTERESIS	0x11d4
 @@ -376,36 +376,36 @@
 #define  STRAP_PCIE0_MODE	__BIT(5)
 #define  STRAP_USB3_SEL		__BIT(4)
 #define  STRAP_EX_EXTCLK	__BIT(3)
 #define  STRAP_HW_FWDG_EN	__BIT(2)
 #define  STRAP_LED_SERIAL_MODE	__BIT(1)
 #define  STRAP_BISR_BYPASS_AUTOLOAD	 __BIT(0)
 #endif /* CRU_PRIVATE */
 #ifdef DMU_PRIVATE
 #define DMU_LCPLL_CONTROL0	0x100
 #define DMU_LCPLL_CONTROL1	0x104
 #define LCPLL_CONTROL1_PDIV	__BITS(30,28)	// = (n ? n : 8)
 #define LCPLL_CONTROL1_NDIV_INT	__BITS(27,20)	// = (n ? n : 256)
 #define LCPLL_CONTROL1_NDIV_FRAC __BITS(19,0)	// = 1 / n
 /*
  * SYS_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref)
  */
 #define DMU_LCPLL_CONTROL2	0x108
 #define LCPLL_CONTROL2_CH0_MDIV	__BITS(31,24)	// = (n ? n : 256), clk_pcie_ref
 #define LCPLL_CONTROL2_CH1_MDIV	__BITS(23,16)	// = (n ? n : 256), clk_sdio
 #define LCPLL_CONTROL2_CH2_MDIV	__BITS(15,8)	// = (n ? n : 256), clk_ddr
 #define LCPLL_CONTROL2_CH3_MDIV	__BITS(7,0)	// = (n ? n : 256), clf_dft
 #define DMU_CRU_RESET		0x200
 #define DMU_CRU_RESET_IPROC	__BIT(1)
 #define DMU_CRU_RESET_CMICD	__BIT(0)
 #endif /* DMU_PRIVATE */
 #ifdef DDR_PRIVATE
 /*
  * DDR CTL register has such inspired names.
  */
 #define DDR_CTL_01		0x004
 @@ -641,27 +641,27 @@
 #define CLK_POLICY_SYS_CLK	1	// sys clk (200MHZ)
 #define CLK_POLICY_ARM_PLL_CH0	6	// slow clock
 #define CLK_POLICY_ARM_PLL_CH1	7	// fast clock
 #define ARMCORE_CLK_APB_DIV	0xa10
 #define CLK_APB_DIV_PRIVED	__BIT(31)
 #define CLK_APB_DIV_VALUE	__BITS(1,0)	// n = n + 1
 #define ARMCORE_CLK_APB_DIV_TRIGGER	0xa10
 #define CLK_APB_DIV_TRIGGER_PRIVED	__BIT(31)
 #define CLK_APB_DIV_TRIGGER_OVERRIDE	__BIT(0)
 #define ARMCORE_CLK_PLLARMA	0xc00
 #define CLK_PLLARMA_PDIV	__BITS(26,24)	// = (n ? n : 16(?))
 #define CLK_PLLARMA_NDIV_INT	__BITS(17,8)	// = (n ? n : 1024)
 #define ARMCORE_CLK_PLLARMB	0xc04
 #define CLK_PLLARMB_NDIV_FRAC	__BITS(19,0)	// = 1 / n
 #endif
 #ifdef IDM_PRIVATE
 #define IDM_ARMCORE_M0_BASE		0x00000
 #define IDM_PCIE_M0_BASE		0x01000
 #define IDM_PCIE_M1_BASE		0x02000
 #define IDM_PCIE_M2_BASE		0x03000
 @@ -767,27 +767,27 @@ struct gmac_rxdb {
 #define  RXC_DRNG		__BITS(17,16)
 #define  TXQ_FLUSH		__BIT(8)
 #define  NWAY_AUTO_POLL_EN	__BIT(7)
 #define  FLOW_CTRL_MODE		__BITS(6,5)
 #define  MIB_RD_RESET_EN	__BIT(4)
 #define  RGMII_LINK_STATUS_SEL	__BIT(3)
 #define  CPU_FLOW_CTRL_ON	__BIT(2)
 #define  RXQ_OVERFLOW_CTRL_SEL	__BIT(1)
 #define  TXARB_STRICT_MODE	__BIT(0)
 #define GMAC_DEVSTATUS		0x004
 #define GMAC_BISTSTATUS		0x00c
 #define GMAC_INTSTATUS		0x020
 #define GMAC_INTMASK		0x024
 #define  TXQECCUNCORRECTED	__BIT(31)
 #define  TXQECCCORRECTED	__BIT(30)
 #define  RXQECCUNCORRECTED	__BIT(29)
 #define  RXQECCCORRECTED	__BIT(28)
 #define  XMTINT_3		__BIT(27)
 #define  XMTINT_2		__BIT(26)
 #define  XMTINT_1		__BIT(25)
 #define  XMTINT_0		__BIT(24)
 #define  RCVINT			__BIT(16)
 #define  XMTUF			__BIT(15)
 #define  RCVFIFOOF		__BIT(14)
 #define  RCVDESCUF		__BIT(13)
 #define  DESCPROTOERR		__BIT(12)
 #define  DATAERR		__BIT(11)
 @@ -894,38 +894,38 @@ struct gmac_rxdb {
 #define  CNTRL_FRM_ENA		__BIT(23)
 #define  ENA_EXT_CONFIG		__BIT(22)
 #define  EN_INTERNAL_TX_CRS	__BIT(21)
 #define  SW_OVERRIDE_RX		__BIT(18)
 #define  SW_OVERRIDE_TX		__BIT(17)
 #define  MAC_LOOP_CON		__BIT(16)
 #define  LOOP_ENA		__BIT(15)
 #define  RCS_CORRUPT_URUN_EN	__BIT(14)
 #define  SW_RESET		__BIT(13)
 #define  OVERFLOW_EN		__BIT(12)
 #define  RX_LOW_LATENCY_EN	__BIT(11)
 #define  HD_ENA			__BIT(10)
 #define  TX_ADDR_INS		__BIT(9)
 #define  PAUSE_IGNORE		__BIT(8)
 #define  PAUSE_FWD		__BIT(7)
 #define  CRC_FWD		__BIT(6)
 #define  PAD_EN			__BIT(5)
 #define  PROMISC_EN		__BIT(4)
 #define  ETH_SPEED		__BITS(3,2)
 #define  ETH_SPEED_10		0
 #define  ETH_SPEED_100		1
 #define  ETH_SPEED_1000		2
 #define  ETH_SPEED_2500		3
 #define  RX_ENA			__BIT(1)
 #define  TX_ENA			__BIT(0)
 #define UNIMAC_MAC_0		0x80c		// bits 16:47 of macaddr
 #define UNIMAC_MAC_1		0x810		// bits 0:15 of macaddr
 #define UNIMAC_FRAME_LEN	0x814
 #define UNIMAC_PAUSE_QUANTA	0x818
 #define UNIMAC_TX_TS_SEQ_ID	0x83c
 #define UNIMAC_MAC_MODE		0x844
 #define UNIMAC_TAG_0		0x848
 #define UNIMAC_TAG_1		0x84c
 #define UNIMAC_RX_PAUSE_QUANTA_SCALE	0x850
 #define UNIMAC_TX_PREAMBLE	0x854
 #define UNIMAC_TX_IPG_LENGTH	0x85c
 #define UNIMAC_PRF_XOFF_TIMER	0x860
 #define UNIMAC_UMAC_EEE_CTRL	0x864

 @@ -33,27 +33,27 @@
 #include "gpio.h"
 #include "bcmcca.h"
 #define	CCA_PRIVATE
 #define CRU_PRIVATE
 #define IDM_PRIVATE
 #if NCOM == 0
 #error no console configured
 #endif
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_cca.c,v 1.5 2022/03/03 06:26:28 riastradh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_cca.c,v 1.5.4.1 2024/02/16 12:07:07 skrll Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/time.h>
 #include <sys/termios.h>
 #include <dev/ic/comreg.h>
 #include <dev/ic/comvar.h>
 #include <arm/mainbus/mainbus.h>
 @@ -133,27 +133,27 @@ bcmcca_intr(void *arg)
 	int rv = 0;
 	uint32_t v = bcmcca_read_4(sc, MISC_INTSTATUS);
 	if (v & INTSTATUS_UARTINT) {
 		if (sc->sc_com_softc[0] != NULL)
 			rv = comintr(sc->sc_com_softc[0]);
 		if (sc->sc_com_softc[1] != NULL) {
 			int rv0 = comintr(sc->sc_com_softc[1]);
 			if (rv)
 				rv = rv0;
+		}
+	}
 	if (v & INTSTATUS_GPIOINT) {
+	}
 	return rv;
+}
 static void
 bcmcca_mainbus_attach(device_t parent, device_t self, void *aux)
+{
 	struct bcmcca_softc * const sc = &bcmcca_sc;
 	sc->sc_dev = self;
 	device_set_private(self, sc);
 	sc->sc_bst = bcm53xx_ioreg_bst;