Wed Apr 17 16:26:10 2024 UTC (33d)
Pull up following revision(s) (requested by riastradh in ticket #1953):

	sys/dev/pci/if_iwn.c: revision 1.100

if_iwn.c: pick up proper firmware for Centrino Wireless-N 130

Both variants should use iwlwifi-6000g2b-6 not iwlwifi-6000g2a-6. (It
seems only two specific product variants use iwlwifi-6000g2a-6. We
could simplify by reversing the sense of the test, as OpenBSD does, but
it doesn't seem to matter much, as what we now match seems to be the
full gamut possible, so the simpler diff was chosen here.)

Addresses PR kern/58105 from wandrien.dev%gmail.com@localhost, with the
PCI_PRODUCT_INTEL_WIFI_LINK_130_1 match tested by the reporter. Code
inspection of the FreeBSD driver indicates we should safely be able to
match PCI_PRODUCT_INTEL_WIFI_LINK_130_2 also.


(martin)
diff -r1.84.6.2 -r1.84.6.3 src/sys/dev/pci/if_iwn.c
cvs diff -r1.84.6.2 -r1.84.6.3 src/sys/dev/pci/if_iwn.c (switch to unified diff)

--- src/sys/dev/pci/if_iwn.c 2017/12/10 10:10:24 1.84.6.2
+++ src/sys/dev/pci/if_iwn.c 2024/04/17 16:26:10 1.84.6.3
@@ -1,1786 +1,1788 @@ @@ -1,1786 +1,1788 @@
1/* $NetBSD: if_iwn.c,v 1.84.6.2 2017/12/10 10:10:24 snj Exp $ */ 1/* $NetBSD: if_iwn.c,v 1.84.6.3 2024/04/17 16:26:10 martin Exp $ */
2/* $OpenBSD: if_iwn.c,v 1.135 2014/09/10 07:22:09 dcoppa Exp $ */ 2/* $OpenBSD: if_iwn.c,v 1.135 2014/09/10 07:22:09 dcoppa Exp $ */
3 3
4/*- 4/*-
5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
6 * 6 *
7 * Permission to use, copy, modify, and distribute this software for any 7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above 8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies. 9 * copyright notice and this permission notice appear in all copies.
10 * 10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */ 18 */
19 19
20/* 20/*
21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
22 * adapters. 22 * adapters.
23 */ 23 */
24#include <sys/cdefs.h> 24#include <sys/cdefs.h>
25__KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.84.6.2 2017/12/10 10:10:24 snj Exp $"); 25__KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.84.6.3 2024/04/17 16:26:10 martin Exp $");
26 26
27#define IWN_USE_RBUF /* Use local storage for RX */ 27#define IWN_USE_RBUF /* Use local storage for RX */
28#undef IWN_HWCRYPTO /* XXX does not even compile yet */ 28#undef IWN_HWCRYPTO /* XXX does not even compile yet */
29 29
30#include <sys/param.h> 30#include <sys/param.h>
31#include <sys/sockio.h> 31#include <sys/sockio.h>
32#include <sys/proc.h> 32#include <sys/proc.h>
33#include <sys/mbuf.h> 33#include <sys/mbuf.h>
34#include <sys/kernel.h> 34#include <sys/kernel.h>
35#include <sys/socket.h> 35#include <sys/socket.h>
36#include <sys/systm.h> 36#include <sys/systm.h>
37#include <sys/malloc.h> 37#include <sys/malloc.h>
38#ifdef notyetMODULE 38#ifdef notyetMODULE
39#include <sys/module.h> 39#include <sys/module.h>
40#endif 40#endif
41#include <sys/mutex.h> 41#include <sys/mutex.h>
42#include <sys/conf.h> 42#include <sys/conf.h>
43#include <sys/kauth.h> 43#include <sys/kauth.h>
44#include <sys/callout.h> 44#include <sys/callout.h>
45 45
46#include <dev/sysmon/sysmonvar.h> 46#include <dev/sysmon/sysmonvar.h>
47 47
48#include <sys/bus.h> 48#include <sys/bus.h>
49#include <machine/endian.h> 49#include <machine/endian.h>
50#include <sys/intr.h> 50#include <sys/intr.h>
51 51
52#include <dev/pci/pcireg.h> 52#include <dev/pci/pcireg.h>
53#include <dev/pci/pcivar.h> 53#include <dev/pci/pcivar.h>
54#include <dev/pci/pcidevs.h> 54#include <dev/pci/pcidevs.h>
55 55
56#include <net/bpf.h> 56#include <net/bpf.h>
57#include <net/if.h> 57#include <net/if.h>
58#include <net/if_arp.h> 58#include <net/if_arp.h>
59#include <net/if_dl.h> 59#include <net/if_dl.h>
60#include <net/if_media.h> 60#include <net/if_media.h>
61#include <net/if_types.h> 61#include <net/if_types.h>
62 62
63#include <netinet/in.h> 63#include <netinet/in.h>
64#include <netinet/in_systm.h> 64#include <netinet/in_systm.h>
65#include <netinet/in_var.h> 65#include <netinet/in_var.h>
66#include <net/if_ether.h> 66#include <net/if_ether.h>
67#include <netinet/ip.h> 67#include <netinet/ip.h>
68 68
69#include <net80211/ieee80211_var.h> 69#include <net80211/ieee80211_var.h>
70#include <net80211/ieee80211_amrr.h> 70#include <net80211/ieee80211_amrr.h>
71#include <net80211/ieee80211_radiotap.h> 71#include <net80211/ieee80211_radiotap.h>
72 72
73#include <dev/firmload.h> 73#include <dev/firmload.h>
74 74
75#include <dev/pci/if_iwnreg.h> 75#include <dev/pci/if_iwnreg.h>
76#include <dev/pci/if_iwnvar.h> 76#include <dev/pci/if_iwnvar.h>
77 77
78static const pci_product_id_t iwn_devices[] = { 78static const pci_product_id_t iwn_devices[] = {
79 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1, 79 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1,
80 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2, 80 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2,
81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1,
82 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 82 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2,
83 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3, 83 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3,
84 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4, 84 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4,
85 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1,
86 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2,
87 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1,
88 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2,
89 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1,
90 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 90 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2,
91 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 91 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1,
92 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 92 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2,
93 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 93 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1,
94 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 94 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2,
95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1,
96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2,
97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1,
98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2,
99 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1,
100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2,
101 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1,
102 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 102 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2,
103 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1,
104 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2, 104 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2,
105 PCI_PRODUCT_INTEL_WIFI_LINK_6235, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6235,
106 PCI_PRODUCT_INTEL_WIFI_LINK_6235_2, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6235_2,
107 PCI_PRODUCT_INTEL_WIFI_LINK_100_1, 107 PCI_PRODUCT_INTEL_WIFI_LINK_100_1,
108 PCI_PRODUCT_INTEL_WIFI_LINK_100_2, 108 PCI_PRODUCT_INTEL_WIFI_LINK_100_2,
109 PCI_PRODUCT_INTEL_WIFI_LINK_130_1, 109 PCI_PRODUCT_INTEL_WIFI_LINK_130_1,
110 PCI_PRODUCT_INTEL_WIFI_LINK_130_2, 110 PCI_PRODUCT_INTEL_WIFI_LINK_130_2,
111 PCI_PRODUCT_INTEL_WIFI_LINK_2230_1, 111 PCI_PRODUCT_INTEL_WIFI_LINK_2230_1,
112 PCI_PRODUCT_INTEL_WIFI_LINK_2230_2, 112 PCI_PRODUCT_INTEL_WIFI_LINK_2230_2,
113 PCI_PRODUCT_INTEL_WIFI_LINK_2200_1, 113 PCI_PRODUCT_INTEL_WIFI_LINK_2200_1,
114 PCI_PRODUCT_INTEL_WIFI_LINK_2200_2, 114 PCI_PRODUCT_INTEL_WIFI_LINK_2200_2,
115 PCI_PRODUCT_INTEL_WIFI_LINK_135_1, 115 PCI_PRODUCT_INTEL_WIFI_LINK_135_1,
116 PCI_PRODUCT_INTEL_WIFI_LINK_135_2, 116 PCI_PRODUCT_INTEL_WIFI_LINK_135_2,
117 PCI_PRODUCT_INTEL_WIFI_LINK_105_1, 117 PCI_PRODUCT_INTEL_WIFI_LINK_105_1,
118 PCI_PRODUCT_INTEL_WIFI_LINK_105_2, 118 PCI_PRODUCT_INTEL_WIFI_LINK_105_2,
119}; 119};
120 120
121/* 121/*
122 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 122 * Supported rates for 802.11a/b/g modes (in 500Kbps unit).
123 */ 123 */
124static const struct ieee80211_rateset iwn_rateset_11a = 124static const struct ieee80211_rateset iwn_rateset_11a =
125 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 125 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } };
126 126
127static const struct ieee80211_rateset iwn_rateset_11b = 127static const struct ieee80211_rateset iwn_rateset_11b =
128 { 4, { 2, 4, 11, 22 } }; 128 { 4, { 2, 4, 11, 22 } };
129 129
130static const struct ieee80211_rateset iwn_rateset_11g = 130static const struct ieee80211_rateset iwn_rateset_11g =
131 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 131 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
132 132
133static int iwn_match(device_t , struct cfdata *, void *); 133static int iwn_match(device_t , struct cfdata *, void *);
134static void iwn_attach(device_t , device_t , void *); 134static void iwn_attach(device_t , device_t , void *);
135static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 135static int iwn4965_attach(struct iwn_softc *, pci_product_id_t);
136static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 136static int iwn5000_attach(struct iwn_softc *, pci_product_id_t);
137static void iwn_radiotap_attach(struct iwn_softc *); 137static void iwn_radiotap_attach(struct iwn_softc *);
138static int iwn_detach(device_t , int); 138static int iwn_detach(device_t , int);
139#if 0 139#if 0
140static void iwn_power(int, void *); 140static void iwn_power(int, void *);
141#endif 141#endif
142static bool iwn_resume(device_t, const pmf_qual_t *); 142static bool iwn_resume(device_t, const pmf_qual_t *);
143static int iwn_nic_lock(struct iwn_softc *); 143static int iwn_nic_lock(struct iwn_softc *);
144static int iwn_eeprom_lock(struct iwn_softc *); 144static int iwn_eeprom_lock(struct iwn_softc *);
145static int iwn_init_otprom(struct iwn_softc *); 145static int iwn_init_otprom(struct iwn_softc *);
146static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 146static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
147static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 147static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *,
148 void **, bus_size_t, bus_size_t); 148 void **, bus_size_t, bus_size_t);
149static void iwn_dma_contig_free(struct iwn_dma_info *); 149static void iwn_dma_contig_free(struct iwn_dma_info *);
150static int iwn_alloc_sched(struct iwn_softc *); 150static int iwn_alloc_sched(struct iwn_softc *);
151static void iwn_free_sched(struct iwn_softc *); 151static void iwn_free_sched(struct iwn_softc *);
152static int iwn_alloc_kw(struct iwn_softc *); 152static int iwn_alloc_kw(struct iwn_softc *);
153static void iwn_free_kw(struct iwn_softc *); 153static void iwn_free_kw(struct iwn_softc *);
154static int iwn_alloc_ict(struct iwn_softc *); 154static int iwn_alloc_ict(struct iwn_softc *);
155static void iwn_free_ict(struct iwn_softc *); 155static void iwn_free_ict(struct iwn_softc *);
156static int iwn_alloc_fwmem(struct iwn_softc *); 156static int iwn_alloc_fwmem(struct iwn_softc *);
157static void iwn_free_fwmem(struct iwn_softc *); 157static void iwn_free_fwmem(struct iwn_softc *);
158static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 158static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
159static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 159static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
160static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 160static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
161static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 161static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
162 int); 162 int);
163static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 163static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
164static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 164static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
165static void iwn5000_ict_reset(struct iwn_softc *); 165static void iwn5000_ict_reset(struct iwn_softc *);
166static int iwn_read_eeprom(struct iwn_softc *); 166static int iwn_read_eeprom(struct iwn_softc *);
167static void iwn4965_read_eeprom(struct iwn_softc *); 167static void iwn4965_read_eeprom(struct iwn_softc *);
168 168
169#ifdef IWN_DEBUG 169#ifdef IWN_DEBUG
170static void iwn4965_print_power_group(struct iwn_softc *, int); 170static void iwn4965_print_power_group(struct iwn_softc *, int);
171#endif 171#endif
172static void iwn5000_read_eeprom(struct iwn_softc *); 172static void iwn5000_read_eeprom(struct iwn_softc *);
173static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 173static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t);
174static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 174static void iwn_read_eeprom_enhinfo(struct iwn_softc *);
175static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 175static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *);
176static void iwn_newassoc(struct ieee80211_node *, int); 176static void iwn_newassoc(struct ieee80211_node *, int);
177static int iwn_media_change(struct ifnet *); 177static int iwn_media_change(struct ifnet *);
178static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 178static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int);
179static void iwn_iter_func(void *, struct ieee80211_node *); 179static void iwn_iter_func(void *, struct ieee80211_node *);
180static void iwn_calib_timeout(void *); 180static void iwn_calib_timeout(void *);
181static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 181static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *,
182 struct iwn_rx_data *); 182 struct iwn_rx_data *);
183static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 183static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
184 struct iwn_rx_data *); 184 struct iwn_rx_data *);
185#ifndef IEEE80211_NO_HT 185#ifndef IEEE80211_NO_HT
186static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 186static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *,
187 struct iwn_rx_data *); 187 struct iwn_rx_data *);
188#endif 188#endif
189static void iwn5000_rx_calib_results(struct iwn_softc *, 189static void iwn5000_rx_calib_results(struct iwn_softc *,
190 struct iwn_rx_desc *, struct iwn_rx_data *); 190 struct iwn_rx_desc *, struct iwn_rx_data *);
191static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 191static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *,
192 struct iwn_rx_data *); 192 struct iwn_rx_data *);
193static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 193static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
194 struct iwn_rx_data *); 194 struct iwn_rx_data *);
195static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 195static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
196 struct iwn_rx_data *); 196 struct iwn_rx_data *);
197static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 197static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int,
198 uint8_t); 198 uint8_t);
199static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 199static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
200static void iwn_notif_intr(struct iwn_softc *); 200static void iwn_notif_intr(struct iwn_softc *);
201static void iwn_wakeup_intr(struct iwn_softc *); 201static void iwn_wakeup_intr(struct iwn_softc *);
202static void iwn_fatal_intr(struct iwn_softc *); 202static void iwn_fatal_intr(struct iwn_softc *);
203static int iwn_intr(void *); 203static int iwn_intr(void *);
204static void iwn_softintr(void *); 204static void iwn_softintr(void *);
205static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 205static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
206 uint16_t); 206 uint16_t);
207static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 207static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
208 uint16_t); 208 uint16_t);
209#ifdef notyet 209#ifdef notyet
210static void iwn5000_reset_sched(struct iwn_softc *, int, int); 210static void iwn5000_reset_sched(struct iwn_softc *, int, int);
211#endif 211#endif
212static int iwn_tx(struct iwn_softc *, struct mbuf *, 212static int iwn_tx(struct iwn_softc *, struct mbuf *,
213 struct ieee80211_node *, int); 213 struct ieee80211_node *, int);
214static void iwn_start(struct ifnet *); 214static void iwn_start(struct ifnet *);
215static void iwn_watchdog(struct ifnet *); 215static void iwn_watchdog(struct ifnet *);
216static int iwn_ioctl(struct ifnet *, u_long, void *); 216static int iwn_ioctl(struct ifnet *, u_long, void *);
217static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 217static int iwn_cmd(struct iwn_softc *, int, const void *, int, int);
218static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 218static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
219 int); 219 int);
220static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 220static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
221 int); 221 int);
222static int iwn_set_link_quality(struct iwn_softc *, 222static int iwn_set_link_quality(struct iwn_softc *,
223 struct ieee80211_node *); 223 struct ieee80211_node *);
224static int iwn_add_broadcast_node(struct iwn_softc *, int); 224static int iwn_add_broadcast_node(struct iwn_softc *, int);
225static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 225static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
226static int iwn_set_critical_temp(struct iwn_softc *); 226static int iwn_set_critical_temp(struct iwn_softc *);
227static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 227static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
228static void iwn4965_power_calibration(struct iwn_softc *, int); 228static void iwn4965_power_calibration(struct iwn_softc *, int);
229static int iwn4965_set_txpower(struct iwn_softc *, int); 229static int iwn4965_set_txpower(struct iwn_softc *, int);
230static int iwn5000_set_txpower(struct iwn_softc *, int); 230static int iwn5000_set_txpower(struct iwn_softc *, int);
231static int iwn4965_get_rssi(const struct iwn_rx_stat *); 231static int iwn4965_get_rssi(const struct iwn_rx_stat *);
232static int iwn5000_get_rssi(const struct iwn_rx_stat *); 232static int iwn5000_get_rssi(const struct iwn_rx_stat *);
233static int iwn_get_noise(const struct iwn_rx_general_stats *); 233static int iwn_get_noise(const struct iwn_rx_general_stats *);
234static int iwn4965_get_temperature(struct iwn_softc *); 234static int iwn4965_get_temperature(struct iwn_softc *);
235static int iwn5000_get_temperature(struct iwn_softc *); 235static int iwn5000_get_temperature(struct iwn_softc *);
236static int iwn_init_sensitivity(struct iwn_softc *); 236static int iwn_init_sensitivity(struct iwn_softc *);
237static void iwn_collect_noise(struct iwn_softc *, 237static void iwn_collect_noise(struct iwn_softc *,
238 const struct iwn_rx_general_stats *); 238 const struct iwn_rx_general_stats *);
239static int iwn4965_init_gains(struct iwn_softc *); 239static int iwn4965_init_gains(struct iwn_softc *);
240static int iwn5000_init_gains(struct iwn_softc *); 240static int iwn5000_init_gains(struct iwn_softc *);
241static int iwn4965_set_gains(struct iwn_softc *); 241static int iwn4965_set_gains(struct iwn_softc *);
242static int iwn5000_set_gains(struct iwn_softc *); 242static int iwn5000_set_gains(struct iwn_softc *);
243static void iwn_tune_sensitivity(struct iwn_softc *, 243static void iwn_tune_sensitivity(struct iwn_softc *,
244 const struct iwn_rx_stats *); 244 const struct iwn_rx_stats *);
245static int iwn_send_sensitivity(struct iwn_softc *); 245static int iwn_send_sensitivity(struct iwn_softc *);
246static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 246static int iwn_set_pslevel(struct iwn_softc *, int, int, int);
247static int iwn5000_runtime_calib(struct iwn_softc *); 247static int iwn5000_runtime_calib(struct iwn_softc *);
248 248
249static int iwn_config_bt_coex_bluetooth(struct iwn_softc *); 249static int iwn_config_bt_coex_bluetooth(struct iwn_softc *);
250static int iwn_config_bt_coex_prio_table(struct iwn_softc *); 250static int iwn_config_bt_coex_prio_table(struct iwn_softc *);
251static int iwn_config_bt_coex_adv1(struct iwn_softc *); 251static int iwn_config_bt_coex_adv1(struct iwn_softc *);
252static int iwn_config_bt_coex_adv2(struct iwn_softc *); 252static int iwn_config_bt_coex_adv2(struct iwn_softc *);
253 253
254static int iwn_config(struct iwn_softc *); 254static int iwn_config(struct iwn_softc *);
255static uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, 255static uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t,
256 uint8_t); 256 uint8_t);
257static uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 257static uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t);
258static uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 258static uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t);
259static int iwn_scan(struct iwn_softc *, uint16_t); 259static int iwn_scan(struct iwn_softc *, uint16_t);
260static int iwn_auth(struct iwn_softc *); 260static int iwn_auth(struct iwn_softc *);
261static int iwn_run(struct iwn_softc *); 261static int iwn_run(struct iwn_softc *);
262#ifdef IWN_HWCRYPTO 262#ifdef IWN_HWCRYPTO
263static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 263static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *,
264 struct ieee80211_key *); 264 struct ieee80211_key *);
265static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 265static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *,
266 struct ieee80211_key *); 266 struct ieee80211_key *);
267#endif 267#endif
268static int iwn_wme_update(struct ieee80211com *); 268static int iwn_wme_update(struct ieee80211com *);
269#ifndef IEEE80211_NO_HT 269#ifndef IEEE80211_NO_HT
270static int iwn_ampdu_rx_start(struct ieee80211com *, 270static int iwn_ampdu_rx_start(struct ieee80211com *,
271 struct ieee80211_node *, uint8_t); 271 struct ieee80211_node *, uint8_t);
272static void iwn_ampdu_rx_stop(struct ieee80211com *, 272static void iwn_ampdu_rx_stop(struct ieee80211com *,
273 struct ieee80211_node *, uint8_t); 273 struct ieee80211_node *, uint8_t);
274static int iwn_ampdu_tx_start(struct ieee80211com *, 274static int iwn_ampdu_tx_start(struct ieee80211com *,
275 struct ieee80211_node *, uint8_t); 275 struct ieee80211_node *, uint8_t);
276static void iwn_ampdu_tx_stop(struct ieee80211com *, 276static void iwn_ampdu_tx_stop(struct ieee80211com *,
277 struct ieee80211_node *, uint8_t); 277 struct ieee80211_node *, uint8_t);
278static void iwn4965_ampdu_tx_start(struct iwn_softc *, 278static void iwn4965_ampdu_tx_start(struct iwn_softc *,
279 struct ieee80211_node *, uint8_t, uint16_t); 279 struct ieee80211_node *, uint8_t, uint16_t);
280static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 280static void iwn4965_ampdu_tx_stop(struct iwn_softc *,
281 uint8_t, uint16_t); 281 uint8_t, uint16_t);
282static void iwn5000_ampdu_tx_start(struct iwn_softc *, 282static void iwn5000_ampdu_tx_start(struct iwn_softc *,
283 struct ieee80211_node *, uint8_t, uint16_t); 283 struct ieee80211_node *, uint8_t, uint16_t);
284static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 284static void iwn5000_ampdu_tx_stop(struct iwn_softc *,
285 uint8_t, uint16_t); 285 uint8_t, uint16_t);
286#endif 286#endif
287static int iwn5000_query_calibration(struct iwn_softc *); 287static int iwn5000_query_calibration(struct iwn_softc *);
288static int iwn5000_send_calibration(struct iwn_softc *); 288static int iwn5000_send_calibration(struct iwn_softc *);
289static int iwn5000_send_wimax_coex(struct iwn_softc *); 289static int iwn5000_send_wimax_coex(struct iwn_softc *);
290static int iwn6000_temp_offset_calib(struct iwn_softc *); 290static int iwn6000_temp_offset_calib(struct iwn_softc *);
291static int iwn2000_temp_offset_calib(struct iwn_softc *); 291static int iwn2000_temp_offset_calib(struct iwn_softc *);
292static int iwn4965_post_alive(struct iwn_softc *); 292static int iwn4965_post_alive(struct iwn_softc *);
293static int iwn5000_post_alive(struct iwn_softc *); 293static int iwn5000_post_alive(struct iwn_softc *);
294static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 294static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
295 int); 295 int);
296static int iwn4965_load_firmware(struct iwn_softc *); 296static int iwn4965_load_firmware(struct iwn_softc *);
297static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 297static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
298 const uint8_t *, int); 298 const uint8_t *, int);
299static int iwn5000_load_firmware(struct iwn_softc *); 299static int iwn5000_load_firmware(struct iwn_softc *);
300static int iwn_read_firmware_leg(struct iwn_softc *, 300static int iwn_read_firmware_leg(struct iwn_softc *,
301 struct iwn_fw_info *); 301 struct iwn_fw_info *);
302static int iwn_read_firmware_tlv(struct iwn_softc *, 302static int iwn_read_firmware_tlv(struct iwn_softc *,
303 struct iwn_fw_info *, uint16_t); 303 struct iwn_fw_info *, uint16_t);
304static int iwn_read_firmware(struct iwn_softc *); 304static int iwn_read_firmware(struct iwn_softc *);
305static int iwn_clock_wait(struct iwn_softc *); 305static int iwn_clock_wait(struct iwn_softc *);
306static int iwn_apm_init(struct iwn_softc *); 306static int iwn_apm_init(struct iwn_softc *);
307static void iwn_apm_stop_master(struct iwn_softc *); 307static void iwn_apm_stop_master(struct iwn_softc *);
308static void iwn_apm_stop(struct iwn_softc *); 308static void iwn_apm_stop(struct iwn_softc *);
309static int iwn4965_nic_config(struct iwn_softc *); 309static int iwn4965_nic_config(struct iwn_softc *);
310static int iwn5000_nic_config(struct iwn_softc *); 310static int iwn5000_nic_config(struct iwn_softc *);
311static int iwn_hw_prepare(struct iwn_softc *); 311static int iwn_hw_prepare(struct iwn_softc *);
312static int iwn_hw_init(struct iwn_softc *); 312static int iwn_hw_init(struct iwn_softc *);
313static void iwn_hw_stop(struct iwn_softc *); 313static void iwn_hw_stop(struct iwn_softc *);
314static int iwn_init(struct ifnet *); 314static int iwn_init(struct ifnet *);
315static void iwn_stop(struct ifnet *, int); 315static void iwn_stop(struct ifnet *, int);
316 316
317/* XXX MCLGETI alternative */ 317/* XXX MCLGETI alternative */
318static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 318static struct mbuf *MCLGETIalt(struct iwn_softc *, int,
319 struct ifnet *, u_int); 319 struct ifnet *, u_int);
320#ifdef IWN_USE_RBUF 320#ifdef IWN_USE_RBUF
321static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 321static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *);
322static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 322static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *);
323static int iwn_alloc_rpool(struct iwn_softc *); 323static int iwn_alloc_rpool(struct iwn_softc *);
324static void iwn_free_rpool(struct iwn_softc *); 324static void iwn_free_rpool(struct iwn_softc *);
325#endif 325#endif
326 326
327static void iwn_fix_channel(struct ieee80211com *, struct mbuf *, 327static void iwn_fix_channel(struct ieee80211com *, struct mbuf *,
328 struct iwn_rx_stat *); 328 struct iwn_rx_stat *);
329 329
330#ifdef IWN_DEBUG 330#ifdef IWN_DEBUG
331#define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 331#define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0)
332#define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 332#define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0)
333int iwn_debug = 0; 333int iwn_debug = 0;
334#else 334#else
335#define DPRINTF(x) 335#define DPRINTF(x)
336#define DPRINTFN(n, x) 336#define DPRINTFN(n, x)
337#endif 337#endif
338 338
339CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 339CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach,
340 iwn_detach, NULL); 340 iwn_detach, NULL);
341 341
342static int 342static int
343iwn_match(device_t parent, cfdata_t match __unused, void *aux) 343iwn_match(device_t parent, cfdata_t match __unused, void *aux)
344{ 344{
345 struct pci_attach_args *pa = aux; 345 struct pci_attach_args *pa = aux;
346 size_t i; 346 size_t i;
347 347
348 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 348 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
349 return 0; 349 return 0;
350 350
351 for (i = 0; i < __arraycount(iwn_devices); i++) 351 for (i = 0; i < __arraycount(iwn_devices); i++)
352 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 352 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i])
353 return 1; 353 return 1;
354 354
355 return 0; 355 return 0;
356} 356}
357 357
358static void 358static void
359iwn_attach(device_t parent __unused, device_t self, void *aux) 359iwn_attach(device_t parent __unused, device_t self, void *aux)
360{ 360{
361 struct iwn_softc *sc = device_private(self); 361 struct iwn_softc *sc = device_private(self);
362 struct ieee80211com *ic = &sc->sc_ic; 362 struct ieee80211com *ic = &sc->sc_ic;
363 struct ifnet *ifp = &sc->sc_ec.ec_if; 363 struct ifnet *ifp = &sc->sc_ec.ec_if;
364 struct pci_attach_args *pa = aux; 364 struct pci_attach_args *pa = aux;
365 const char *intrstr; 365 const char *intrstr;
366 pcireg_t memtype, reg; 366 pcireg_t memtype, reg;
367 int i, error; 367 int i, error;
368 char intrbuf[PCI_INTRSTR_LEN]; 368 char intrbuf[PCI_INTRSTR_LEN];
369 369
370 sc->sc_dev = self; 370 sc->sc_dev = self;
371 sc->sc_pct = pa->pa_pc; 371 sc->sc_pct = pa->pa_pc;
372 sc->sc_pcitag = pa->pa_tag; 372 sc->sc_pcitag = pa->pa_tag;
373 sc->sc_dmat = pa->pa_dmat; 373 sc->sc_dmat = pa->pa_dmat;
374 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 374 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE);
375 375
376 callout_init(&sc->calib_to, 0); 376 callout_init(&sc->calib_to, 0);
377 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 377 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc);
378 378
379 pci_aprint_devinfo(pa, NULL); 379 pci_aprint_devinfo(pa, NULL);
380 380
381 /* 381 /*
382 * Get the offset of the PCI Express Capability Structure in PCI 382 * Get the offset of the PCI Express Capability Structure in PCI
383 * Configuration Space. 383 * Configuration Space.
384 */ 384 */
385 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 385 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag,
386 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 386 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL);
387 if (error == 0) { 387 if (error == 0) {
388 aprint_error_dev(self, 388 aprint_error_dev(self,
389 "PCIe capability structure not found!\n"); 389 "PCIe capability structure not found!\n");
390 return; 390 return;
391 } 391 }
392 392
393 /* Clear device-specific "PCI retry timeout" register (41h). */ 393 /* Clear device-specific "PCI retry timeout" register (41h). */
394 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 394 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
395 if (reg & 0xff00) 395 if (reg & 0xff00)
396 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 396 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
397 397
398 /* Enable bus-mastering. */ 398 /* Enable bus-mastering. */
399 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 399 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */
400 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 400 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
401 reg |= PCI_COMMAND_MASTER_ENABLE; 401 reg |= PCI_COMMAND_MASTER_ENABLE;
402 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 402 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
403 403
404 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 404 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0);
405 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 405 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st,
406 &sc->sc_sh, NULL, &sc->sc_sz); 406 &sc->sc_sh, NULL, &sc->sc_sz);
407 if (error != 0) { 407 if (error != 0) {
408 aprint_error_dev(self, "can't map mem space\n"); 408 aprint_error_dev(self, "can't map mem space\n");
409 return; 409 return;
410 } 410 }
411 411
412 sc->sc_soft_ih = softint_establish(SOFTINT_NET, iwn_softintr, sc); 412 sc->sc_soft_ih = softint_establish(SOFTINT_NET, iwn_softintr, sc);
413 if (sc->sc_soft_ih == NULL) { 413 if (sc->sc_soft_ih == NULL) {
414 aprint_error_dev(self, "can't establish soft interrupt\n"); 414 aprint_error_dev(self, "can't establish soft interrupt\n");
415 goto unmap; 415 goto unmap;
416 } 416 }
417 417
418 /* Install interrupt handler. */ 418 /* Install interrupt handler. */
419 error = pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0); 419 error = pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0);
420 if (error) { 420 if (error) {
421 aprint_error_dev(self, "can't allocate interrupt\n"); 421 aprint_error_dev(self, "can't allocate interrupt\n");
422 goto failsi; 422 goto failsi;
423 } 423 }
424 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 424 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
425 if (pci_intr_type(sc->sc_pct, sc->sc_pihp[0]) == PCI_INTR_TYPE_INTX) 425 if (pci_intr_type(sc->sc_pct, sc->sc_pihp[0]) == PCI_INTR_TYPE_INTX)
426 CLR(reg, PCI_COMMAND_INTERRUPT_DISABLE); 426 CLR(reg, PCI_COMMAND_INTERRUPT_DISABLE);
427 else 427 else
428 SET(reg, PCI_COMMAND_INTERRUPT_DISABLE); 428 SET(reg, PCI_COMMAND_INTERRUPT_DISABLE);
429 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 429 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
430 intrstr = pci_intr_string(sc->sc_pct, sc->sc_pihp[0], intrbuf, 430 intrstr = pci_intr_string(sc->sc_pct, sc->sc_pihp[0], intrbuf,
431 sizeof(intrbuf)); 431 sizeof(intrbuf));
432 sc->sc_ih = pci_intr_establish_xname(sc->sc_pct, sc->sc_pihp[0], 432 sc->sc_ih = pci_intr_establish_xname(sc->sc_pct, sc->sc_pihp[0],
433 IPL_NET, iwn_intr, sc, device_xname(self)); 433 IPL_NET, iwn_intr, sc, device_xname(self));
434 if (sc->sc_ih == NULL) { 434 if (sc->sc_ih == NULL) {
435 aprint_error_dev(self, "can't establish interrupt"); 435 aprint_error_dev(self, "can't establish interrupt");
436 if (intrstr != NULL) 436 if (intrstr != NULL)
437 aprint_error(" at %s", intrstr); 437 aprint_error(" at %s", intrstr);
438 aprint_error("\n"); 438 aprint_error("\n");
439 goto failia; 439 goto failia;
440 } 440 }
441 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 441 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
442 442
443 /* Read hardware revision and attach. */ 443 /* Read hardware revision and attach. */
444 sc->hw_type = 444 sc->hw_type =
445 (IWN_READ(sc, IWN_HW_REV) & IWN_HW_REV_TYPE_MASK) 445 (IWN_READ(sc, IWN_HW_REV) & IWN_HW_REV_TYPE_MASK)
446 >> IWN_HW_REV_TYPE_SHIFT; 446 >> IWN_HW_REV_TYPE_SHIFT;
447 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 447 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
448 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 448 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id));
449 else 449 else
450 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 450 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id));
451 if (error != 0) { 451 if (error != 0) {
452 aprint_error_dev(self, "could not attach device\n"); 452 aprint_error_dev(self, "could not attach device\n");
453 goto failih; 453 goto failih;
454 }  454 }
455 455
456 if ((error = iwn_hw_prepare(sc)) != 0) { 456 if ((error = iwn_hw_prepare(sc)) != 0) {
457 aprint_error_dev(self, "hardware not ready\n"); 457 aprint_error_dev(self, "hardware not ready\n");
458 goto failih; 458 goto failih;
459 } 459 }
460 460
461 /* Read MAC address, channels, etc from EEPROM. */ 461 /* Read MAC address, channels, etc from EEPROM. */
462 if ((error = iwn_read_eeprom(sc)) != 0) { 462 if ((error = iwn_read_eeprom(sc)) != 0) {
463 aprint_error_dev(self, "could not read EEPROM\n"); 463 aprint_error_dev(self, "could not read EEPROM\n");
464 goto failih; 464 goto failih;
465 } 465 }
466 466
467 /* Allocate DMA memory for firmware transfers. */ 467 /* Allocate DMA memory for firmware transfers. */
468 if ((error = iwn_alloc_fwmem(sc)) != 0) { 468 if ((error = iwn_alloc_fwmem(sc)) != 0) {
469 aprint_error_dev(self, 469 aprint_error_dev(self,
470 "could not allocate memory for firmware\n"); 470 "could not allocate memory for firmware\n");
471 goto failih; 471 goto failih;
472 } 472 }
473 473
474 /* Allocate "Keep Warm" page. */ 474 /* Allocate "Keep Warm" page. */
475 if ((error = iwn_alloc_kw(sc)) != 0) { 475 if ((error = iwn_alloc_kw(sc)) != 0) {
476 aprint_error_dev(self, "could not allocate keep warm page\n"); 476 aprint_error_dev(self, "could not allocate keep warm page\n");
477 goto fail1; 477 goto fail1;
478 } 478 }
479 479
480 /* Allocate ICT table for 5000 Series. */ 480 /* Allocate ICT table for 5000 Series. */
481 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 481 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
482 (error = iwn_alloc_ict(sc)) != 0) { 482 (error = iwn_alloc_ict(sc)) != 0) {
483 aprint_error_dev(self, "could not allocate ICT table\n"); 483 aprint_error_dev(self, "could not allocate ICT table\n");
484 goto fail2; 484 goto fail2;
485 } 485 }
486 486
487 /* Allocate TX scheduler "rings". */ 487 /* Allocate TX scheduler "rings". */
488 if ((error = iwn_alloc_sched(sc)) != 0) { 488 if ((error = iwn_alloc_sched(sc)) != 0) {
489 aprint_error_dev(self, 489 aprint_error_dev(self,
490 "could not allocate TX scheduler rings\n"); 490 "could not allocate TX scheduler rings\n");
491 goto fail3; 491 goto fail3;
492 } 492 }
493 493
494#ifdef IWN_USE_RBUF 494#ifdef IWN_USE_RBUF
495 /* Allocate RX buffers. */ 495 /* Allocate RX buffers. */
496 if ((error = iwn_alloc_rpool(sc)) != 0) { 496 if ((error = iwn_alloc_rpool(sc)) != 0) {
497 aprint_error_dev(self, "could not allocate RX buffers\n"); 497 aprint_error_dev(self, "could not allocate RX buffers\n");
498 goto fail3; 498 goto fail3;
499 } 499 }
500#endif 500#endif
501 501
502 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 502 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */
503 for (i = 0; i < sc->ntxqs; i++) { 503 for (i = 0; i < sc->ntxqs; i++) {
504 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 504 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) {
505 aprint_error_dev(self, 505 aprint_error_dev(self,
506 "could not allocate TX ring %d\n", i); 506 "could not allocate TX ring %d\n", i);
507 goto fail4; 507 goto fail4;
508 } 508 }
509 } 509 }
510 510
511 /* Allocate RX ring. */ 511 /* Allocate RX ring. */
512 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 512 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) {
513 aprint_error_dev(self, "could not allocate RX ring\n"); 513 aprint_error_dev(self, "could not allocate RX ring\n");
514 goto fail4; 514 goto fail4;
515 } 515 }
516 516
517 /* Clear pending interrupts. */ 517 /* Clear pending interrupts. */
518 IWN_WRITE(sc, IWN_INT, 0xffffffff); 518 IWN_WRITE(sc, IWN_INT, 0xffffffff);
519 519
520 /* Count the number of available chains. */ 520 /* Count the number of available chains. */
521 sc->ntxchains = 521 sc->ntxchains =
522 ((sc->txchainmask >> 2) & 1) + 522 ((sc->txchainmask >> 2) & 1) +
523 ((sc->txchainmask >> 1) & 1) + 523 ((sc->txchainmask >> 1) & 1) +
524 ((sc->txchainmask >> 0) & 1); 524 ((sc->txchainmask >> 0) & 1);
525 sc->nrxchains = 525 sc->nrxchains =
526 ((sc->rxchainmask >> 2) & 1) + 526 ((sc->rxchainmask >> 2) & 1) +
527 ((sc->rxchainmask >> 1) & 1) + 527 ((sc->rxchainmask >> 1) & 1) +
528 ((sc->rxchainmask >> 0) & 1); 528 ((sc->rxchainmask >> 0) & 1);
529 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 529 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n",
530 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 530 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
531 ether_sprintf(ic->ic_myaddr)); 531 ether_sprintf(ic->ic_myaddr));
532 532
533 ic->ic_ifp = ifp; 533 ic->ic_ifp = ifp;
534 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 534 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
535 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 535 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
536 ic->ic_state = IEEE80211_S_INIT; 536 ic->ic_state = IEEE80211_S_INIT;
537 537
538 /* Set device capabilities. */ 538 /* Set device capabilities. */
539 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 539 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN,
540 * and IEEE80211_C_PMGT too. */ 540 * and IEEE80211_C_PMGT too. */
541 ic->ic_caps = 541 ic->ic_caps =
542 IEEE80211_C_IBSS | /* IBSS mode support */ 542 IEEE80211_C_IBSS | /* IBSS mode support */
543 IEEE80211_C_WPA | /* 802.11i */ 543 IEEE80211_C_WPA | /* 802.11i */
544 IEEE80211_C_MONITOR | /* monitor mode supported */ 544 IEEE80211_C_MONITOR | /* monitor mode supported */
545 IEEE80211_C_TXPMGT | /* tx power management */ 545 IEEE80211_C_TXPMGT | /* tx power management */
546 IEEE80211_C_SHSLOT | /* short slot time supported */ 546 IEEE80211_C_SHSLOT | /* short slot time supported */
547 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 547 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
548 IEEE80211_C_WME; /* 802.11e */ 548 IEEE80211_C_WME; /* 802.11e */
549 549
550#ifndef IEEE80211_NO_HT 550#ifndef IEEE80211_NO_HT
551 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 551 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
552 /* Set HT capabilities. */ 552 /* Set HT capabilities. */
553 ic->ic_htcaps = 553 ic->ic_htcaps =
554#if IWN_RBUF_SIZE == 8192 554#if IWN_RBUF_SIZE == 8192
555 IEEE80211_HTCAP_AMSDU7935 | 555 IEEE80211_HTCAP_AMSDU7935 |
556#endif 556#endif
557 IEEE80211_HTCAP_CBW20_40 | 557 IEEE80211_HTCAP_CBW20_40 |
558 IEEE80211_HTCAP_SGI20 | 558 IEEE80211_HTCAP_SGI20 |
559 IEEE80211_HTCAP_SGI40; 559 IEEE80211_HTCAP_SGI40;
560 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 560 if (sc->hw_type != IWN_HW_REV_TYPE_4965)
561 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 561 ic->ic_htcaps |= IEEE80211_HTCAP_GF;
562 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 562 if (sc->hw_type == IWN_HW_REV_TYPE_6050)
563 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 563 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN;
564 else 564 else
565 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 565 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS;
566 } 566 }
567#endif /* !IEEE80211_NO_HT */ 567#endif /* !IEEE80211_NO_HT */
568 568
569 /* Set supported legacy rates. */ 569 /* Set supported legacy rates. */
570 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 570 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b;
571 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 571 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g;
572 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 572 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) {
573 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 573 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a;
574 } 574 }
575#ifndef IEEE80211_NO_HT 575#ifndef IEEE80211_NO_HT
576 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 576 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
577 /* Set supported HT rates. */ 577 /* Set supported HT rates. */
578 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 578 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */
579 if (sc->nrxchains > 1) 579 if (sc->nrxchains > 1)
580 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 580 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */
581 if (sc->nrxchains > 2) 581 if (sc->nrxchains > 2)
582 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 582 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */
583 } 583 }
584#endif 584#endif
585 585
586 /* IBSS channel undefined for now. */ 586 /* IBSS channel undefined for now. */
587 ic->ic_ibss_chan = &ic->ic_channels[0]; 587 ic->ic_ibss_chan = &ic->ic_channels[0];
588 588
589 ifp->if_softc = sc; 589 ifp->if_softc = sc;
590 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 590 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
591 ifp->if_init = iwn_init; 591 ifp->if_init = iwn_init;
592 ifp->if_ioctl = iwn_ioctl; 592 ifp->if_ioctl = iwn_ioctl;
593 ifp->if_start = iwn_start; 593 ifp->if_start = iwn_start;
594 ifp->if_stop = iwn_stop; 594 ifp->if_stop = iwn_stop;
595 ifp->if_watchdog = iwn_watchdog; 595 ifp->if_watchdog = iwn_watchdog;
596 IFQ_SET_READY(&ifp->if_snd); 596 IFQ_SET_READY(&ifp->if_snd);
597 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 597 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
598 598
599 error = if_initialize(ifp); 599 error = if_initialize(ifp);
600 if (error != 0) { 600 if (error != 0) {
601 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 601 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n",
602 error); 602 error);
603 goto fail5; 603 goto fail5;
604 } 604 }
605 ieee80211_ifattach(ic); 605 ieee80211_ifattach(ic);
606 /* Use common softint-based if_input */ 606 /* Use common softint-based if_input */
607 ifp->if_percpuq = if_percpuq_create(ifp); 607 ifp->if_percpuq = if_percpuq_create(ifp);
608 if_register(ifp); 608 if_register(ifp);
609 609
610 ic->ic_node_alloc = iwn_node_alloc; 610 ic->ic_node_alloc = iwn_node_alloc;
611 ic->ic_newassoc = iwn_newassoc; 611 ic->ic_newassoc = iwn_newassoc;
612#ifdef IWN_HWCRYPTO 612#ifdef IWN_HWCRYPTO
613 ic->ic_crypto.cs_key_set = iwn_set_key; 613 ic->ic_crypto.cs_key_set = iwn_set_key;
614 ic->ic_crypto.cs_key_delete = iwn_delete_key; 614 ic->ic_crypto.cs_key_delete = iwn_delete_key;
615#endif 615#endif
616 ic->ic_wme.wme_update = iwn_wme_update; 616 ic->ic_wme.wme_update = iwn_wme_update;
617#ifndef IEEE80211_NO_HT 617#ifndef IEEE80211_NO_HT
618 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 618 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
619 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 619 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
620 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 620 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start;
621 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 621 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop;
622#endif 622#endif
623 623
624 /* Override 802.11 state transition machine. */ 624 /* Override 802.11 state transition machine. */
625 sc->sc_newstate = ic->ic_newstate; 625 sc->sc_newstate = ic->ic_newstate;
626 ic->ic_newstate = iwn_newstate; 626 ic->ic_newstate = iwn_newstate;
627 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 627 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status);
628 628
629 sc->amrr.amrr_min_success_threshold = 1; 629 sc->amrr.amrr_min_success_threshold = 1;
630 sc->amrr.amrr_max_success_threshold = 15; 630 sc->amrr.amrr_max_success_threshold = 15;
631 631
632 iwn_radiotap_attach(sc); 632 iwn_radiotap_attach(sc);
633 633
634 /* 634 /*
635 * XXX for NetBSD, OpenBSD timeout_set replaced by 635 * XXX for NetBSD, OpenBSD timeout_set replaced by
636 * callout_init and callout_setfunc, above. 636 * callout_init and callout_setfunc, above.
637 */ 637 */
638 638
639 if (pmf_device_register(self, NULL, iwn_resume)) 639 if (pmf_device_register(self, NULL, iwn_resume))
640 pmf_class_network_register(self, ifp); 640 pmf_class_network_register(self, ifp);
641 else 641 else
642 aprint_error_dev(self, "couldn't establish power handler\n"); 642 aprint_error_dev(self, "couldn't establish power handler\n");
643 643
644 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 644 /* XXX NetBSD add call to ieee80211_announce for dmesg. */
645 ieee80211_announce(ic); 645 ieee80211_announce(ic);
646 646
647 sc->sc_flags |= IWN_FLAG_ATTACHED; 647 sc->sc_flags |= IWN_FLAG_ATTACHED;
648 return; 648 return;
649 649
650 /* Free allocated memory if something failed during attachment. */ 650 /* Free allocated memory if something failed during attachment. */
651fail5: iwn_free_rx_ring(sc, &sc->rxq); 651fail5: iwn_free_rx_ring(sc, &sc->rxq);
652fail4: while (--i >= 0) 652fail4: while (--i >= 0)
653 iwn_free_tx_ring(sc, &sc->txq[i]); 653 iwn_free_tx_ring(sc, &sc->txq[i]);
654#ifdef IWN_USE_RBUF 654#ifdef IWN_USE_RBUF
655 iwn_free_rpool(sc); 655 iwn_free_rpool(sc);
656#endif 656#endif
657 iwn_free_sched(sc); 657 iwn_free_sched(sc);
658fail3: if (sc->ict != NULL) 658fail3: if (sc->ict != NULL)
659 iwn_free_ict(sc); 659 iwn_free_ict(sc);
660fail2: iwn_free_kw(sc); 660fail2: iwn_free_kw(sc);
661fail1: iwn_free_fwmem(sc); 661fail1: iwn_free_fwmem(sc);
662failih: pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 662failih: pci_intr_disestablish(sc->sc_pct, sc->sc_ih);
663 sc->sc_ih = NULL; 663 sc->sc_ih = NULL;
664failia: pci_intr_release(sc->sc_pct, sc->sc_pihp, 1); 664failia: pci_intr_release(sc->sc_pct, sc->sc_pihp, 1);
665 sc->sc_pihp = NULL; 665 sc->sc_pihp = NULL;
666failsi: softint_disestablish(sc->sc_soft_ih); 666failsi: softint_disestablish(sc->sc_soft_ih);
667 sc->sc_soft_ih = NULL; 667 sc->sc_soft_ih = NULL;
668unmap: bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 668unmap: bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz);
669} 669}
670 670
671int 671int
672iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 672iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid)
673{ 673{
674 struct iwn_ops *ops = &sc->ops; 674 struct iwn_ops *ops = &sc->ops;
675 675
676 ops->load_firmware = iwn4965_load_firmware; 676 ops->load_firmware = iwn4965_load_firmware;
677 ops->read_eeprom = iwn4965_read_eeprom; 677 ops->read_eeprom = iwn4965_read_eeprom;
678 ops->post_alive = iwn4965_post_alive; 678 ops->post_alive = iwn4965_post_alive;
679 ops->nic_config = iwn4965_nic_config; 679 ops->nic_config = iwn4965_nic_config;
680 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 680 ops->config_bt_coex = iwn_config_bt_coex_bluetooth;
681 ops->update_sched = iwn4965_update_sched; 681 ops->update_sched = iwn4965_update_sched;
682 ops->get_temperature = iwn4965_get_temperature; 682 ops->get_temperature = iwn4965_get_temperature;
683 ops->get_rssi = iwn4965_get_rssi; 683 ops->get_rssi = iwn4965_get_rssi;
684 ops->set_txpower = iwn4965_set_txpower; 684 ops->set_txpower = iwn4965_set_txpower;
685 ops->init_gains = iwn4965_init_gains; 685 ops->init_gains = iwn4965_init_gains;
686 ops->set_gains = iwn4965_set_gains; 686 ops->set_gains = iwn4965_set_gains;
687 ops->add_node = iwn4965_add_node; 687 ops->add_node = iwn4965_add_node;
688 ops->tx_done = iwn4965_tx_done; 688 ops->tx_done = iwn4965_tx_done;
689#ifndef IEEE80211_NO_HT 689#ifndef IEEE80211_NO_HT
690 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 690 ops->ampdu_tx_start = iwn4965_ampdu_tx_start;
691 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 691 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop;
692#endif 692#endif
693 sc->ntxqs = IWN4965_NTXQUEUES; 693 sc->ntxqs = IWN4965_NTXQUEUES;
694 sc->ndmachnls = IWN4965_NDMACHNLS; 694 sc->ndmachnls = IWN4965_NDMACHNLS;
695 sc->broadcast_id = IWN4965_ID_BROADCAST; 695 sc->broadcast_id = IWN4965_ID_BROADCAST;
696 sc->rxonsz = IWN4965_RXONSZ; 696 sc->rxonsz = IWN4965_RXONSZ;
697 sc->schedsz = IWN4965_SCHEDSZ; 697 sc->schedsz = IWN4965_SCHEDSZ;
698 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 698 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ;
699 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 699 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ;
700 sc->fwsz = IWN4965_FWSZ; 700 sc->fwsz = IWN4965_FWSZ;
701 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 701 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT;
702 sc->limits = &iwn4965_sensitivity_limits; 702 sc->limits = &iwn4965_sensitivity_limits;
703 sc->fwname = "iwlwifi-4965-2.ucode"; 703 sc->fwname = "iwlwifi-4965-2.ucode";
704 /* Override chains masks, ROM is known to be broken. */ 704 /* Override chains masks, ROM is known to be broken. */
705 sc->txchainmask = IWN_ANT_AB; 705 sc->txchainmask = IWN_ANT_AB;
706 sc->rxchainmask = IWN_ANT_ABC; 706 sc->rxchainmask = IWN_ANT_ABC;
707 707
708 return 0; 708 return 0;
709} 709}
710 710
711int 711int
712iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 712iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid)
713{ 713{
714 struct iwn_ops *ops = &sc->ops; 714 struct iwn_ops *ops = &sc->ops;
715 715
716 ops->load_firmware = iwn5000_load_firmware; 716 ops->load_firmware = iwn5000_load_firmware;
717 ops->read_eeprom = iwn5000_read_eeprom; 717 ops->read_eeprom = iwn5000_read_eeprom;
718 ops->post_alive = iwn5000_post_alive; 718 ops->post_alive = iwn5000_post_alive;
719 ops->nic_config = iwn5000_nic_config; 719 ops->nic_config = iwn5000_nic_config;
720 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 720 ops->config_bt_coex = iwn_config_bt_coex_bluetooth;
721 ops->update_sched = iwn5000_update_sched; 721 ops->update_sched = iwn5000_update_sched;
722 ops->get_temperature = iwn5000_get_temperature; 722 ops->get_temperature = iwn5000_get_temperature;
723 ops->get_rssi = iwn5000_get_rssi; 723 ops->get_rssi = iwn5000_get_rssi;
724 ops->set_txpower = iwn5000_set_txpower; 724 ops->set_txpower = iwn5000_set_txpower;
725 ops->init_gains = iwn5000_init_gains; 725 ops->init_gains = iwn5000_init_gains;
726 ops->set_gains = iwn5000_set_gains; 726 ops->set_gains = iwn5000_set_gains;
727 ops->add_node = iwn5000_add_node; 727 ops->add_node = iwn5000_add_node;
728 ops->tx_done = iwn5000_tx_done; 728 ops->tx_done = iwn5000_tx_done;
729#ifndef IEEE80211_NO_HT 729#ifndef IEEE80211_NO_HT
730 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 730 ops->ampdu_tx_start = iwn5000_ampdu_tx_start;
731 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 731 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop;
732#endif 732#endif
733 sc->ntxqs = IWN5000_NTXQUEUES; 733 sc->ntxqs = IWN5000_NTXQUEUES;
734 sc->ndmachnls = IWN5000_NDMACHNLS; 734 sc->ndmachnls = IWN5000_NDMACHNLS;
735 sc->broadcast_id = IWN5000_ID_BROADCAST; 735 sc->broadcast_id = IWN5000_ID_BROADCAST;
736 sc->rxonsz = IWN5000_RXONSZ; 736 sc->rxonsz = IWN5000_RXONSZ;
737 sc->schedsz = IWN5000_SCHEDSZ; 737 sc->schedsz = IWN5000_SCHEDSZ;
738 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 738 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ;
739 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 739 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ;
740 sc->fwsz = IWN5000_FWSZ; 740 sc->fwsz = IWN5000_FWSZ;
741 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 741 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT;
742 742
743 switch (sc->hw_type) { 743 switch (sc->hw_type) {
744 case IWN_HW_REV_TYPE_5100: 744 case IWN_HW_REV_TYPE_5100:
745 sc->limits = &iwn5000_sensitivity_limits; 745 sc->limits = &iwn5000_sensitivity_limits;
746 sc->fwname = "iwlwifi-5000-2.ucode"; 746 sc->fwname = "iwlwifi-5000-2.ucode";
747 /* Override chains masks, ROM is known to be broken. */ 747 /* Override chains masks, ROM is known to be broken. */
748 sc->txchainmask = IWN_ANT_B; 748 sc->txchainmask = IWN_ANT_B;
749 sc->rxchainmask = IWN_ANT_AB; 749 sc->rxchainmask = IWN_ANT_AB;
750 break; 750 break;
751 case IWN_HW_REV_TYPE_5150: 751 case IWN_HW_REV_TYPE_5150:
752 sc->limits = &iwn5150_sensitivity_limits; 752 sc->limits = &iwn5150_sensitivity_limits;
753 sc->fwname = "iwlwifi-5150-2.ucode"; 753 sc->fwname = "iwlwifi-5150-2.ucode";
754 break; 754 break;
755 case IWN_HW_REV_TYPE_5300: 755 case IWN_HW_REV_TYPE_5300:
756 case IWN_HW_REV_TYPE_5350: 756 case IWN_HW_REV_TYPE_5350:
757 sc->limits = &iwn5000_sensitivity_limits; 757 sc->limits = &iwn5000_sensitivity_limits;
758 sc->fwname = "iwlwifi-5000-2.ucode"; 758 sc->fwname = "iwlwifi-5000-2.ucode";
759 break; 759 break;
760 case IWN_HW_REV_TYPE_1000: 760 case IWN_HW_REV_TYPE_1000:
761 sc->limits = &iwn1000_sensitivity_limits; 761 sc->limits = &iwn1000_sensitivity_limits;
762 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_1 || 762 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_1 ||
763 pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_2) 763 pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_2)
764 sc->fwname = "iwlwifi-100-5.ucode"; 764 sc->fwname = "iwlwifi-100-5.ucode";
765 else 765 else
766 sc->fwname = "iwlwifi-1000-3.ucode"; 766 sc->fwname = "iwlwifi-1000-3.ucode";
767 break; 767 break;
768 case IWN_HW_REV_TYPE_6000: 768 case IWN_HW_REV_TYPE_6000:
769 sc->limits = &iwn6000_sensitivity_limits; 769 sc->limits = &iwn6000_sensitivity_limits;
770 sc->fwname = "iwlwifi-6000-4.ucode"; 770 sc->fwname = "iwlwifi-6000-4.ucode";
771 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 771 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 ||
772 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 772 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) {
773 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 773 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
774 /* Override chains masks, ROM is known to be broken. */ 774 /* Override chains masks, ROM is known to be broken. */
775 sc->txchainmask = IWN_ANT_BC; 775 sc->txchainmask = IWN_ANT_BC;
776 sc->rxchainmask = IWN_ANT_BC; 776 sc->rxchainmask = IWN_ANT_BC;
777 } 777 }
778 break; 778 break;
779 case IWN_HW_REV_TYPE_6050: 779 case IWN_HW_REV_TYPE_6050:
780 sc->limits = &iwn6000_sensitivity_limits; 780 sc->limits = &iwn6000_sensitivity_limits;
781 sc->fwname = "iwlwifi-6050-5.ucode"; 781 sc->fwname = "iwlwifi-6050-5.ucode";
782 break; 782 break;
783 case IWN_HW_REV_TYPE_6005: 783 case IWN_HW_REV_TYPE_6005:
784 sc->limits = &iwn6000_sensitivity_limits; 784 sc->limits = &iwn6000_sensitivity_limits;
785 /* Type 6030 cards return IWN_HW_REV_TYPE_6005 */ 785 /* Type 6030 cards return IWN_HW_REV_TYPE_6005 */
786 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 || 786 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 ||
787 pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 || 787 pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 ||
 788 pid == PCI_PRODUCT_INTEL_WIFI_LINK_130_1 ||
 789 pid == PCI_PRODUCT_INTEL_WIFI_LINK_130_2 ||
788 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 || 790 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 ||
789 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 || 791 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 ||
790 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235 || 792 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235 ||
791 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235_2) { 793 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235_2) {
792 sc->fwname = "iwlwifi-6000g2b-6.ucode"; 794 sc->fwname = "iwlwifi-6000g2b-6.ucode";
793 ops->config_bt_coex = iwn_config_bt_coex_adv1; 795 ops->config_bt_coex = iwn_config_bt_coex_adv1;
794 } 796 }
795 else 797 else
796 sc->fwname = "iwlwifi-6000g2a-5.ucode"; 798 sc->fwname = "iwlwifi-6000g2a-5.ucode";
797 break; 799 break;
798 case IWN_HW_REV_TYPE_2030: 800 case IWN_HW_REV_TYPE_2030:
799 sc->limits = &iwn2030_sensitivity_limits; 801 sc->limits = &iwn2030_sensitivity_limits;
800 sc->fwname = "iwlwifi-2030-6.ucode"; 802 sc->fwname = "iwlwifi-2030-6.ucode";
801 ops->config_bt_coex = iwn_config_bt_coex_adv2; 803 ops->config_bt_coex = iwn_config_bt_coex_adv2;
802 break; 804 break;
803 case IWN_HW_REV_TYPE_2000: 805 case IWN_HW_REV_TYPE_2000:
804 sc->limits = &iwn2000_sensitivity_limits; 806 sc->limits = &iwn2000_sensitivity_limits;
805 sc->fwname = "iwlwifi-2000-6.ucode"; 807 sc->fwname = "iwlwifi-2000-6.ucode";
806 break; 808 break;
807 case IWN_HW_REV_TYPE_135: 809 case IWN_HW_REV_TYPE_135:
808 sc->limits = &iwn2000_sensitivity_limits; 810 sc->limits = &iwn2000_sensitivity_limits;
809 sc->fwname = "iwlwifi-135-6.ucode"; 811 sc->fwname = "iwlwifi-135-6.ucode";
810 ops->config_bt_coex = iwn_config_bt_coex_adv2; 812 ops->config_bt_coex = iwn_config_bt_coex_adv2;
811 break; 813 break;
812 case IWN_HW_REV_TYPE_105: 814 case IWN_HW_REV_TYPE_105:
813 sc->limits = &iwn2000_sensitivity_limits; 815 sc->limits = &iwn2000_sensitivity_limits;
814 sc->fwname = "iwlwifi-105-6.ucode"; 816 sc->fwname = "iwlwifi-105-6.ucode";
815 break; 817 break;
816 default: 818 default:
817 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 819 aprint_normal(": adapter type %d not supported\n", sc->hw_type);
818 return ENOTSUP; 820 return ENOTSUP;
819 } 821 }
820 return 0; 822 return 0;
821} 823}
822 824
823/* 825/*
824 * Attach the interface to 802.11 radiotap. 826 * Attach the interface to 802.11 radiotap.
825 */ 827 */
826static void 828static void
827iwn_radiotap_attach(struct iwn_softc *sc) 829iwn_radiotap_attach(struct iwn_softc *sc)
828{ 830{
829 struct ifnet *ifp = sc->sc_ic.ic_ifp; 831 struct ifnet *ifp = sc->sc_ic.ic_ifp;
830 832
831 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 833 bpf_attach2(ifp, DLT_IEEE802_11_RADIO,
832 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 834 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN,
833 &sc->sc_drvbpf); 835 &sc->sc_drvbpf);
834 836
835 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 837 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
836 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 838 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
837 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 839 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT);
838 840
839 sc->sc_txtap_len = sizeof sc->sc_txtapu; 841 sc->sc_txtap_len = sizeof sc->sc_txtapu;
840 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 842 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
841 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 843 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT);
842} 844}
843 845
844static int 846static int
845iwn_detach(device_t self, int flags __unused) 847iwn_detach(device_t self, int flags __unused)
846{ 848{
847 struct iwn_softc *sc = device_private(self); 849 struct iwn_softc *sc = device_private(self);
848 struct ifnet *ifp = sc->sc_ic.ic_ifp; 850 struct ifnet *ifp = sc->sc_ic.ic_ifp;
849 int qid; 851 int qid;
850 852
851 if (!(sc->sc_flags & IWN_FLAG_ATTACHED)) 853 if (!(sc->sc_flags & IWN_FLAG_ATTACHED))
852 return 0; 854 return 0;
853 855
854 callout_stop(&sc->calib_to); 856 callout_stop(&sc->calib_to);
855 857
856 /* Uninstall interrupt handler. */ 858 /* Uninstall interrupt handler. */
857 if (sc->sc_ih != NULL) 859 if (sc->sc_ih != NULL)
858 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 860 pci_intr_disestablish(sc->sc_pct, sc->sc_ih);
859 if (sc->sc_pihp != NULL) 861 if (sc->sc_pihp != NULL)
860 pci_intr_release(sc->sc_pct, sc->sc_pihp, 1); 862 pci_intr_release(sc->sc_pct, sc->sc_pihp, 1);
861 if (sc->sc_soft_ih != NULL) 863 if (sc->sc_soft_ih != NULL)
862 softint_disestablish(sc->sc_soft_ih); 864 softint_disestablish(sc->sc_soft_ih);
863 865
864 /* Free DMA resources. */ 866 /* Free DMA resources. */
865 iwn_free_rx_ring(sc, &sc->rxq); 867 iwn_free_rx_ring(sc, &sc->rxq);
866 for (qid = 0; qid < sc->ntxqs; qid++) 868 for (qid = 0; qid < sc->ntxqs; qid++)
867 iwn_free_tx_ring(sc, &sc->txq[qid]); 869 iwn_free_tx_ring(sc, &sc->txq[qid]);
868#ifdef IWN_USE_RBUF 870#ifdef IWN_USE_RBUF
869 iwn_free_rpool(sc); 871 iwn_free_rpool(sc);
870#endif 872#endif
871 iwn_free_sched(sc); 873 iwn_free_sched(sc);
872 iwn_free_kw(sc); 874 iwn_free_kw(sc);
873 if (sc->ict != NULL) 875 if (sc->ict != NULL)
874 iwn_free_ict(sc); 876 iwn_free_ict(sc);
875 iwn_free_fwmem(sc); 877 iwn_free_fwmem(sc);
876 878
877 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 879 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz);
878 880
879 ieee80211_ifdetach(&sc->sc_ic); 881 ieee80211_ifdetach(&sc->sc_ic);
880 if_detach(ifp); 882 if_detach(ifp);
881 883
882 return 0; 884 return 0;
883} 885}
884 886
885#if 0 887#if 0
886/* 888/*
887 * XXX Investigate if clearing the PCI retry timeout could eliminate 889 * XXX Investigate if clearing the PCI retry timeout could eliminate
888 * the repeated scan calls. Also the calls to if_init and if_start 890 * the repeated scan calls. Also the calls to if_init and if_start
889 * are similar to the effect of adding the call to ifioctl_common . 891 * are similar to the effect of adding the call to ifioctl_common .
890 */ 892 */
891static void 893static void
892iwn_power(int why, void *arg) 894iwn_power(int why, void *arg)
893{ 895{
894 struct iwn_softc *sc = arg; 896 struct iwn_softc *sc = arg;
895 struct ifnet *ifp; 897 struct ifnet *ifp;
896 pcireg_t reg; 898 pcireg_t reg;
897 int s; 899 int s;
898 900
899 if (why != PWR_RESUME) 901 if (why != PWR_RESUME)
900 return; 902 return;
901 903
902 /* Clear device-specific "PCI retry timeout" register (41h). */ 904 /* Clear device-specific "PCI retry timeout" register (41h). */
903 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 905 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
904 if (reg & 0xff00) 906 if (reg & 0xff00)
905 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 907 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
906 908
907 s = splnet(); 909 s = splnet();
908 ifp = &sc->sc_ic.ic_if; 910 ifp = &sc->sc_ic.ic_if;
909 if (ifp->if_flags & IFF_UP) { 911 if (ifp->if_flags & IFF_UP) {
910 ifp->if_init(ifp); 912 ifp->if_init(ifp);
911 if (ifp->if_flags & IFF_RUNNING) 913 if (ifp->if_flags & IFF_RUNNING)
912 ifp->if_start(ifp); 914 ifp->if_start(ifp);
913 } 915 }
914 splx(s); 916 splx(s);
915} 917}
916#endif 918#endif
917 919
918static bool 920static bool
919iwn_resume(device_t dv, const pmf_qual_t *qual) 921iwn_resume(device_t dv, const pmf_qual_t *qual)
920{ 922{
921 return true; 923 return true;
922} 924}
923 925
924static int 926static int
925iwn_nic_lock(struct iwn_softc *sc) 927iwn_nic_lock(struct iwn_softc *sc)
926{ 928{
927 int ntries; 929 int ntries;
928 930
929 /* Request exclusive access to NIC. */ 931 /* Request exclusive access to NIC. */
930 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 932 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
931 933
932 /* Spin until we actually get the lock. */ 934 /* Spin until we actually get the lock. */
933 for (ntries = 0; ntries < 1000; ntries++) { 935 for (ntries = 0; ntries < 1000; ntries++) {
934 if ((IWN_READ(sc, IWN_GP_CNTRL) & 936 if ((IWN_READ(sc, IWN_GP_CNTRL) &
935 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 937 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
936 IWN_GP_CNTRL_MAC_ACCESS_ENA) 938 IWN_GP_CNTRL_MAC_ACCESS_ENA)
937 return 0; 939 return 0;
938 DELAY(10); 940 DELAY(10);
939 } 941 }
940 return ETIMEDOUT; 942 return ETIMEDOUT;
941} 943}
942 944
943static __inline void 945static __inline void
944iwn_nic_unlock(struct iwn_softc *sc) 946iwn_nic_unlock(struct iwn_softc *sc)
945{ 947{
946 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 948 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
947} 949}
948 950
949static __inline uint32_t 951static __inline uint32_t
950iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 952iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
951{ 953{
952 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 954 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
953 IWN_BARRIER_READ_WRITE(sc); 955 IWN_BARRIER_READ_WRITE(sc);
954 return IWN_READ(sc, IWN_PRPH_RDATA); 956 return IWN_READ(sc, IWN_PRPH_RDATA);
955} 957}
956 958
957static __inline void 959static __inline void
958iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 960iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
959{ 961{
960 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 962 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
961 IWN_BARRIER_WRITE(sc); 963 IWN_BARRIER_WRITE(sc);
962 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 964 IWN_WRITE(sc, IWN_PRPH_WDATA, data);
963} 965}
964 966
965static __inline void 967static __inline void
966iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 968iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
967{ 969{
968 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 970 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
969} 971}
970 972
971static __inline void 973static __inline void
972iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 974iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
973{ 975{
974 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 976 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
975} 977}
976 978
977static __inline void 979static __inline void
978iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 980iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
979 const uint32_t *data, int count) 981 const uint32_t *data, int count)
980{ 982{
981 for (; count > 0; count--, data++, addr += 4) 983 for (; count > 0; count--, data++, addr += 4)
982 iwn_prph_write(sc, addr, *data); 984 iwn_prph_write(sc, addr, *data);
983} 985}
984 986
985static __inline uint32_t 987static __inline uint32_t
986iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 988iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
987{ 989{
988 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 990 IWN_WRITE(sc, IWN_MEM_RADDR, addr);
989 IWN_BARRIER_READ_WRITE(sc); 991 IWN_BARRIER_READ_WRITE(sc);
990 return IWN_READ(sc, IWN_MEM_RDATA); 992 return IWN_READ(sc, IWN_MEM_RDATA);
991} 993}
992 994
993static __inline void 995static __inline void
994iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 996iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
995{ 997{
996 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 998 IWN_WRITE(sc, IWN_MEM_WADDR, addr);
997 IWN_BARRIER_WRITE(sc); 999 IWN_BARRIER_WRITE(sc);
998 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1000 IWN_WRITE(sc, IWN_MEM_WDATA, data);
999} 1001}
1000 1002
1001#ifndef IEEE80211_NO_HT 1003#ifndef IEEE80211_NO_HT
1002static __inline void 1004static __inline void
1003iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1005iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
1004{ 1006{
1005 uint32_t tmp; 1007 uint32_t tmp;
1006 1008
1007 tmp = iwn_mem_read(sc, addr & ~3); 1009 tmp = iwn_mem_read(sc, addr & ~3);
1008 if (addr & 3) 1010 if (addr & 3)
1009 tmp = (tmp & 0x0000ffff) | data << 16; 1011 tmp = (tmp & 0x0000ffff) | data << 16;
1010 else 1012 else
1011 tmp = (tmp & 0xffff0000) | data; 1013 tmp = (tmp & 0xffff0000) | data;
1012 iwn_mem_write(sc, addr & ~3, tmp); 1014 iwn_mem_write(sc, addr & ~3, tmp);
1013} 1015}
1014#endif 1016#endif
1015 1017
1016static __inline void 1018static __inline void
1017iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1019iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
1018 int count) 1020 int count)
1019{ 1021{
1020 for (; count > 0; count--, addr += 4) 1022 for (; count > 0; count--, addr += 4)
1021 *data++ = iwn_mem_read(sc, addr); 1023 *data++ = iwn_mem_read(sc, addr);
1022} 1024}
1023 1025
1024static __inline void 1026static __inline void
1025iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1027iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
1026 int count) 1028 int count)
1027{ 1029{
1028 for (; count > 0; count--, addr += 4) 1030 for (; count > 0; count--, addr += 4)
1029 iwn_mem_write(sc, addr, val); 1031 iwn_mem_write(sc, addr, val);
1030} 1032}
1031 1033
1032static int 1034static int
1033iwn_eeprom_lock(struct iwn_softc *sc) 1035iwn_eeprom_lock(struct iwn_softc *sc)
1034{ 1036{
1035 int i, ntries; 1037 int i, ntries;
1036 1038
1037 for (i = 0; i < 100; i++) { 1039 for (i = 0; i < 100; i++) {
1038 /* Request exclusive access to EEPROM. */ 1040 /* Request exclusive access to EEPROM. */
1039 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1041 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1040 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1042 IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1041 1043
1042 /* Spin until we actually get the lock. */ 1044 /* Spin until we actually get the lock. */
1043 for (ntries = 0; ntries < 100; ntries++) { 1045 for (ntries = 0; ntries < 100; ntries++) {
1044 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1046 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1045 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1047 IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1046 return 0; 1048 return 0;
1047 DELAY(10); 1049 DELAY(10);
1048 } 1050 }
1049 } 1051 }
1050 return ETIMEDOUT; 1052 return ETIMEDOUT;
1051} 1053}
1052 1054
1053static __inline void 1055static __inline void
1054iwn_eeprom_unlock(struct iwn_softc *sc) 1056iwn_eeprom_unlock(struct iwn_softc *sc)
1055{ 1057{
1056 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1058 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1057} 1059}
1058 1060
1059/* 1061/*
1060 * Initialize access by host to One Time Programmable ROM. 1062 * Initialize access by host to One Time Programmable ROM.
1061 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1063 * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1062 */ 1064 */
1063static int 1065static int
1064iwn_init_otprom(struct iwn_softc *sc) 1066iwn_init_otprom(struct iwn_softc *sc)
1065{ 1067{
1066 uint16_t prev = 0, base, next; 1068 uint16_t prev = 0, base, next;
1067 int count, error; 1069 int count, error;
1068 1070
1069 /* Wait for clock stabilization before accessing prph. */ 1071 /* Wait for clock stabilization before accessing prph. */
1070 if ((error = iwn_clock_wait(sc)) != 0) 1072 if ((error = iwn_clock_wait(sc)) != 0)
1071 return error; 1073 return error;
1072 1074
1073 if ((error = iwn_nic_lock(sc)) != 0) 1075 if ((error = iwn_nic_lock(sc)) != 0)
1074 return error; 1076 return error;
1075 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1077 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1076 DELAY(5); 1078 DELAY(5);
1077 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1079 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1078 iwn_nic_unlock(sc); 1080 iwn_nic_unlock(sc);
1079 1081
1080 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1082 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1081 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1083 if (sc->hw_type != IWN_HW_REV_TYPE_1000) {
1082 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1084 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1083 IWN_RESET_LINK_PWR_MGMT_DIS); 1085 IWN_RESET_LINK_PWR_MGMT_DIS);
1084 } 1086 }
1085 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1087 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1086 /* Clear ECC status. */ 1088 /* Clear ECC status. */
1087 IWN_SETBITS(sc, IWN_OTP_GP, 1089 IWN_SETBITS(sc, IWN_OTP_GP,
1088 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1090 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1089 1091
1090 /* 1092 /*
1091 * Find the block before last block (contains the EEPROM image) 1093 * Find the block before last block (contains the EEPROM image)
1092 * for HW without OTP shadow RAM. 1094 * for HW without OTP shadow RAM.
1093 */ 1095 */
1094 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1096 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
1095 /* Switch to absolute addressing mode. */ 1097 /* Switch to absolute addressing mode. */
1096 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1098 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1097 base = 0; 1099 base = 0;
1098 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1100 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) {
1099 error = iwn_read_prom_data(sc, base, &next, 2); 1101 error = iwn_read_prom_data(sc, base, &next, 2);
1100 if (error != 0) 1102 if (error != 0)
1101 return error; 1103 return error;
1102 if (next == 0) /* End of linked-list. */ 1104 if (next == 0) /* End of linked-list. */
1103 break; 1105 break;
1104 prev = base; 1106 prev = base;
1105 base = le16toh(next); 1107 base = le16toh(next);
1106 } 1108 }
1107 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1109 if (count == 0 || count == IWN1000_OTP_NBLOCKS)
1108 return EIO; 1110 return EIO;
1109 /* Skip "next" word. */ 1111 /* Skip "next" word. */
1110 sc->prom_base = prev + 1; 1112 sc->prom_base = prev + 1;
1111 } 1113 }
1112 return 0; 1114 return 0;
1113} 1115}
1114 1116
1115static int 1117static int
1116iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1118iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1117{ 1119{
1118 uint8_t *out = data; 1120 uint8_t *out = data;
1119 uint32_t val, tmp; 1121 uint32_t val, tmp;
1120 int ntries; 1122 int ntries;
1121 1123
1122 addr += sc->prom_base; 1124 addr += sc->prom_base;
1123 for (; count > 0; count -= 2, addr++) { 1125 for (; count > 0; count -= 2, addr++) {
1124 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1126 IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1125 for (ntries = 0; ntries < 10; ntries++) { 1127 for (ntries = 0; ntries < 10; ntries++) {
1126 val = IWN_READ(sc, IWN_EEPROM); 1128 val = IWN_READ(sc, IWN_EEPROM);
1127 if (val & IWN_EEPROM_READ_VALID) 1129 if (val & IWN_EEPROM_READ_VALID)
1128 break; 1130 break;
1129 DELAY(5); 1131 DELAY(5);
1130 } 1132 }
1131 if (ntries == 10) { 1133 if (ntries == 10) {
1132 aprint_error_dev(sc->sc_dev, 1134 aprint_error_dev(sc->sc_dev,
1133 "timeout reading ROM at 0x%x\n", addr); 1135 "timeout reading ROM at 0x%x\n", addr);
1134 return ETIMEDOUT; 1136 return ETIMEDOUT;
1135 } 1137 }
1136 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1138 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1137 /* OTPROM, check for ECC errors. */ 1139 /* OTPROM, check for ECC errors. */
1138 tmp = IWN_READ(sc, IWN_OTP_GP); 1140 tmp = IWN_READ(sc, IWN_OTP_GP);
1139 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1141 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1140 aprint_error_dev(sc->sc_dev, 1142 aprint_error_dev(sc->sc_dev,
1141 "OTPROM ECC error at 0x%x\n", addr); 1143 "OTPROM ECC error at 0x%x\n", addr);
1142 return EIO; 1144 return EIO;
1143 } 1145 }
1144 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1146 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1145 /* Correctable ECC error, clear bit. */ 1147 /* Correctable ECC error, clear bit. */
1146 IWN_SETBITS(sc, IWN_OTP_GP, 1148 IWN_SETBITS(sc, IWN_OTP_GP,
1147 IWN_OTP_GP_ECC_CORR_STTS); 1149 IWN_OTP_GP_ECC_CORR_STTS);
1148 } 1150 }
1149 } 1151 }
1150 *out++ = val >> 16; 1152 *out++ = val >> 16;
1151 if (count > 1) 1153 if (count > 1)
1152 *out++ = val >> 24; 1154 *out++ = val >> 24;
1153 } 1155 }
1154 return 0; 1156 return 0;
1155} 1157}
1156 1158
1157static int 1159static int
1158iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1160iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap,
1159 bus_size_t size, bus_size_t alignment) 1161 bus_size_t size, bus_size_t alignment)
1160{ 1162{
1161 int nsegs, error; 1163 int nsegs, error;
1162 1164
1163 dma->tag = tag; 1165 dma->tag = tag;
1164 dma->size = size; 1166 dma->size = size;
1165 1167
1166 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1168 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT,
1167 &dma->map); 1169 &dma->map);
1168 if (error != 0) 1170 if (error != 0)
1169 goto fail; 1171 goto fail;
1170 1172
1171 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1173 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs,
1172 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1174 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */
1173 if (error != 0) 1175 if (error != 0)
1174 goto fail; 1176 goto fail;
1175 1177
1176 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1178 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr,
1177 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1179 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */
1178 if (error != 0) 1180 if (error != 0)
1179 goto fail; 1181 goto fail;
1180 1182
1181 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1183 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL,
1182 BUS_DMA_NOWAIT); 1184 BUS_DMA_NOWAIT);
1183 if (error != 0) 1185 if (error != 0)
1184 goto fail; 1186 goto fail;
1185 1187
1186 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1188 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */
1187 memset(dma->vaddr, 0, size); 1189 memset(dma->vaddr, 0, size);
1188 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1190 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE);
1189 1191
1190 dma->paddr = dma->map->dm_segs[0].ds_addr; 1192 dma->paddr = dma->map->dm_segs[0].ds_addr;
1191 if (kvap != NULL) 1193 if (kvap != NULL)
1192 *kvap = dma->vaddr; 1194 *kvap = dma->vaddr;
1193 1195
1194 return 0; 1196 return 0;
1195 1197
1196fail: iwn_dma_contig_free(dma); 1198fail: iwn_dma_contig_free(dma);
1197 return error; 1199 return error;
1198} 1200}
1199 1201
1200static void 1202static void
1201iwn_dma_contig_free(struct iwn_dma_info *dma) 1203iwn_dma_contig_free(struct iwn_dma_info *dma)
1202{ 1204{
1203 if (dma->map != NULL) { 1205 if (dma->map != NULL) {
1204 if (dma->vaddr != NULL) { 1206 if (dma->vaddr != NULL) {
1205 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1207 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size,
1206 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1208 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1207 bus_dmamap_unload(dma->tag, dma->map); 1209 bus_dmamap_unload(dma->tag, dma->map);
1208 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1210 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size);
1209 bus_dmamem_free(dma->tag, &dma->seg, 1); 1211 bus_dmamem_free(dma->tag, &dma->seg, 1);
1210 dma->vaddr = NULL; 1212 dma->vaddr = NULL;
1211 } 1213 }
1212 bus_dmamap_destroy(dma->tag, dma->map); 1214 bus_dmamap_destroy(dma->tag, dma->map);
1213 dma->map = NULL; 1215 dma->map = NULL;
1214 } 1216 }
1215} 1217}
1216 1218
1217static int 1219static int
1218iwn_alloc_sched(struct iwn_softc *sc) 1220iwn_alloc_sched(struct iwn_softc *sc)
1219{ 1221{
1220 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1222 /* TX scheduler rings must be aligned on a 1KB boundary. */
1221 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1223 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma,
1222 (void **)&sc->sched, sc->schedsz, 1024); 1224 (void **)&sc->sched, sc->schedsz, 1024);
1223} 1225}
1224 1226
1225static void 1227static void
1226iwn_free_sched(struct iwn_softc *sc) 1228iwn_free_sched(struct iwn_softc *sc)
1227{ 1229{
1228 iwn_dma_contig_free(&sc->sched_dma); 1230 iwn_dma_contig_free(&sc->sched_dma);
1229} 1231}
1230 1232
1231static int 1233static int
1232iwn_alloc_kw(struct iwn_softc *sc) 1234iwn_alloc_kw(struct iwn_softc *sc)
1233{ 1235{
1234 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1236 /* "Keep Warm" page must be aligned on a 4KB boundary. */
1235 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1237 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096,
1236 4096); 1238 4096);
1237} 1239}
1238 1240
1239static void 1241static void
1240iwn_free_kw(struct iwn_softc *sc) 1242iwn_free_kw(struct iwn_softc *sc)
1241{ 1243{
1242 iwn_dma_contig_free(&sc->kw_dma); 1244 iwn_dma_contig_free(&sc->kw_dma);
1243} 1245}
1244 1246
1245static int 1247static int
1246iwn_alloc_ict(struct iwn_softc *sc) 1248iwn_alloc_ict(struct iwn_softc *sc)
1247{ 1249{
1248 /* ICT table must be aligned on a 4KB boundary. */ 1250 /* ICT table must be aligned on a 4KB boundary. */
1249 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1251 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma,
1250 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1252 (void **)&sc->ict, IWN_ICT_SIZE, 4096);
1251} 1253}
1252 1254
1253static void 1255static void
1254iwn_free_ict(struct iwn_softc *sc) 1256iwn_free_ict(struct iwn_softc *sc)
1255{ 1257{
1256 iwn_dma_contig_free(&sc->ict_dma); 1258 iwn_dma_contig_free(&sc->ict_dma);
1257} 1259}
1258 1260
1259static int 1261static int
1260iwn_alloc_fwmem(struct iwn_softc *sc) 1262iwn_alloc_fwmem(struct iwn_softc *sc)
1261{ 1263{
1262 /* Must be aligned on a 16-byte boundary. */ 1264 /* Must be aligned on a 16-byte boundary. */
1263 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1265 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL,
1264 sc->fwsz, 16); 1266 sc->fwsz, 16);
1265} 1267}
1266 1268
1267static void 1269static void
1268iwn_free_fwmem(struct iwn_softc *sc) 1270iwn_free_fwmem(struct iwn_softc *sc)
1269{ 1271{
1270 iwn_dma_contig_free(&sc->fw_dma); 1272 iwn_dma_contig_free(&sc->fw_dma);
1271} 1273}
1272 1274
1273static int 1275static int
1274iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1276iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1275{ 1277{
1276 bus_size_t size; 1278 bus_size_t size;
1277 int i, error; 1279 int i, error;
1278 1280
1279 ring->cur = 0; 1281 ring->cur = 0;
1280 1282
1281 /* Allocate RX descriptors (256-byte aligned). */ 1283 /* Allocate RX descriptors (256-byte aligned). */
1282 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1284 size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1283 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1285 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma,
1284 (void **)&ring->desc, size, 256); 1286 (void **)&ring->desc, size, 256);
1285 if (error != 0) { 1287 if (error != 0) {
1286 aprint_error_dev(sc->sc_dev, 1288 aprint_error_dev(sc->sc_dev,
1287 "could not allocate RX ring DMA memory\n"); 1289 "could not allocate RX ring DMA memory\n");
1288 goto fail; 1290 goto fail;
1289 } 1291 }
1290 1292
1291 /* Allocate RX status area (16-byte aligned). */ 1293 /* Allocate RX status area (16-byte aligned). */
1292 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1294 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma,
1293 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1295 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16);
1294 if (error != 0) { 1296 if (error != 0) {
1295 aprint_error_dev(sc->sc_dev, 1297 aprint_error_dev(sc->sc_dev,
1296 "could not allocate RX status DMA memory\n"); 1298 "could not allocate RX status DMA memory\n");
1297 goto fail; 1299 goto fail;
1298 } 1300 }
1299 1301
1300 /* 1302 /*
1301 * Allocate and map RX buffers. 1303 * Allocate and map RX buffers.
1302 */ 1304 */
1303 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1305 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1304 struct iwn_rx_data *data = &ring->data[i]; 1306 struct iwn_rx_data *data = &ring->data[i];
1305 1307
1306 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1308 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1,
1307 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1309 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
1308 &data->map); 1310 &data->map);
1309 if (error != 0) { 1311 if (error != 0) {
1310 aprint_error_dev(sc->sc_dev, 1312 aprint_error_dev(sc->sc_dev,
1311 "could not create RX buf DMA map\n"); 1313 "could not create RX buf DMA map\n");
1312 goto fail; 1314 goto fail;
1313 } 1315 }
1314 1316
1315 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1317 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE);
1316 if (data->m == NULL) { 1318 if (data->m == NULL) {
1317 aprint_error_dev(sc->sc_dev, 1319 aprint_error_dev(sc->sc_dev,
1318 "could not allocate RX mbuf\n"); 1320 "could not allocate RX mbuf\n");
1319 error = ENOBUFS; 1321 error = ENOBUFS;
1320 goto fail; 1322 goto fail;
1321 } 1323 }
1322 1324
1323 error = bus_dmamap_load(sc->sc_dmat, data->map, 1325 error = bus_dmamap_load(sc->sc_dmat, data->map,
1324 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1326 mtod(data->m, void *), IWN_RBUF_SIZE, NULL,
1325 BUS_DMA_NOWAIT | BUS_DMA_READ); 1327 BUS_DMA_NOWAIT | BUS_DMA_READ);
1326 if (error != 0) { 1328 if (error != 0) {
1327 aprint_error_dev(sc->sc_dev, 1329 aprint_error_dev(sc->sc_dev,
1328 "can't not map mbuf (error %d)\n", error); 1330 "can't not map mbuf (error %d)\n", error);
1329 goto fail; 1331 goto fail;
1330 } 1332 }
1331 1333
1332 /* Set physical address of RX buffer (256-byte aligned). */ 1334 /* Set physical address of RX buffer (256-byte aligned). */
1333 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1335 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8);
1334 } 1336 }
1335 1337
1336 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1338 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size,
1337 BUS_DMASYNC_PREWRITE); 1339 BUS_DMASYNC_PREWRITE);
1338 1340
1339 return 0; 1341 return 0;
1340 1342
1341fail: iwn_free_rx_ring(sc, ring); 1343fail: iwn_free_rx_ring(sc, ring);
1342 return error; 1344 return error;
1343} 1345}
1344 1346
1345static void 1347static void
1346iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1348iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1347{ 1349{
1348 int ntries; 1350 int ntries;
1349 1351
1350 if (iwn_nic_lock(sc) == 0) { 1352 if (iwn_nic_lock(sc) == 0) {
1351 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1353 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1352 for (ntries = 0; ntries < 1000; ntries++) { 1354 for (ntries = 0; ntries < 1000; ntries++) {
1353 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1355 if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1354 IWN_FH_RX_STATUS_IDLE) 1356 IWN_FH_RX_STATUS_IDLE)
1355 break; 1357 break;
1356 DELAY(10); 1358 DELAY(10);
1357 } 1359 }
1358 iwn_nic_unlock(sc); 1360 iwn_nic_unlock(sc);
1359 } 1361 }
1360 ring->cur = 0; 1362 ring->cur = 0;
1361 sc->last_rx_valid = 0; 1363 sc->last_rx_valid = 0;
1362} 1364}
1363 1365
1364static void 1366static void
1365iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1367iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1366{ 1368{
1367 int i; 1369 int i;
1368 1370
1369 iwn_dma_contig_free(&ring->desc_dma); 1371 iwn_dma_contig_free(&ring->desc_dma);
1370 iwn_dma_contig_free(&ring->stat_dma); 1372 iwn_dma_contig_free(&ring->stat_dma);
1371 1373
1372 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1374 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1373 struct iwn_rx_data *data = &ring->data[i]; 1375 struct iwn_rx_data *data = &ring->data[i];
1374 1376
1375 if (data->m != NULL) { 1377 if (data->m != NULL) {
1376 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1378 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
1377 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1379 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1378 bus_dmamap_unload(sc->sc_dmat, data->map); 1380 bus_dmamap_unload(sc->sc_dmat, data->map);
1379 m_freem(data->m); 1381 m_freem(data->m);
1380 } 1382 }
1381 if (data->map != NULL) 1383 if (data->map != NULL)
1382 bus_dmamap_destroy(sc->sc_dmat, data->map); 1384 bus_dmamap_destroy(sc->sc_dmat, data->map);
1383 } 1385 }
1384} 1386}
1385 1387
1386static int 1388static int
1387iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1389iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1388{ 1390{
1389 bus_addr_t paddr; 1391 bus_addr_t paddr;
1390 bus_size_t size; 1392 bus_size_t size;
1391 int i, error; 1393 int i, error;
1392 1394
1393 ring->qid = qid; 1395 ring->qid = qid;
1394 ring->queued = 0; 1396 ring->queued = 0;
1395 ring->cur = 0; 1397 ring->cur = 0;
1396 1398
1397 /* Allocate TX descriptors (256-byte aligned). */ 1399 /* Allocate TX descriptors (256-byte aligned). */
1398 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1400 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc);
1399 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1401 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma,
1400 (void **)&ring->desc, size, 256); 1402 (void **)&ring->desc, size, 256);
1401 if (error != 0) { 1403 if (error != 0) {
1402 aprint_error_dev(sc->sc_dev, 1404 aprint_error_dev(sc->sc_dev,
1403 "could not allocate TX ring DMA memory\n"); 1405 "could not allocate TX ring DMA memory\n");
1404 goto fail; 1406 goto fail;
1405 } 1407 }
1406 /* 1408 /*
1407 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1409 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need
1408 * to allocate commands space for other rings. 1410 * to allocate commands space for other rings.
1409 * XXX Do we really need to allocate descriptors for other rings? 1411 * XXX Do we really need to allocate descriptors for other rings?
1410 */ 1412 */
1411 if (qid > 4) 1413 if (qid > 4)
1412 return 0; 1414 return 0;
1413 1415
1414 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1416 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd);
1415 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1417 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma,
1416 (void **)&ring->cmd, size, 4); 1418 (void **)&ring->cmd, size, 4);
1417 if (error != 0) { 1419 if (error != 0) {
1418 aprint_error_dev(sc->sc_dev, 1420 aprint_error_dev(sc->sc_dev,
1419 "could not allocate TX cmd DMA memory\n"); 1421 "could not allocate TX cmd DMA memory\n");
1420 goto fail; 1422 goto fail;
1421 } 1423 }
1422 1424
1423 paddr = ring->cmd_dma.paddr; 1425 paddr = ring->cmd_dma.paddr;
1424 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1426 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1425 struct iwn_tx_data *data = &ring->data[i]; 1427 struct iwn_tx_data *data = &ring->data[i];
1426 1428
1427 data->cmd_paddr = paddr; 1429 data->cmd_paddr = paddr;
1428 data->scratch_paddr = paddr + 12; 1430 data->scratch_paddr = paddr + 12;
1429 paddr += sizeof (struct iwn_tx_cmd); 1431 paddr += sizeof (struct iwn_tx_cmd);
1430 1432
1431 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1433 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
1432 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1434 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT,
1433 &data->map); 1435 &data->map);
1434 if (error != 0) { 1436 if (error != 0) {
1435 aprint_error_dev(sc->sc_dev, 1437 aprint_error_dev(sc->sc_dev,
1436 "could not create TX buf DMA map\n"); 1438 "could not create TX buf DMA map\n");
1437 goto fail; 1439 goto fail;
1438 } 1440 }
1439 } 1441 }
1440 return 0; 1442 return 0;
1441 1443
1442fail: iwn_free_tx_ring(sc, ring); 1444fail: iwn_free_tx_ring(sc, ring);
1443 return error; 1445 return error;
1444} 1446}
1445 1447
1446static void 1448static void
1447iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1449iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1448{ 1450{
1449 int i; 1451 int i;
1450 1452
1451 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1453 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1452 struct iwn_tx_data *data = &ring->data[i]; 1454 struct iwn_tx_data *data = &ring->data[i];
1453 1455
1454 if (data->m != NULL) { 1456 if (data->m != NULL) {
1455 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1457 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
1456 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1458 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1457 bus_dmamap_unload(sc->sc_dmat, data->map); 1459 bus_dmamap_unload(sc->sc_dmat, data->map);
1458 m_freem(data->m); 1460 m_freem(data->m);
1459 data->m = NULL; 1461 data->m = NULL;
1460 } 1462 }
1461 } 1463 }
1462 /* Clear TX descriptors. */ 1464 /* Clear TX descriptors. */
1463 memset(ring->desc, 0, ring->desc_dma.size); 1465 memset(ring->desc, 0, ring->desc_dma.size);
1464 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1466 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0,
1465 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1467 ring->desc_dma.size, BUS_DMASYNC_PREWRITE);
1466 sc->qfullmsk &= ~(1 << ring->qid); 1468 sc->qfullmsk &= ~(1 << ring->qid);
1467 ring->queued = 0; 1469 ring->queued = 0;
1468 ring->cur = 0; 1470 ring->cur = 0;
1469} 1471}
1470 1472
1471static void 1473static void
1472iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1474iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1473{ 1475{
1474 int i; 1476 int i;
1475 1477
1476 iwn_dma_contig_free(&ring->desc_dma); 1478 iwn_dma_contig_free(&ring->desc_dma);
1477 iwn_dma_contig_free(&ring->cmd_dma); 1479 iwn_dma_contig_free(&ring->cmd_dma);
1478 1480
1479 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1481 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1480 struct iwn_tx_data *data = &ring->data[i]; 1482 struct iwn_tx_data *data = &ring->data[i];
1481 1483
1482 if (data->m != NULL) { 1484 if (data->m != NULL) {
1483 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1485 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
1484 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1486 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1485 bus_dmamap_unload(sc->sc_dmat, data->map); 1487 bus_dmamap_unload(sc->sc_dmat, data->map);
1486 m_freem(data->m); 1488 m_freem(data->m);
1487 } 1489 }
1488 if (data->map != NULL) 1490 if (data->map != NULL)
1489 bus_dmamap_destroy(sc->sc_dmat, data->map); 1491 bus_dmamap_destroy(sc->sc_dmat, data->map);
1490 } 1492 }
1491} 1493}
1492 1494
1493static void 1495static void
1494iwn5000_ict_reset(struct iwn_softc *sc) 1496iwn5000_ict_reset(struct iwn_softc *sc)
1495{ 1497{
1496 /* Disable interrupts. */ 1498 /* Disable interrupts. */
1497 IWN_WRITE(sc, IWN_INT_MASK, 0); 1499 IWN_WRITE(sc, IWN_INT_MASK, 0);
1498 1500
1499 /* Reset ICT table. */ 1501 /* Reset ICT table. */
1500 memset(sc->ict, 0, IWN_ICT_SIZE); 1502 memset(sc->ict, 0, IWN_ICT_SIZE);
1501 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 0, IWN_ICT_SIZE, 1503 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 0, IWN_ICT_SIZE,
1502 BUS_DMASYNC_PREWRITE); 1504 BUS_DMASYNC_PREWRITE);
1503 sc->ict_cur = 0; 1505 sc->ict_cur = 0;
1504 1506
1505 /* Set physical address of ICT table (4KB aligned). */ 1507 /* Set physical address of ICT table (4KB aligned). */
1506 DPRINTF(("enabling ICT\n")); 1508 DPRINTF(("enabling ICT\n"));
1507 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1509 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
1508 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1510 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
1509 1511
1510 /* Enable periodic RX interrupt. */ 1512 /* Enable periodic RX interrupt. */
1511 sc->int_mask |= IWN_INT_RX_PERIODIC; 1513 sc->int_mask |= IWN_INT_RX_PERIODIC;
1512 /* Switch to ICT interrupt mode in driver. */ 1514 /* Switch to ICT interrupt mode in driver. */
1513 sc->sc_flags |= IWN_FLAG_USE_ICT; 1515 sc->sc_flags |= IWN_FLAG_USE_ICT;
1514 1516
1515 /* Re-enable interrupts. */ 1517 /* Re-enable interrupts. */
1516 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1518 IWN_WRITE(sc, IWN_INT, 0xffffffff);
1517 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1519 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
1518} 1520}
1519 1521
1520static int 1522static int
1521iwn_read_eeprom(struct iwn_softc *sc) 1523iwn_read_eeprom(struct iwn_softc *sc)
1522{ 1524{
1523 struct iwn_ops *ops = &sc->ops; 1525 struct iwn_ops *ops = &sc->ops;
1524 struct ieee80211com *ic = &sc->sc_ic; 1526 struct ieee80211com *ic = &sc->sc_ic;
1525 uint16_t val; 1527 uint16_t val;
1526 int error; 1528 int error;
1527 1529
1528 /* Check whether adapter has an EEPROM or an OTPROM. */ 1530 /* Check whether adapter has an EEPROM or an OTPROM. */
1529 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1531 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
1530 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1532 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
1531 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1533 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
1532 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1534 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ?
1533 "OTPROM" : "EEPROM")); 1535 "OTPROM" : "EEPROM"));
1534 1536
1535 /* Adapter has to be powered on for EEPROM access to work. */ 1537 /* Adapter has to be powered on for EEPROM access to work. */
1536 if ((error = iwn_apm_init(sc)) != 0) { 1538 if ((error = iwn_apm_init(sc)) != 0) {
1537 aprint_error_dev(sc->sc_dev, 1539 aprint_error_dev(sc->sc_dev,
1538 "could not power ON adapter\n"); 1540 "could not power ON adapter\n");
1539 return error; 1541 return error;
1540 } 1542 }
1541 1543
1542 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1544 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
1543 aprint_error_dev(sc->sc_dev, 1545 aprint_error_dev(sc->sc_dev,
1544 "bad ROM signature\n"); 1546 "bad ROM signature\n");
1545 return EIO; 1547 return EIO;
1546 } 1548 }
1547 if ((error = iwn_eeprom_lock(sc)) != 0) { 1549 if ((error = iwn_eeprom_lock(sc)) != 0) {
1548 aprint_error_dev(sc->sc_dev, 1550 aprint_error_dev(sc->sc_dev,
1549 "could not lock ROM (error=%d)\n", error); 1551 "could not lock ROM (error=%d)\n", error);
1550 return error; 1552 return error;
1551 } 1553 }
1552 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1554 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1553 if ((error = iwn_init_otprom(sc)) != 0) { 1555 if ((error = iwn_init_otprom(sc)) != 0) {
1554 aprint_error_dev(sc->sc_dev, 1556 aprint_error_dev(sc->sc_dev,
1555 "could not initialize OTPROM\n"); 1557 "could not initialize OTPROM\n");
1556 return error; 1558 return error;
1557 } 1559 }
1558 } 1560 }
1559 1561
1560 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1562 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2);
1561 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1563 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val)));
1562 /* Check if HT support is bonded out. */ 1564 /* Check if HT support is bonded out. */
1563 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1565 if (val & htole16(IWN_EEPROM_SKU_CAP_11N))
1564 sc->sc_flags |= IWN_FLAG_HAS_11N; 1566 sc->sc_flags |= IWN_FLAG_HAS_11N;
1565 1567
1566 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1568 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
1567 sc->rfcfg = le16toh(val); 1569 sc->rfcfg = le16toh(val);
1568 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1570 DPRINTF(("radio config=0x%04x\n", sc->rfcfg));
1569 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1571 /* Read Tx/Rx chains from ROM unless it's known to be broken. */
1570 if (sc->txchainmask == 0) 1572 if (sc->txchainmask == 0)
1571 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1573 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg);
1572 if (sc->rxchainmask == 0) 1574 if (sc->rxchainmask == 0)
1573 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1575 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg);
1574 1576
1575 /* Read MAC address. */ 1577 /* Read MAC address. */
1576 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1578 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6);
1577 1579
1578 /* Read adapter-specific information from EEPROM. */ 1580 /* Read adapter-specific information from EEPROM. */
1579 ops->read_eeprom(sc); 1581 ops->read_eeprom(sc);
1580 1582
1581 iwn_apm_stop(sc); /* Power OFF adapter. */ 1583 iwn_apm_stop(sc); /* Power OFF adapter. */
1582 1584
1583 iwn_eeprom_unlock(sc); 1585 iwn_eeprom_unlock(sc);
1584 return 0; 1586 return 0;
1585} 1587}
1586 1588
1587static void 1589static void
1588iwn4965_read_eeprom(struct iwn_softc *sc) 1590iwn4965_read_eeprom(struct iwn_softc *sc)
1589{ 1591{
1590 uint32_t addr; 1592 uint32_t addr;
1591 uint16_t val; 1593 uint16_t val;
1592 int i; 1594 int i;
1593 1595
1594 /* Read regulatory domain (4 ASCII characters). */ 1596 /* Read regulatory domain (4 ASCII characters). */
1595 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1597 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
1596 1598
1597 /* Read the list of authorized channels (20MHz ones only). */ 1599 /* Read the list of authorized channels (20MHz ones only). */
1598 for (i = 0; i < 5; i++) { 1600 for (i = 0; i < 5; i++) {
1599 addr = iwn4965_regulatory_bands[i]; 1601 addr = iwn4965_regulatory_bands[i];
1600 iwn_read_eeprom_channels(sc, i, addr); 1602 iwn_read_eeprom_channels(sc, i, addr);
1601 } 1603 }
1602 1604
1603 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1605 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */
1604 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1606 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
1605 sc->maxpwr2GHz = val & 0xff; 1607 sc->maxpwr2GHz = val & 0xff;
1606 sc->maxpwr5GHz = val >> 8; 1608 sc->maxpwr5GHz = val >> 8;
1607 /* Check that EEPROM values are within valid range. */ 1609 /* Check that EEPROM values are within valid range. */
1608 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1610 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
1609 sc->maxpwr5GHz = 38; 1611 sc->maxpwr5GHz = 38;
1610 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1612 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
1611 sc->maxpwr2GHz = 38; 1613 sc->maxpwr2GHz = 38;
1612 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1614 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz));
1613 1615
1614 /* Read samples for each TX power group. */ 1616 /* Read samples for each TX power group. */
1615 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1617 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
1616 sizeof sc->bands); 1618 sizeof sc->bands);
1617 1619
1618 /* Read voltage at which samples were taken. */ 1620 /* Read voltage at which samples were taken. */
1619 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1621 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
1620 sc->eeprom_voltage = (int16_t)le16toh(val); 1622 sc->eeprom_voltage = (int16_t)le16toh(val);
1621 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1623 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage));
1622 1624
1623#ifdef IWN_DEBUG 1625#ifdef IWN_DEBUG
1624 /* Print samples. */ 1626 /* Print samples. */
1625 if (iwn_debug > 0) { 1627 if (iwn_debug > 0) {
1626 for (i = 0; i < IWN_NBANDS; i++) 1628 for (i = 0; i < IWN_NBANDS; i++)
1627 iwn4965_print_power_group(sc, i); 1629 iwn4965_print_power_group(sc, i);
1628 } 1630 }
1629#endif 1631#endif
1630} 1632}
1631 1633
1632#ifdef IWN_DEBUG 1634#ifdef IWN_DEBUG
1633static void 1635static void
1634iwn4965_print_power_group(struct iwn_softc *sc, int i) 1636iwn4965_print_power_group(struct iwn_softc *sc, int i)
1635{ 1637{
1636 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1638 struct iwn4965_eeprom_band *band = &sc->bands[i];
1637 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1639 struct iwn4965_eeprom_chan_samples *chans = band->chans;
1638 int j, c; 1640 int j, c;
1639 1641
1640 aprint_normal("===band %d===\n", i); 1642 aprint_normal("===band %d===\n", i);
1641 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1643 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
1642 aprint_normal("chan1 num=%d\n", chans[0].num); 1644 aprint_normal("chan1 num=%d\n", chans[0].num);
1643 for (c = 0; c < 2; c++) { 1645 for (c = 0; c < 2; c++) {
1644 for (j = 0; j < IWN_NSAMPLES; j++) { 1646 for (j = 0; j < IWN_NSAMPLES; j++) {
1645 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1647 aprint_normal("chain %d, sample %d: temp=%d gain=%d "
1646 "power=%d pa_det=%d\n", c, j, 1648 "power=%d pa_det=%d\n", c, j,
1647 chans[0].samples[c][j].temp, 1649 chans[0].samples[c][j].temp,
1648 chans[0].samples[c][j].gain, 1650 chans[0].samples[c][j].gain,
1649 chans[0].samples[c][j].power, 1651 chans[0].samples[c][j].power,
1650 chans[0].samples[c][j].pa_det); 1652 chans[0].samples[c][j].pa_det);
1651 } 1653 }
1652 } 1654 }
1653 aprint_normal("chan2 num=%d\n", chans[1].num); 1655 aprint_normal("chan2 num=%d\n", chans[1].num);
1654 for (c = 0; c < 2; c++) { 1656 for (c = 0; c < 2; c++) {
1655 for (j = 0; j < IWN_NSAMPLES; j++) { 1657 for (j = 0; j < IWN_NSAMPLES; j++) {
1656 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1658 aprint_normal("chain %d, sample %d: temp=%d gain=%d "
1657 "power=%d pa_det=%d\n", c, j, 1659 "power=%d pa_det=%d\n", c, j,
1658 chans[1].samples[c][j].temp, 1660 chans[1].samples[c][j].temp,
1659 chans[1].samples[c][j].gain, 1661 chans[1].samples[c][j].gain,
1660 chans[1].samples[c][j].power, 1662 chans[1].samples[c][j].power,
1661 chans[1].samples[c][j].pa_det); 1663 chans[1].samples[c][j].pa_det);
1662 } 1664 }
1663 } 1665 }
1664} 1666}
1665#endif 1667#endif
1666 1668
1667static void 1669static void
1668iwn5000_read_eeprom(struct iwn_softc *sc) 1670iwn5000_read_eeprom(struct iwn_softc *sc)
1669{ 1671{
1670 struct iwn5000_eeprom_calib_hdr hdr; 1672 struct iwn5000_eeprom_calib_hdr hdr;
1671 int32_t volt; 1673 int32_t volt;
1672 uint32_t base, addr; 1674 uint32_t base, addr;
1673 uint16_t val; 1675 uint16_t val;
1674 int i; 1676 int i;
1675 1677
1676 /* Read regulatory domain (4 ASCII characters). */ 1678 /* Read regulatory domain (4 ASCII characters). */
1677 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1679 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1678 base = le16toh(val); 1680 base = le16toh(val);
1679 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1681 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
1680 sc->eeprom_domain, 4); 1682 sc->eeprom_domain, 4);
1681 1683
1682 /* Read the list of authorized channels (20MHz ones only). */ 1684 /* Read the list of authorized channels (20MHz ones only). */
1683 for (i = 0; i < 5; i++) { 1685 for (i = 0; i < 5; i++) {
1684 addr = base + iwn5000_regulatory_bands[i]; 1686 addr = base + iwn5000_regulatory_bands[i];
1685 iwn_read_eeprom_channels(sc, i, addr); 1687 iwn_read_eeprom_channels(sc, i, addr);
1686 } 1688 }
1687 1689
1688 /* Read enhanced TX power information for 6000 Series. */ 1690 /* Read enhanced TX power information for 6000 Series. */
1689 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1691 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1690 iwn_read_eeprom_enhinfo(sc); 1692 iwn_read_eeprom_enhinfo(sc);
1691 1693
1692 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1694 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
1693 base = le16toh(val); 1695 base = le16toh(val);
1694 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1696 iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
1695 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1697 DPRINTF(("calib version=%u pa type=%u voltage=%u\n",
1696 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1698 hdr.version, hdr.pa_type, le16toh(hdr.volt)));
1697 sc->calib_ver = hdr.version; 1699 sc->calib_ver = hdr.version;
1698 1700
1699 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1701 if (sc->hw_type == IWN_HW_REV_TYPE_2030 ||
1700 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1702 sc->hw_type == IWN_HW_REV_TYPE_2000 ||
1701 sc->hw_type == IWN_HW_REV_TYPE_135 || 1703 sc->hw_type == IWN_HW_REV_TYPE_135 ||
1702 sc->hw_type == IWN_HW_REV_TYPE_105) { 1704 sc->hw_type == IWN_HW_REV_TYPE_105) {
1703 sc->eeprom_voltage = le16toh(hdr.volt); 1705 sc->eeprom_voltage = le16toh(hdr.volt);
1704 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1706 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1705 sc->eeprom_temp = le16toh(val); 1707 sc->eeprom_temp = le16toh(val);
1706 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1708 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2);
1707 sc->eeprom_rawtemp = le16toh(val); 1709 sc->eeprom_rawtemp = le16toh(val);
1708 } 1710 }
1709 1711
1710 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1712 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
1711 /* Compute temperature offset. */ 1713 /* Compute temperature offset. */
1712 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1714 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1713 sc->eeprom_temp = le16toh(val); 1715 sc->eeprom_temp = le16toh(val);
1714 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1716 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
1715 volt = le16toh(val); 1717 volt = le16toh(val);
1716 sc->temp_off = sc->eeprom_temp - (volt / -5); 1718 sc->temp_off = sc->eeprom_temp - (volt / -5);
1717 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1719 DPRINTF(("temp=%d volt=%d offset=%dK\n",
1718 sc->eeprom_temp, volt, sc->temp_off)); 1720 sc->eeprom_temp, volt, sc->temp_off));
1719 } else { 1721 } else {
1720 /* Read crystal calibration. */ 1722 /* Read crystal calibration. */
1721 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1723 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
1722 &sc->eeprom_crystal, sizeof (uint32_t)); 1724 &sc->eeprom_crystal, sizeof (uint32_t));
1723 DPRINTF(("crystal calibration 0x%08x\n", 1725 DPRINTF(("crystal calibration 0x%08x\n",
1724 le32toh(sc->eeprom_crystal))); 1726 le32toh(sc->eeprom_crystal)));
1725 } 1727 }
1726} 1728}
1727 1729
1728static void 1730static void
1729iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1731iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
1730{ 1732{
1731 struct ieee80211com *ic = &sc->sc_ic; 1733 struct ieee80211com *ic = &sc->sc_ic;
1732 const struct iwn_chan_band *band = &iwn_bands[n]; 1734 const struct iwn_chan_band *band = &iwn_bands[n];
1733 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1735 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND];
1734 uint8_t chan; 1736 uint8_t chan;
1735 int i; 1737 int i;
1736 1738
1737 iwn_read_prom_data(sc, addr, channels, 1739 iwn_read_prom_data(sc, addr, channels,
1738 band->nchan * sizeof (struct iwn_eeprom_chan)); 1740 band->nchan * sizeof (struct iwn_eeprom_chan));
1739 1741
1740 for (i = 0; i < band->nchan; i++) { 1742 for (i = 0; i < band->nchan; i++) {
1741 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1743 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID))
1742 continue; 1744 continue;
1743 1745
1744 chan = band->chan[i]; 1746 chan = band->chan[i];
1745 1747
1746 if (n == 0) { /* 2GHz band */ 1748 if (n == 0) { /* 2GHz band */
1747 ic->ic_channels[chan].ic_freq = 1749 ic->ic_channels[chan].ic_freq =
1748 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1750 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ);
1749 ic->ic_channels[chan].ic_flags = 1751 ic->ic_channels[chan].ic_flags =
1750 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1752 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
1751 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1753 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
1752 1754
1753 } else { /* 5GHz band */ 1755 } else { /* 5GHz band */
1754 /* 1756 /*
1755 * Some adapters support channels 7, 8, 11 and 12 1757 * Some adapters support channels 7, 8, 11 and 12
1756 * both in the 2GHz and 4.9GHz bands. 1758 * both in the 2GHz and 4.9GHz bands.
1757 * Because of limitations in our net80211 layer, 1759 * Because of limitations in our net80211 layer,
1758 * we don't support them in the 4.9GHz band. 1760 * we don't support them in the 4.9GHz band.
1759 */ 1761 */
1760 if (chan <= 14) 1762 if (chan <= 14)
1761 continue; 1763 continue;
1762 1764
1763 ic->ic_channels[chan].ic_freq = 1765 ic->ic_channels[chan].ic_freq =
1764 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1766 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ);
1765 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1767 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A;
1766 /* We have at least one valid 5GHz channel. */ 1768 /* We have at least one valid 5GHz channel. */
1767 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1769 sc->sc_flags |= IWN_FLAG_HAS_5GHZ;
1768 } 1770 }
1769 1771
1770 /* Is active scan allowed on this channel? */ 1772 /* Is active scan allowed on this channel? */
1771 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1773 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) {
1772 ic->ic_channels[chan].ic_flags |= 1774 ic->ic_channels[chan].ic_flags |=
1773 IEEE80211_CHAN_PASSIVE; 1775 IEEE80211_CHAN_PASSIVE;
1774 } 1776 }
1775 1777
1776 /* Save maximum allowed TX power for this channel. */ 1778 /* Save maximum allowed TX power for this channel. */
1777 sc->maxpwr[chan] = channels[i].maxpwr; 1779 sc->maxpwr[chan] = channels[i].maxpwr;
1778 1780
1779 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1781 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n",
1780 chan, channels[i].flags, sc->maxpwr[chan])); 1782 chan, channels[i].flags, sc->maxpwr[chan]));
1781 } 1783 }
1782} 1784}
1783 1785
1784static void 1786static void
1785iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1787iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
1786{ 1788{