 @@ -1,14 +1,14 @@
-/*	$NetBSD: pmap.c,v 1.437.4.3 2023/12/14 17:43:10 martin Exp $	*/
+/*	$NetBSD: pmap.c,v 1.437.4.4 2024/04/18 18:14:22 martin Exp $	*/
 /*
  * Copyright 2003 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Steve C. Woodford for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -183,27 +183,27 @@
 #include "opt_arm_debug.h"
 #include "opt_cpuoptions.h"
 #include "opt_ddb.h"
 #include "opt_efi.h"
 #include "opt_lockdebug.h"
 #include "opt_multiprocessor.h"
 #ifdef MULTIPROCESSOR
 #define _INTR_PRIVATE
 #endif
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.437.4.3 2023/12/14 17:43:10 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.437.4.4 2024/04/18 18:14:22 martin Exp $");
 #include <sys/param.h>
 #include <sys/types.h>
 #include <sys/asan.h>
 #include <sys/atomic.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/intr.h>
 #include <sys/kernel.h>
 #include <sys/kernhist.h>
 #include <sys/kmem.h>
 #include <sys/pool.h>
 @@ -2320,35 +2320,30 @@ pmap_vac_me_harder(struct vm_page_md *md
 /*
  * Modify pte bits for all ptes corresponding to the given physical address.
  * We use `maskbits' rather than `clearbits' because we're always passing
  * constants and the latter would require an extra inversion at run-time.
  */
 static void
 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits)
+{
 	struct pv_entry *pv;
 #ifdef PMAP_CACHE_VIPT
 	const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs);
 	bool need_syncicache = false;
-#ifdef ARM_MMU_EXTENDED
+#ifndef ARM_MMU_EXTENDED
 	const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0;
 #else
 	const u_int execbits = 0;
 	bool need_vac_me_harder = false;
 #endif
-#else
+#endif /* PMAP_CACHE_VIPT */
 	const u_int execbits = 0;
 #endif
 	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx maskbits %#jx",
 	    (uintptr_t)md, pa, maskbits, 0);
 #ifdef PMAP_CACHE_VIPT
 	/*
 	 * If we might want to sync the I-cache and we've modified it,
 	 * then we know we definitely need to sync or discard it.
 	 */
 	if (want_syncicache) {
 		if (md->pvh_attrs & PVF_MOD) {
 			need_syncicache = true;
 @@ -2411,29 +2406,34 @@ pmap_clearbit(struct vm_page_md *md, pad
 			pmap_destroy(pm);
 			/* Restart from the beginning. */
 			pmap_acquire_page_lock(md);
 			pv = SLIST_FIRST(&md->pvh_list);
 			continue;
+		}
 		pv->pv_flags &= ~maskbits;
 		struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va);
 		KASSERTMSG(l2b != NULL, "%#lx", va);
 		pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)];
 		const pt_entry_t opte = *ptep;
-		pt_entry_t npte = opte | execbits;
+		pt_entry_t npte = opte;
 #if defined(ARM_MMU_EXTENDED)
 		if ((maskbits & PVF_EXEC) != 0 && l2pte_valid_p(opte)) {
 			KASSERT((opte & L2_TYPE_S) != 0);
 			npte |= L2_XS_XN;
+		}
 #ifdef ARM_MMU_EXTENDED
 		KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG));
 #endif
 		UVMHIST_LOG(maphist, "pv %#jx pm %#jx va %#jx flag %#jx",
 		    (uintptr_t)pv, (uintptr_t)pm, va, oflags);
 		if (maskbits & (PVF_WRITE|PVF_MOD)) {
 #ifdef PMAP_CACHE_VIVT
 			if ((oflags & PVF_NC)) {
 				/*
 				 * Entry is not cacheable:
+				 *
 				 * Don't turn caching on again if this is a