 @@ -1,14 +1,14 @@
-# $NetBSD: Makefile,v 1.39 2023/07/16 22:20:54 rjs Exp $
+# $NetBSD: Makefile,v 1.40 2024/04/21 00:23:23 maya Exp $
 # Link the mesa_dri_drivers mega driver.
 .include <bsd.own.mk>
 .include "../mesa-which.mk"
 .if ${MACHINE_ARCH} == "i386" || ${MACHINE_ARCH} == "x86_64" || \
     ${MACHINE} == "evbarm"
 LIBISMODULE=	yes
 LIBISCXX=     yes
 @@ -111,29 +111,31 @@ CPPFLAGS.i915_${_f}+=	-I${X11SRCDIR.Mesa
 .PATH: ${X11SRCDIR.Mesa}/src/intel/dev
 .PATH: ${X11SRCDIR.Mesa}/src/intel/ds
 .PATH: ${X11SRCDIR.Mesa}/src/intel/isl
 .PATH: ${X11SRCDIR.Mesa}/src/intel/perf
 .PATH: ${X11SRCDIR.Mesa}/../src/intel/
 .PATH: ${X11SRCDIR.Mesa}/../src/intel/compiler
 .PATH: ${X11SRCDIR.Mesa}/../src/intel/isl
 .PATH: ${X11SRCDIR.Mesa}/../src/intel/perf
 DRI_SOURCES.i965+= \
 	blorp.c \
 	blorp_blit.c \
 	blorp_clear.c \
 	brw_batch.c \
 	brw_binding_tables.c \
 	brw_blit.c \
 	brw_blorp.c \
 	brw_mipmap_tree.c \
 	brw_buffer_objects.c \
 	brw_buffers.c \
 	brw_bufmgr.c \
 	brw_cfg.cpp \
 	brw_clear.c \
 	brw_clip.c \
 	brw_clip_line.c \
 	brw_clip_point.c \
 	brw_clip_tri.c \
 	brw_clip_unfilled.c \
 	brw_clip_util.c \
 	brw_compile_clip.c \
 	brw_compile_ff_gs.c \
 @@ -148,72 +150,76 @@ DRI_SOURCES.i965+= \
 	brw_dead_control_flow.cpp \
 	brw_debug_recompile.c \
 	brw_disasm.c \
 	brw_disasm_info.c \
 	brw_disk_cache.c \
 	brw_draw.c \
 	brw_draw_upload.c \
 	brw_eu.cpp \
 	brw_eu_compact.c \
 	brw_eu_emit.c \
 	brw_eu_util.c \
 	brw_eu_validate.c \
 	brw_extensions.c \
 	brw_fbo.c \
 	brw_fs.cpp \
 	brw_fs_bank_conflicts.cpp \
 	brw_fs_cmod_propagation.cpp \
 	brw_fs_combine_constants.cpp \
 	brw_fs_copy_propagation.cpp \
 	brw_fs_cse.cpp \
 	brw_fs_dead_code_eliminate.cpp \
 	brw_fs_generator.cpp \
 	brw_fs_live_variables.cpp \
 	brw_fs_lower_pack.cpp \
 	brw_fs_lower_regioning.cpp \
 	brw_fs_nir.cpp \
 	brw_fs_reg_allocate.cpp \
 	brw_ff_gs.c \
 	brw_formatquery.c \
 	brw_fs_register_coalesce.cpp \
 	brw_fs_saturate_propagation.cpp \
 	brw_fs_scoreboard.cpp \
 	brw_fs_sel_peephole.cpp \
 	brw_fs_validate.cpp \
 	brw_fs_visitor.cpp \
 	brw_ff_gs.c \
 	brw_formatquery.c \
 	brw_generate_mipmap.c \
 	brw_gs.c \
 	brw_gs_surface_state.c \
 	brw_interpolation_map.c \
 	brw_ir_performance.cpp \
 	brw_link.cpp \
 	brw_meta_util.c \
 	brw_mipmap_tree.c \
 	brw_misc_state.c \
 	brw_nir.c \
 	brw_nir_analyze_boolean_resolves.c \
 	brw_nir_analyze_ubo_ranges.c \
 	brw_nir_attribute_workarounds.c \
 	brw_nir_clamp_image_1d_2d_array_sizes.c \
 	brw_nir_lower_alpha_to_coverage.c \
 	brw_nir_lower_conversions.c \
 	brw_nir_lower_cs_intrinsics.c \
 	brw_nir_lower_intersection_shader.c \
 	brw_nir_lower_mem_access_bit_sizes.c \
 	brw_nir_lower_rt_intrinsics.c \
 	brw_nir_lower_scoped_barriers.c \
 	brw_nir_lower_shader_calls.c \
 	brw_nir_lower_storage_image.c \
 	brw_nir_opt_peephole_ffma.c \
 	brw_nir_rt.c \
 	brw_nir_tcs_workarounds.c \
 	brw_nir_trig_workarounds.c \
 	brw_nir_uniforms.cpp \
 	brw_object_purgeable.c \
 	brw_packed_float.c \
 	brw_performance_query.c \
 	brw_pipe_control.c \
 	brw_pixel.c \
 	brw_pixel_bitmap.c \
 	brw_pixel_copy.c \
 	brw_pixel_draw.c \
 	brw_pixel_read.c \
 	brw_predicated_break.cpp \
 	brw_primitive_restart.c \
 	brw_program.c \
 	brw_program_binary.c \
 @@ -267,26 +273,27 @@ DRI_SOURCES.i965+= \
 	gfx6_gs_visitor.cpp \
 	gfx6_multisample_state.c \
 	gfx6_queryobj.c \
 	gfx6_sampler_state.c \
 	gfx6_sol.c \
 	gfx6_urb.c \
 	gfx7_l3_state.c \
 	gfx7_sol_state.c \
 	gfx7_urb.c \
 	gfx8_depth_state.c \
 	gfx8_multisample_state.c \
 	hsw_queryobj.c \
 	hsw_sol.c \
 	intel_perf_metrics.c \
 	isl.c \
 	isl_aux_info.c \
 	isl_drm.c \
 	isl_format.c \
 	isl_format_layout.c \
 	isl_gfx4.c \
 	isl_gfx6.c \
 	isl_gfx7.c \
 	isl_gfx8.c \
 	isl_gfx9.c \
 	isl_gfx12.c \
 	isl_storage_image.c \
 	isl_tiled_memcpy.c \
 @@ -301,28 +308,29 @@ I965_INTEL_COMMON_FILES = \
 	intel_gem.c \
 	intel_l3_config.c \
 	intel_measure.c \
 	intel_sample_positions.c \
 	intel_urb_config.c \
 	intel_uuid.c
 I965_INTEL_DEV_FILES = \
 	intel_debug.c \
 	intel_dev_info.c \
 	intel_device_info.c
 I965_INTEL_PERF_FILES = \
-	intel_pps_driver.cc \
+	intel_perf.c \
-	intel_pps_perf.cc
+	intel_perf_query.c \
 	intel_perf_mdapi.c
 INTEL_GENS_BLORP=	40 45 50 60 70 75 80 90 110
 .for _gen in ${INTEL_GENS_BLORP}
 BUILDSYMLINKS+=		${X11SRCDIR.Mesa}/src/mesa/drivers/dri/i965/genX_state_upload.c ${_gen}_state_upload.c
 BUILDSYMLINKS+=		${X11SRCDIR.Mesa}/src/mesa/drivers/dri/i965/genX_blorp_exec.c ${_gen}_blorp_exec.c
 BUILDSYMLINKS+=		${X11SRCDIR.Mesa}/src/mesa/drivers/dri/i965/genX_pipe_control.c ${_gen}_pipe_control.c
 DRI_SOURCES.i965+=	${_gen}_state_upload.c ${_gen}_blorp_exec.c ${_gen}_pipe_control.c
 CPPFLAGS.${_gen}_state_upload.c+=	-DGFX_VERx10=${_gen}
 CPPFLAGS.${_gen}_blorp_exec.c+=		-DGFX_VERx10=${_gen}
 CPPFLAGS.${_gen}_pipe_control.c+=	-DGFX_VERx10=${_gen}
 .endfor
 @@ -336,26 +344,31 @@ DRI_SOURCES.i965+=	${_gen}_isl_emit_dept
 CPPFLAGS.${_gen}_isl_emit_depth_stencil.c+=	-DGFX_VERx10=${_gen} -I${X11SRCDIR.Mesa}/src/intel/isl/
 CPPFLAGS.${_gen}_isl_surface_state.c+=		-DGFX_VERx10=${_gen} -I${X11SRCDIR.Mesa}/src/intel/isl/
 .endfor
 .for _f in ${I965_INTEL_COMMON_FILES}
 BUILDSYMLINKS+=		${X11SRCDIR.Mesa}/src/intel/common/${_f} i965_${_f}
 DRI_SOURCES.i965+=	i965_${_f}
 .endfor
 .for _f in ${I965_INTEL_DEV_FILES}
 BUILDSYMLINKS+=		${X11SRCDIR.Mesa}/src/intel/dev/${_f} i965_${_f}
 DRI_SOURCES.i965+=	i965_${_f}
 .endfor
 .for _f in ${I965_INTEL_PERF_FILES}
 BUILDSYMLINKS+=			${X11SRCDIR.Mesa}/src/intel/perf/${_f} i965_${_f}
 DRI_SOURCES.i965+=		i965_${_f}
 CPPFLAGS.i965_${_f}+=	-I${X11SRCDIR.Mesa}/src/intel/perf
 .endfor
 .for _f in ${DRI_SOURCES.i965}
 CPPFLAGS.${_f} +=	-I${X11SRCDIR.Mesa}/src/mesa/drivers/dri/i965 \
 			-I${X11SRCDIR.Mesa}/src/intel \
 			-I${X11SRCDIR.Mesa}/src/intel/common \
 			-I${X11SRCDIR.Mesa}/src/intel/compiler \
 			-I${X11SRCDIR.Mesa}/src/intel/dev \
 			-I${X11SRCDIR.Mesa}/../src/intel \
 			-I${X11SRCDIR.Mesa}/src/compiler/nir \
 			-I${X11SRCDIR.Mesa}/../src/compiler/nir \
 			-I${X11SRCDIR.Mesa}/../src
 .endfor