Wed Apr 24 07:51:17 2024 UTC (16d)
Add dummy cpu feature detection for mipsn64 on NetBSD.
XXX seems there is no way to detect mips MSA (SIMD) support currently.


(martin)
diff -r1.2 -r1.3 xsrc/external/mit/MesaLib/dist/src/util/u_cpu_detect.c
cvs diff -r1.2 -r1.3 xsrc/external/mit/MesaLib/dist/src/util/u_cpu_detect.c (expand / switch to unified diff)

--- xsrc/external/mit/MesaLib/dist/src/util/u_cpu_detect.c 2023/07/16 22:01:35 1.2
+++ xsrc/external/mit/MesaLib/dist/src/util/u_cpu_detect.c 2024/04/24 07:51:17 1.3
@@ -425,45 +425,53 @@ check_os_arm_support(void) @@ -425,45 +425,53 @@ check_os_arm_support(void)
425 } 425 }
426#endif /* PIPE_OS_LINUX */ 426#endif /* PIPE_OS_LINUX */
427} 427}
428 428
429#elif defined(PIPE_ARCH_AARCH64) 429#elif defined(PIPE_ARCH_AARCH64)
430static void 430static void
431check_os_arm_support(void) 431check_os_arm_support(void)
432{ 432{
433 util_cpu_caps.has_neon = true; 433 util_cpu_caps.has_neon = true;
434} 434}
435#endif /* PIPE_ARCH_ARM || PIPE_ARCH_AARCH64 */ 435#endif /* PIPE_ARCH_ARM || PIPE_ARCH_AARCH64 */
436 436
437#if defined(PIPE_ARCH_MIPS64) 437#if defined(PIPE_ARCH_MIPS64)
 438#ifdef __NetBSD__
 439static void
 440check_os_arm_support(void)
 441{
 442 util_cpu_caps.has_msa = false; /* XXX seems there is no way to detect MSA support from userland */
 443}
 444#else
438static void 445static void
439check_os_mips64_support(void) 446check_os_mips64_support(void)
440{ 447{
441 Elf64_auxv_t aux; 448 Elf64_auxv_t aux;
442 int fd; 449 int fd;
443 450
444 fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC); 451 fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
445 if (fd >= 0) { 452 if (fd >= 0) {
446 while (read(fd, &aux, sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) { 453 while (read(fd, &aux, sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) {
447 if (aux.a_type == AT_HWCAP) { 454 if (aux.a_type == AT_HWCAP) {
448 uint64_t hwcap = aux.a_un.a_val; 455 uint64_t hwcap = aux.a_un.a_val;
449 456
450 util_cpu_caps.has_msa = (hwcap >> 1) & 1; 457 util_cpu_caps.has_msa = (hwcap >> 1) & 1;
451 break; 458 break;
452 } 459 }
453 } 460 }
454 close (fd); 461 close (fd);
455 } 462 }
456} 463}
 464#endif
457#endif /* PIPE_ARCH_MIPS64 */ 465#endif /* PIPE_ARCH_MIPS64 */
458 466
459 467
460static void 468static void
461get_cpu_topology(void) 469get_cpu_topology(void)
462{ 470{
463 /* Default. This is OK if L3 is not present or there is only one. */ 471 /* Default. This is OK if L3 is not present or there is only one. */
464 util_cpu_caps.num_L3_caches = 1; 472 util_cpu_caps.num_L3_caches = 1;
465 473
466 memset(util_cpu_caps.cpu_to_L3, 0xff, sizeof(util_cpu_caps.cpu_to_L3)); 474 memset(util_cpu_caps.cpu_to_L3, 0xff, sizeof(util_cpu_caps.cpu_to_L3));
467 475
468#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) 476#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
469 /* AMD Zen */ 477 /* AMD Zen */