Fri May 3 21:38:15 2024 UTC (29d)
s/inerttupts/interrupts/ in comments.


(andvar)
diff -r1.3 -r1.4 src/sys/arch/cobalt/stand/boot/zs.c
diff -r1.1 -r1.2 src/sys/arch/sgimips/stand/common/iris_zs.c
cvs diff -r1.3 -r1.4 src/sys/arch/cobalt/stand/boot/zs.c (expand / switch to unified diff)

--- src/sys/arch/cobalt/stand/boot/zs.c 2008/05/14 13:29:28 1.3
+++ src/sys/arch/cobalt/stand/boot/zs.c 2024/05/03 21:38:15 1.4
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: zs.c,v 1.3 2008/05/14 13:29:28 tsutsui Exp $ */ 1/* $NetBSD: zs.c,v 1.4 2024/05/03 21:38:15 andvar Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2008 Izumi Tsutsui. All rights reserved. 4 * Copyright (c) 2008 Izumi Tsutsui. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 1. Redistributions of source code must retain the above copyright 9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer. 10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright 11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the 12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution. 13 * documentation and/or other materials provided with the distribution.
14 * 14 *
@@ -77,27 +77,27 @@ zs_write_reg(void *dev, uint8_t reg, uin @@ -77,27 +77,27 @@ zs_write_reg(void *dev, uint8_t reg, uin
77 zs_write(dev, ZS_CSR, val); 77 zs_write(dev, ZS_CSR, val);
78} 78}
79 79
80static void 80static void
81zs_reset(void *dev) 81zs_reset(void *dev)
82{ 82{
83 83
84 /* clear errors */ 84 /* clear errors */
85 zs_write_reg(dev, 9, 0); 85 zs_write_reg(dev, 9, 0);
86 /* hardware reset */ 86 /* hardware reset */
87 zs_write_reg(dev, 9, ZSWR9_HARD_RESET); 87 zs_write_reg(dev, 9, ZSWR9_HARD_RESET);
88 delay(1000); 88 delay(1000);
89 89
90 /* disable all inerttupts */ 90 /* disable all interrupts */
91 zs_write_reg(dev, 1, 0); 91 zs_write_reg(dev, 1, 0);
92 92
93 /* set TX/RX misc parameters and modes */ 93 /* set TX/RX misc parameters and modes */
94 zs_write_reg(dev, 4, ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP); 94 zs_write_reg(dev, 4, ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP);
95 zs_write_reg(dev, 10, ZSWR10_NRZ); 95 zs_write_reg(dev, 10, ZSWR10_NRZ);
96 zs_write_reg(dev, 3, ZSWR3_RX_8); 96 zs_write_reg(dev, 3, ZSWR3_RX_8);
97 zs_write_reg(dev, 5, ZSWR5_TX_8 | ZSWR5_DTR | ZSWR5_RTS); 97 zs_write_reg(dev, 5, ZSWR5_TX_8 | ZSWR5_DTR | ZSWR5_RTS);
98 98
99 /* sync registers unused */ 99 /* sync registers unused */
100 zs_write_reg(dev, 6, 0); 100 zs_write_reg(dev, 6, 0);
101 zs_write_reg(dev, 7, 0); 101 zs_write_reg(dev, 7, 0);
102 102
103 /* set baud rate generator mode */ 103 /* set baud rate generator mode */
cvs diff -r1.1 -r1.2 src/sys/arch/sgimips/stand/common/iris_zs.c (expand / switch to unified diff)

--- src/sys/arch/sgimips/stand/common/iris_zs.c 2019/01/12 16:44:47 1.1
+++ src/sys/arch/sgimips/stand/common/iris_zs.c 2024/05/03 21:38:15 1.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: iris_zs.c,v 1.1 2019/01/12 16:44:47 tsutsui Exp $ */ 1/* $NetBSD: iris_zs.c,v 1.2 2024/05/03 21:38:15 andvar Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2018 Naruaki Etomi 4 * Copyright (c) 2018 Naruaki Etomi
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -103,27 +103,27 @@ zs_write_reg(void *dev, uint8_t reg, uin @@ -103,27 +103,27 @@ zs_write_reg(void *dev, uint8_t reg, uin
103 zs_write(dev, val); 103 zs_write(dev, val);
104} 104}
105 105
106static void 106static void
107zs_reset(void *dev) 107zs_reset(void *dev)
108{ 108{
109 109
110 /* clear errors */ 110 /* clear errors */
111 zs_write_reg(dev, 9, 0); 111 zs_write_reg(dev, 9, 0);
112 /* hardware reset */ 112 /* hardware reset */
113 zs_write_reg(dev, 9, ZSWR9_HARD_RESET); 113 zs_write_reg(dev, 9, ZSWR9_HARD_RESET);
114 DELAY(1000); 114 DELAY(1000);
115 115
116 /* disable all inerttupts */ 116 /* disable all interrupts */
117 zs_write_reg(dev, 1, 0); 117 zs_write_reg(dev, 1, 0);
118 118
119 /* set TX/RX misc parameters and modes */ 119 /* set TX/RX misc parameters and modes */
120 zs_write_reg(dev, 4, ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP); 120 zs_write_reg(dev, 4, ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP);
121 zs_write_reg(dev, 10, ZSWR10_NRZ); 121 zs_write_reg(dev, 10, ZSWR10_NRZ);
122 zs_write_reg(dev, 3, ZSWR3_RX_8); 122 zs_write_reg(dev, 3, ZSWR3_RX_8);
123 zs_write_reg(dev, 5, ZSWR5_TX_8 | ZSWR5_DTR | ZSWR5_RTS); 123 zs_write_reg(dev, 5, ZSWR5_TX_8 | ZSWR5_DTR | ZSWR5_RTS);
124 124
125 /* sync registers unused */ 125 /* sync registers unused */
126 zs_write_reg(dev, 6, 0); 126 zs_write_reg(dev, 6, 0);
127 zs_write_reg(dev, 7, 0); 127 zs_write_reg(dev, 7, 0);
128 128
129 /* set clock mode */ 129 /* set clock mode */