Now
MAIN commitmail json YAML
src/sys/arch/mips/conf/files.mips@1.71
/
diff
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nxr@1.71
src/sys/arch/mips/mips/locore_mips3.S@1.101 / diff / nxr@1.101
src/sys/arch/mips/mips/loongson2_subr.S@1.1 / diff / nxr@1.1
src/sys/arch/mips/mips/mips32_subr.S@1.6 / diff / nxr@1.6
src/sys/arch/mips/mips/mips32r2_subr.S@1.2 / diff / nxr@1.2
src/sys/arch/mips/mips/mips3_subr.S@1.6 / diff / nxr@1.6
src/sys/arch/mips/mips/mips64_subr.S@1.6 / diff / nxr@1.6
src/sys/arch/mips/mips/mips64r2_subr.S@1.2 / diff / nxr@1.2
src/sys/arch/mips/mips/mipsX_subr.S@1.51 / diff / nxr@1.51
src/sys/arch/mips/mips/mips_machdep.c@1.245 / diff / nxr@1.245
src/sys/arch/mips/mips/locore_mips3.S@1.101 / diff / nxr@1.101
src/sys/arch/mips/mips/loongson2_subr.S@1.1 / diff / nxr@1.1
src/sys/arch/mips/mips/mips32_subr.S@1.6 / diff / nxr@1.6
src/sys/arch/mips/mips/mips32r2_subr.S@1.2 / diff / nxr@1.2
src/sys/arch/mips/mips/mips3_subr.S@1.6 / diff / nxr@1.6
src/sys/arch/mips/mips/mips64_subr.S@1.6 / diff / nxr@1.6
src/sys/arch/mips/mips/mips64r2_subr.S@1.2 / diff / nxr@1.2
src/sys/arch/mips/mips/mipsX_subr.S@1.51 / diff / nxr@1.51
src/sys/arch/mips/mips/mips_machdep.c@1.245 / diff / nxr@1.245
Add support for a loongson2_subr.S. This is needed since that chip needs
special handling to manually flush the ITLB on TLB updates.
special handling to manually flush the ITLB on TLB updates.