Sat Oct 4 17:20:06 2008 UTC ()
in cpu_hatch(), set PIR when the current value is not what we need
rather than only when it's zero.


(chs)
diff -r1.48 -r1.49 src/sys/arch/powerpc/oea/cpu_subr.c
cvs diff -r1.48 -r1.49 src/sys/arch/powerpc/oea/cpu_subr.c (expand / switch to unified diff)

--- src/sys/arch/powerpc/oea/cpu_subr.c 2008/09/23 13:58:59 1.48
+++ src/sys/arch/powerpc/oea/cpu_subr.c 2008/10/04 17:20:06 1.49
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpu_subr.c,v 1.48 2008/09/23 13:58:59 macallan Exp $ */ 1/* $NetBSD: cpu_subr.c,v 1.49 2008/10/04 17:20:06 chs Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2001 Matt Thomas. 4 * Copyright (c) 2001 Matt Thomas.
5 * Copyright (c) 2001 Tsubai Masanari. 5 * Copyright (c) 2001 Tsubai Masanari.
6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
7 * All rights reserved. 7 * All rights reserved.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -24,27 +24,27 @@ @@ -24,27 +24,27 @@
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */ 34 */
35 35
36#include <sys/cdefs.h> 36#include <sys/cdefs.h>
37__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.48 2008/09/23 13:58:59 macallan Exp $"); 37__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.49 2008/10/04 17:20:06 chs Exp $");
38 38
39#include "opt_ppcparam.h" 39#include "opt_ppcparam.h"
40#include "opt_multiprocessor.h" 40#include "opt_multiprocessor.h"
41#include "opt_altivec.h" 41#include "opt_altivec.h"
42#include "sysmon_envsys.h" 42#include "sysmon_envsys.h"
43 43
44#include <sys/param.h> 44#include <sys/param.h>
45#include <sys/systm.h> 45#include <sys/systm.h>
46#include <sys/device.h> 46#include <sys/device.h>
47#include <sys/types.h> 47#include <sys/types.h>
48#include <sys/lwp.h> 48#include <sys/lwp.h>
49#include <sys/user.h> 49#include <sys/user.h>
50#include <sys/malloc.h> 50#include <sys/malloc.h>
@@ -1174,33 +1174,32 @@ extern void tlbia(void); @@ -1174,33 +1174,32 @@ extern void tlbia(void);
1174register_t 1174register_t
1175cpu_hatch(void) 1175cpu_hatch(void)
1176{ 1176{
1177 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1177 volatile struct cpu_hatch_data *h = cpu_hatch_data;
1178 struct cpu_info * const ci = h->ci; 1178 struct cpu_info * const ci = h->ci;
1179 u_int msr; 1179 u_int msr;
1180 int i; 1180 int i;
1181 1181
1182 /* Initialize timebase. */ 1182 /* Initialize timebase. */
1183 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1183 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0));
1184 1184
1185 /* 1185 /*
1186 * Set PIR (Processor Identification Register). i.e. whoami 1186 * Set PIR (Processor Identification Register). i.e. whoami
1187 * Note that PIR is read-only on some CPU's. Try to work around 1187 * Note that PIR is read-only on some CPU versions, so we write to it
1188 * that as best as possible. Assume that if it is 0, it is meant 1188 * only if it has a different value than we need.
1189 * to be setup by us. 
1190 */ 1189 */
1191 1190
1192 msr = mfspr(SPR_PIR); 1191 msr = mfspr(SPR_PIR);
1193 if (msr == 0) 1192 if (msr != h->pir)
1194 mtspr(SPR_PIR, h->pir); 1193 mtspr(SPR_PIR, h->pir);
1195  1194
1196 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1195 __asm volatile ("mtsprg 0,%0" :: "r"(ci));
1197 cpu_spinstart_ack = 0; 1196 cpu_spinstart_ack = 0;
1198 1197
1199 /* Initialize MMU. */ 1198 /* Initialize MMU. */
1200 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1199 __asm ("mtibatu 0,%0" :: "r"(h->batu[0]));
1201 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1200 __asm ("mtibatl 0,%0" :: "r"(h->batl[0]));
1202 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1201 __asm ("mtibatu 1,%0" :: "r"(h->batu[1]));
1203 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1202 __asm ("mtibatl 1,%0" :: "r"(h->batl[1]));
1204 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1203 __asm ("mtibatu 2,%0" :: "r"(h->batu[2]));
1205 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1204 __asm ("mtibatl 2,%0" :: "r"(h->batl[2]));
1206 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1205 __asm ("mtibatu 3,%0" :: "r"(h->batu[3]));