 @@ -1,14 +1,14 @@
-/*	$NetBSD: cache.c,v 1.7 2011/06/06 01:16:48 mrg Exp $	*/
+/*	$NetBSD: cache.c,v 1.8 2011/06/06 02:49:39 mrg Exp $	*/
 /*
  * Copyright (c) 2011 Matthew R. Green
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -25,81 +25,82 @@
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*
  * Handle picking the right types of the different cache call.
+ *
  * This module could take on a larger role.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.7 2011/06/06 01:16:48 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.8 2011/06/06 02:49:39 mrg Exp $");
 #include "opt_multiprocessor.h"
 #include <sys/param.h>
 #include <sys/reboot.h>
 #include <machine/cpu.h>
 #include <sparc64/sparc64/cache.h>
 static void
 cache_nop(void)
+{
+}
 static void
 blast_dcache_real(void)
+{
 	sp_blast_dcache(dcache_size, dcache_line_size);
+}
 #if 0
 static void
 sp_dcache_flush_page_cpuset(paddr_t pa, sparc64_cpuset_t cs)
+{
 	dcache_flush_page(pa);
+}
 void    (*dcache_flush_page)(paddr_t) =	dcache_flush_page_us;
 void	(*dcache_flush_page_cpuset)(paddr_t, sparc64_cpuset_t) =
 					sp_dcache_flush_page_cpuset;
 #endif
 void	(*blast_dcache)(void) =		blast_dcache_real;
 void	(*blast_icache)(void) =		blast_icache_us;
 #ifdef MULTIPROCESSOR
 void    (*sp_dcache_flush_page)(paddr_t) = dcache_flush_page_us;
 #endif
 void
 cache_setup_funcs(void)
+{
 	if (CPU_ISSUN4US || CPU_ISSUN4V) {
 #if 0
 		dcache_flush_page = (void (*)(paddr_t)) cache_nop;
 #ifdef MULTIPROCESSOR
 		/* XXXMRG shouldn't be necessary -- only caller is nop'ed out */
 		sp_dcache_flush_page = (void (*)(paddr_t)) cache_nop;
 #endif
 		blast_dcache = cache_nop;
 		blast_icache = cache_nop;
 	} else {
 		if (CPU_IS_USIII_UP()) {
 #if 0
 			dcache_flush_page = dcache_flush_page_usiii;
 #ifdef MULTIPROCESSOR
 			sp_dcache_flush_page = dcache_flush_page_usiii;
 #endif
 			blast_icache = blast_icache_usiii;
 printf("set usIII dcache/icache funcs\n");
+		}
 #ifdef MULTIPROCESSOR
 		if (sparc_ncpus > 1 && (boothowto & RB_MD1) == 0) {
 printf("set MP dcache funcs\n");
 #if 0
 			dcache_flush_page = smp_dcache_flush_page_allcpu;
 			dcache_flush_page_cpuset = smp_dcache_flush_page_cpuset;
 #endif
 			blast_dcache = smp_blast_dcache;
+		}
 #endif
+	}
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cache.h,v 1.21 2011/06/06 01:16:48 mrg Exp $ */
+/*	$NetBSD: cache.h,v 1.22 2011/06/06 02:49:39 mrg Exp $ */
 /*
  * Copyright (c) 2011 Matthew R. Green
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -92,37 +92,26 @@ extern	int	icache_size;
 /* The following are for I$ and D$ flushes and are in locore.s */
 void 	dcache_flush_page_us(paddr_t);	/* flush page from D$ */
 void 	dcache_flush_page_usiii(paddr_t); /* flush page from D$ */
 void 	sp_blast_dcache(int, int);	/* Clear entire D$ */
 void 	blast_icache_us(void);		/* Clear entire I$ */
 void 	blast_icache_usiii(void);	/* Clear entire I$ */
 /* The following flush a range from the D$ and I$ but not E$. */
 void	cache_flush_phys_us(paddr_t, psize_t, int);
 void	cache_flush_phys_usiii(paddr_t, psize_t, int);
 static __inline__ void
 dcache_flush_page(paddr_t pa)
 	if (CPU_ISSUN4US || CPU_ISSUN4V)
 		return;
 	if (CPU_IS_USIII_UP())
 		dcache_flush_page_usiii(pa);
 	else
 		dcache_flush_page_us(pa);
 static __inline__ void
 cache_flush_phys(paddr_t pa, psize_t size, int ecache)
+{
 	if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
 		cache_flush_phys_usiii(pa, size, ecache);
 	else
 		cache_flush_phys_us(pa, size, ecache);
+}
 /* SPARC64 specific */
 /* Assembly routines to flush TLB mappings */
 void sp_tlb_flush_pte_us(vaddr_t, int);
 void sp_tlb_flush_pte_usiii(vaddr_t, int);
 void sp_tlb_flush_all_us(void);
 @@ -136,35 +125,35 @@ sp_tlb_flush_pte(vaddr_t va, int ctx)
 	else
 		sp_tlb_flush_pte_us(va, ctx);
+}
 static __inline__ void
 sp_tlb_flush_all(void)
+{
 	if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
 		sp_tlb_flush_all_usiii();
 	else
 		sp_tlb_flush_all_us();
+}
 #if 0
 extern	void	(*dcache_flush_page)(paddr_t);
 extern	void	(*dcache_flush_page_cpuset)(paddr_t, sparc64_cpuset_t);
 #endif
 extern	void	(*blast_dcache)(void);
 extern	void	(*blast_icache)(void);
 void cache_setup_funcs(void);
 #ifdef MULTIPROCESSOR
 extern	void	(*sp_dcache_flush_page)(paddr_t);
 void smp_tlb_flush_pte(vaddr_t, struct pmap *);
 void smp_dcache_flush_page_cpuset(paddr_t pa, sparc64_cpuset_t);
 void smp_dcache_flush_page_allcpu(paddr_t pa);
 void smp_blast_dcache(void);
-#define	tlb_flush_pte(va,pm	)	smp_tlb_flush_pte(va, pm)
+#define	tlb_flush_pte(va,pm)		smp_tlb_flush_pte(va, pm)
 #define	dcache_flush_page_all(pa)	smp_dcache_flush_page_cpuset(pa, cpus_active)
 #define	dcache_flush_page_cpuset(pa,cs)	smp_dcache_flush_page_cpuset(pa, cs)
 #else
 #define	tlb_flush_pte(va,pm)		sp_tlb_flush_pte(va, (pm)->pm_ctx[0])
 #define	dcache_flush_page_all(pa)	dcache_flush_page(pa)
 #define	dcache_flush_page_cpuset(pa,cs)	dcache_flush_page(pa)
 #endif

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ipifuncs.c,v 1.41 2011/06/06 01:16:48 mrg Exp $ */
+/*	$NetBSD: ipifuncs.c,v 1.42 2011/06/06 02:49:39 mrg Exp $ */
 /*-
  * Copyright (c) 2004 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.41 2011/06/06 01:16:48 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.42 2011/06/06 02:49:39 mrg Exp $");
 #include "opt_ddb.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/malloc.h>
 #include <sys/xcall.h>
 #include <machine/db_machdep.h>
 #include <machine/cpu.h>
 #include <machine/cpu_counter.h>
 #include <machine/ctlreg.h>
 @@ -412,57 +412,49 @@ smp_tlb_flush_pte(vaddr_t va, struct pma
 			sparc64_send_ipi(ci->ci_cpuid, func, va, ctx);
+		}
+	}
+}
 /*
  * Make sure this page is flushed from all/some CPUs.
  */
 void
 smp_dcache_flush_page_cpuset(paddr_t pa, sparc64_cpuset_t activecpus)
+{
 	ipifunc_t func;
 	if (CPU_ISSUN4US || CPU_ISSUN4V)
 		return;
 	if (CPU_IS_USIII_UP())
 		func = sparc64_ipi_dcache_flush_page_usiii;
 	else
 		func = sparc64_ipi_dcache_flush_page_us;
 	sparc64_multicast_ipi(activecpus, func, pa, dcache_line_size);
-	dcache_flush_page(pa);
+	sp_dcache_flush_page(pa);
+}
 #if 0
 void
 smp_dcache_flush_page_allcpu(paddr_t pa)
+{
 	smp_dcache_flush_page_cpuset(pa, cpus_active);
+}
 #endif
 /*
  * Flush the D$ on all CPUs.
  */
 void
 smp_blast_dcache(void)
+{
 	if (CPU_ISSUN4US || CPU_ISSUN4V)
 		return;
 	sparc64_multicast_ipi(cpus_active, sparc64_ipi_blast_dcache,
 			      dcache_size, dcache_line_size);
 	sp_blast_dcache(dcache_size, dcache_line_size);
+}
 /*
  * Print an error message.
  */
 void
 sparc64_ipi_error(const char *s, sparc64_cpuset_t cpus_succeeded,
 	sparc64_cpuset_t cpus_expected)
+{
 	int cpuid;