@@ -1,4 +1,4 @@
-#	$NetBSD: files.gdium,v 1.1 2009/08/06 00:50:25 matt Exp $
+#	$NetBSD: files.gdium,v 1.2 2011/06/08 17:47:48 bouyer Exp $
 
 file	arch/evbmips/gdium/gdium_bus_io.c
 file	arch/evbmips/gdium/gdium_bus_mem.c
@@ -15,7 +15,6 @@
 
 file	arch/mips/mips/mips3_clock.c
 file	arch/mips/mips/mips3_clockintr.c
-file	arch/mips/mips/softintr.c
 
 # The autoconfiguration root.
 device	mainbus { [addr = -1] }

@@ -1,4 +1,4 @@
-/*	$NetBSD: gdium_dma.c,v 1.2 2009/08/06 16:37:01 matt Exp $	*/
+/*	$NetBSD: gdium_dma.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gdium_dma.c,v 1.2 2009/08/06 16:37:01 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gdium_dma.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $");
 
 #include <sys/param.h>
 
@@ -55,20 +55,9 @@
 	t = &gc->gc_pci_dmat;
 	t->_cookie = gc;
 	t->_wbase = GDIUM_DMA_PCI_PCIBASE;
-	t->_physbase = GDIUM_DMA_PCI_PHYSBASE;
-	t->_wsize = GDIUM_DMA_PCI_SIZE;
-	t->_dmamap_create = _bus_dmamap_create;
-	t->_dmamap_destroy = _bus_dmamap_destroy;
-	t->_dmamap_load = _bus_dmamap_load;
-	t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
-	t->_dmamap_load_uio = _bus_dmamap_load_uio;
-	t->_dmamap_load_raw = _bus_dmamap_load_raw;
-	t->_dmamap_unload = _bus_dmamap_unload;
-	t->_dmamap_sync = _bus_dmamap_sync;
-
-	t->_dmamem_alloc = _bus_dmamem_alloc;
-	t->_dmamem_free = _bus_dmamem_free;
-	t->_dmamem_map = _bus_dmamem_map;
-	t->_dmamem_unmap = _bus_dmamem_unmap;
-	t->_dmamem_mmap = _bus_dmamem_mmap;
+	t->_bounce_alloc_lo = GDIUM_DMA_PCI_PHYSBASE;
+	t->_bounce_alloc_hi = GDIUM_DMA_PCI_PHYSBASE + GDIUM_DMA_PCI_SIZE;
+	t->_dmamap_ops = mips_bus_dmamap_ops;
+	t->_dmamem_ops = mips_bus_dmamem_ops;
+	t->_dmatag_ops = mips_bus_dmatag_ops;
 }

@@ -1,4 +1,4 @@
-/*	$NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $	*/
+/*	$NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -37,8 +37,11 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $");
 
+#define __INTR_PRIVATE
+
+
 #include "opt_ddb.h"
 
 #include <sys/param.h>
@@ -129,7 +132,7 @@
 };
 
 struct gdium_cpuintr gdium_cpuintrs[NINTRS];
-const char *gdium_cpuintrnames[NINTRS] = {
+const char * const gdium_cpuintrnames[NINTRS] = {
 	"int 0 (pci)",
 	"int 1 (errors)",
 };
@@ -138,20 +141,11 @@
  * This is a mask of bits to clear in the SR when we go to a
  * given hardware interrupt priority level.
  */
-const uint32_t ipl_sr_bits[_IPL_N] = {
-	[IPL_NONE] = 0,
-	[IPL_SOFTCLOCK] =
-	    MIPS_SOFT_INT_MASK_0,
-#if IPL_SOFTCLOCK != IPL_SOFTBIO
-	[IPL_SOFTBIO] =
-	    MIPS_SOFT_INT_MASK_0,
-#endif
-	[IPL_SOFTNET] =
-	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
-#if IPL_SOFTNET != IPL_SOFTSERIAL
-	[IPL_SOFTSERIAL] =
-	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
-#endif
+static const struct ipl_sr_map gdium_ipl_sr_map = {
+    .sr_bits = {
+	[IPL_NONE] =		0,
+	[IPL_SOFTCLOCK] =	MIPS_SOFT_INT_MASK_0,
+	[IPL_SOFTNET] =		MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
 	[IPL_VM] =
 	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
 	    MIPS_INT_MASK_0 |
@@ -167,25 +161,12 @@
 	    MIPS_INT_MASK_3 |
 	    MIPS_INT_MASK_4 |
 	    MIPS_INT_MASK_5,
+	[IPL_DDB] =		MIPS_INT_MASK,
+	[IPL_HIGH] =            MIPS_INT_MASK,
+    },
 };
 
-/*
- * This is a mask of bits to clear in the SR when we go to a
- * given software interrupt priority level.
- * Hardware ipls are port/board specific.
- */
-const uint32_t mips_ipl_si_to_sr[] = {
-	[IPL_SOFTCLOCK-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
-#if IPL_SOFTCLOCK != IPL_SOFTBIO
-	[IPL_SOFTBIO-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
-#endif
-	[IPL_SOFTNET-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
-#if IPL_SOFTNET != IPL_SOFTSERIAL
-	[IPL_SOFTSERIAL-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
-#endif
-};
-
-int	gdium_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
+int	gdium_pci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
 const char *gdium_pci_intr_string(void *, pci_intr_handle_t);
 const struct evcnt *gdium_pci_intr_evcnt(void *, pci_intr_handle_t);
 void	*gdium_pci_intr_establish(void *, pci_intr_handle_t, int,
@@ -196,12 +177,14 @@
 void
 evbmips_intr_init(void)
 {
-	struct gdium_config *gc = &gdium_configuration;
+	struct gdium_config * const gc = &gdium_configuration;
 	struct bonito_config *bc = &gc->gc_bonito;
 	const struct gdium_irqmap *irqmap;
 	uint32_t intbit;
-	int i;
+	size_t i;
 
+	ipl_sr_map = gdium_ipl_sr_map;
+
 	for (i = 0; i < NINTRS; i++) {
 		LIST_INIT(&gdium_cpuintrs[i].cintr_list);
 		evcnt_attach_dynamic(&gdium_cpuintrs[i].cintr_count,
@@ -316,8 +299,7 @@
 }
 
 void
-evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc,
-	uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
 {
 	const struct gdium_irqmap *irqmap;
 	struct evbmips_intrhand *ih;
@@ -341,11 +323,7 @@
 				(*ih->ih_func)(ih->ih_arg);
 			}
 		}
-		cause &= ~(MIPS_INT_MASK_0 << level);
 	}
-
-	/* Re-enable anything that we have processed. */
-	_splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
 }
 
 /*****************************************************************************
@@ -353,7 +331,7 @@
  *****************************************************************************/
 
 int
-gdium_pci_intr_map(struct pci_attach_args *pa,
+gdium_pci_intr_map(const struct pci_attach_args *pa,
     pci_intr_handle_t *ihp)
 {
 	static const int8_t pciirqmap[5/*device*/] = {

@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $	*/
+/*	$NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $	*/
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -74,7 +74,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $");
 
 #include "opt_ddb.h"
 #include "opt_execfmt.h"
@@ -106,6 +106,8 @@
 #include <machine/cpu.h>
 #include <machine/psl.h>
 
+#include <mips/locore.h>
+
 #include <mips/bonito/bonitoreg.h>
 #include <evbmips/gdium/gdiumvar.h>
 
@@ -126,9 +128,6 @@
 /* For sysctl_hw. */
 extern char cpu_model[];
 
-/* Our exported CPU info; we can have only one. */  
-struct cpu_info cpu_info_store;
-
 /* Maps for VM objects. */
 struct vm_map *phys_map = NULL;
 
@@ -200,9 +199,6 @@
 {
 	struct gdium_config *gc = &gdium_configuration;
 	void *kernend;
-	u_long first, last;
-	struct pcb *pcb0;
-	vaddr_t v;
 #ifdef NOTYET
 	char *cp;
 	int howto;
@@ -225,7 +221,7 @@
 	 * first printf() after that is called).
 	 * Also clears the I+D caches.
 	 */
-	mips_vector_init(NULL, bool);
+	mips_vector_init(NULL, false);
 
 	/* set the VM page size */
 	uvm_setpagesize();
@@ -261,7 +257,7 @@
 		}
 	}
 	
-	if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+	if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
 		curcpu()->ci_cpu_freq /= 2;
 
 	/* Compute the number of ticks for hz. */
@@ -275,7 +271,7 @@
 	 * Get correct cpu frequency if the CPU runs at twice the
 	 * external/cp0-count frequency.
 	 */
-	if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+	if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
 		curcpu()->ci_cpu_freq *= 2;
 
 #ifdef DEBUG
@@ -330,10 +326,8 @@
 	/*
 	 * Load the rest of the available pages into the VM system.
 	 */
-	first = round_page(MIPS_KSEG0_TO_PHYS(kernend));
-	last = mem_clusters[0].start + mem_clusters[0].size;
-	uvm_page_physload(atop(first), atop(last), atop(first), atop(last),
-		VM_FREELIST_DEFAULT);
+	mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
+	    mem_clusters, mem_cluster_cnt, NULL, 0);
 
 	/*
 	 * Initialize error message buffer (at end of core).
@@ -345,14 +339,8 @@
 	/*
 	 * Allocate uarea page for lwp0 and set it.
 	 */
-	v = uvm_pageboot_alloc(USPACE); 
-	uvm_lwp_setuarea(&lwp0, v);
+	mips_init_lwp0_uarea();
 
-	pcb0 = lwp_getpcb(&lwp0);
-	pcb0->pcb_context[11] = MIPS_INT_MASK | MIPS_SR_INT_IE; /* SR */
-
-	lwp0.l_md.md_regs = (struct frame *)(v + USPACE) - 1;
-
 	/*
 	 * Initialize debuggers, and break into them, if appropriate.
 	 */
@@ -378,15 +366,10 @@
 void
 cpu_startup(void)
 {
-	vaddr_t minaddr, maxaddr;
-	char pbuf[9];
-
 	/*
-	 * Good {morning,afternoon,evening,night}.
+	 *  Do the common startup items.
 	 */
-	printf("%s%s", copyright, version);
-	format_bytes(pbuf, sizeof(pbuf), ctob(physmem));
-	printf("total memory = %s\n", pbuf);
+	cpu_startup_common();
 
 	/*
 	 * Virtual memory is bootstrapped -- notify the bus spaces
@@ -394,21 +377,6 @@
 	 */
 	gdium_configuration.gc_mallocsafe = 1;
 
-	minaddr = 0;
-	/*
-	 * Allocate a submap for physio.
-	 */
-	phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
-				    VM_PHYS_SIZE, 0, FALSE, NULL);
-
-	/*
-	 * (No need to allocate an mbuf cluster submap.  Mbuf clusters
-	 * are allocated via the pool allocator, and we use KSEG to
-	 * map those pages.)
-	 */
-
-	format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free));
-	printf("avail memory = %s\n", pbuf);
 }
 
 int	waittime = -1;
@@ -418,8 +386,7 @@
 {
 
 	/* Take a snapshot before clobbering any registers. */
-	if (curproc)
-		savectx(curpcb);
+	savectx(curpcb);
 
 	if (cold) {
 		howto |= RB_HALT;

@@ -1,4 +1,4 @@
-/*	$NetBSD: cache.c,v 1.46 2011/03/15 07:39:22 matt Exp $	*/
+/*	$NetBSD: cache.c,v 1.47 2011/06/08 17:47:48 bouyer Exp $	*/
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.46 2011/03/15 07:39:22 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.47 2011/06/08 17:47:48 bouyer Exp $");
 
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
@@ -586,40 +586,40 @@
 #endif /* ENABLE_MIPS4_CACHE_R10K */
 #ifdef MIPS3_LOONGSON2
 	case MIPS_LOONGSON2:
-		mips_picache_ways = 4;
-		mips_pdcache_ways = 4;
+		mci->mci_picache_ways = 4;
+		mci->mci_pdcache_ways = 4;
 
 		mips3_get_cache_config(csizebase);
 
-		mips_sdcache_line_size = 32;	/* don't trust config reg */
+		mci->mci_sdcache_line_size = 32;	/* don't trust config reg */
 
-		if (mips_picache_size / mips_picache_ways > PAGE_SIZE ||
-		    mips_pdcache_size / mips_pdcache_ways > PAGE_SIZE)
-			mips_cache_virtual_alias = 1;
+		if (mci->mci_picache_size / mci->mci_picache_ways > PAGE_SIZE ||
+		    mci->mci_pdcache_size / mci->mci_pdcache_ways > PAGE_SIZE)
+			mci->mci_cache_virtual_alias = 1;
 
-		mips_cache_ops.mco_icache_sync_all =
+		mco->mco_icache_sync_all =
 		    ls2_icache_sync_all;
-		mips_cache_ops.mco_icache_sync_range =
+		mco->mco_icache_sync_range =
 		    ls2_icache_sync_range;
-		mips_cache_ops.mco_icache_sync_range_index =
+		mco->mco_icache_sync_range_index =
 		    ls2_icache_sync_range_index;
 
-		mips_cache_ops.mco_pdcache_wbinv_all =
+		mco->mco_pdcache_wbinv_all =
 		    ls2_pdcache_wbinv_all;
-		mips_cache_ops.mco_pdcache_wbinv_range =
+		mco->mco_pdcache_wbinv_range =
 		    ls2_pdcache_wbinv_range;
-		mips_cache_ops.mco_pdcache_wbinv_range_index =
+		mco->mco_pdcache_wbinv_range_index =
 		    ls2_pdcache_wbinv_range_index;
-		mips_cache_ops.mco_pdcache_inv_range =
+		mco->mco_pdcache_inv_range =
 		    ls2_pdcache_inv_range;
-		mips_cache_ops.mco_pdcache_wb_range =
+		mco->mco_pdcache_wb_range =
 		    ls2_pdcache_wb_range;
 
 		/*
 		 * For current version chips, [the] operating system is
 		 * obliged to eliminate the potential for virtual aliasing.
 		 */
-		uvmexp.ncolors = mips_pdcache_ways;
+		uvmexp.ncolors = mci->mci_pdcache_ways;
 		break;
 #endif
 #endif /* MIPS3 || MIPS4 */
@@ -768,19 +768,19 @@
 #endif /* ENABLE_MIPS4_CACHE_R10K */
 #ifdef MIPS3_LOONGSON2
 	case MIPS_LOONGSON2:
-		mips_sdcache_ways = 4;
-		mips_sdcache_size = 512*1024;
-		mips_scache_unified = 1;
+		mci->mci_sdcache_ways = 4;
+		mci->mci_sdcache_size = 512*1024;
+		mci->mci_scache_unified = 1;
 
-		mips_cache_ops.mco_sdcache_wbinv_all =
+		mco->mco_sdcache_wbinv_all =
 		    ls2_sdcache_wbinv_all;
-		mips_cache_ops.mco_sdcache_wbinv_range =
+		mco->mco_sdcache_wbinv_range =
 		    ls2_sdcache_wbinv_range;
-		mips_cache_ops.mco_sdcache_wbinv_range_index =
+		mco->mco_sdcache_wbinv_range_index =
 		    ls2_sdcache_wbinv_range_index;
-		mips_cache_ops.mco_sdcache_inv_range =
+		mco->mco_sdcache_inv_range =
 		    ls2_sdcache_inv_range;
-		mips_cache_ops.mco_sdcache_wb_range =
+		mco->mco_sdcache_wb_range =
 		    ls2_sdcache_wb_range;
 
 		/*

@@ -1,4 +1,4 @@
-/*	$NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $	*/
+/*	$NetBSD: cache_ls2.c,v 1.4 2011/06/08 17:47:48 bouyer Exp $	*/
 
 /*-
  * Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.4 2011/06/08 17:47:48 bouyer Exp $");
 
 #include <sys/param.h>
 
@@ -55,11 +55,12 @@
 void
 ls2_icache_sync_range(vaddr_t va, vsize_t size)
 {
+	struct mips_cache_info * const mci = &mips_cache_info;
 	const vaddr_t eva = round_line(va + size);
 
 	va = trunc_line(va);
 
-	if (va + mips_picache_size <= eva) {
+	if (va + mci->mci_picache_size <= eva) {
 		ls2_icache_sync_all();
 		return;
 	}
@@ -81,6 +82,7 @@
 ls2_icache_sync_range_index(vaddr_t va, vsize_t size)
 {
 	vaddr_t eva;
+	struct mips_cache_info * const mci = &mips_cache_info;
 
 	/*
 	 * Since we're doing Index ops, we expect to not be able
@@ -89,13 +91,13 @@
 	 * address out of them.
 	 */
 
-	va = MIPS_PHYS_TO_KSEG0(va & mips_picache_way_mask);
+	va = MIPS_PHYS_TO_KSEG0(va & mci->mci_picache_way_mask);
 	eva = round_line(va + size);
 	va = trunc_line(va);
 
-	if (va + mips_picache_way_size < eva) {
+	if (va + mci->mci_picache_way_size < eva) {
 		va = MIPS_PHYS_TO_KSEG0(0);
-		eva = mips_picache_way_size;
+		eva = mci->mci_picache_way_size;
 	}
 
 	for (; va + 8 * 32 <= eva; va += 8 * 32) {
@@ -114,7 +116,8 @@
 void
 ls2_icache_sync_all(void)
 {
-	ls2_icache_sync_range_index(0, mips_picache_way_size);
+	struct mips_cache_info * const mci = &mips_cache_info;
+	ls2_icache_sync_range_index(0, mci->mci_picache_way_size);
 }
 
 void
@@ -166,6 +169,7 @@
 ls2_pdcache_wbinv_range_index(vaddr_t va, vsize_t size)
 {
 	vaddr_t eva;
+	struct mips_cache_info * const mci = &mips_cache_info;
 
 	/*
 	 * Since we're doing Index ops, we expect to not be able
@@ -173,14 +177,14 @@
 	 * bits that determine the cache index, and make a KSEG0
 	 * address out of them.
 	 */
-	va = MIPS_PHYS_TO_KSEG0(va & mips_pdcache_way_mask);
+	va = MIPS_PHYS_TO_KSEG0(va & mci->mci_pdcache_way_mask);
 
 	eva = round_line(va + size);
 	va = trunc_line(va);
 
-	if (va + mips_pdcache_way_size > eva) {
+	if (va + mci->mci_pdcache_way_size > eva) {
 		va = MIPS_PHYS_TO_KSEG0(0);
-		eva = mips_pdcache_way_size;
+		eva = mci->mci_pdcache_way_size;
 	}
 
 	for (; va + 8 * 32 <= eva; va += 8 * 32) {
@@ -197,7 +201,8 @@
 void
 ls2_pdcache_wbinv_all(void)
 {
-	ls2_pdcache_wbinv_range_index(0, mips_pdcache_way_size);
+	struct mips_cache_info * const mci = &mips_cache_info;
+	ls2_pdcache_wbinv_range_index(0, mci->mci_pdcache_way_size);
 }
 
 /*
@@ -262,6 +267,7 @@
 ls2_sdcache_wbinv_range_index(vaddr_t va, vsize_t size)
 {
 	vaddr_t eva;
+	struct mips_cache_info * const mci = &mips_cache_info;
 
 	/*
 	 * Since we're doing Index ops, we expect to not be able
@@ -269,14 +275,14 @@
 	 * bits that determine the cache index, and make a KSEG0
 	 * address out of them.
 	 */
-	va = MIPS_PHYS_TO_KSEG0(va & mips_sdcache_way_mask);
+	va = MIPS_PHYS_TO_KSEG0(va & mci->mci_sdcache_way_mask);
 
 	eva = round_line(va + size);
 	va = trunc_line(va);
 
-	if (va + mips_sdcache_way_size > eva) {
+	if (va + mci->mci_sdcache_way_size > eva) {
 		va = MIPS_PHYS_TO_KSEG0(0);
-		eva = va + mips_sdcache_way_size;
+		eva = va + mci->mci_sdcache_way_size;
 	}
 
 	for (; va + 8 * 32 <= eva; va += 8 * 32) {
@@ -295,5 +301,6 @@
 void
 ls2_sdcache_wbinv_all(void)
 {
-	ls2_sdcache_wbinv_range_index(0, mips_sdcache_way_size);
+	struct mips_cache_info * const mci = &mips_cache_info;
+	ls2_sdcache_wbinv_range_index(0, mci->mci_sdcache_way_size);
 }