 @@ -1,14 +1,14 @@
-/*	$NetBSD: gdium_dma.c,v 1.2 2009/08/06 16:37:01 matt Exp $	*/
+/*	$NetBSD: gdium_dma.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $	*/
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -24,51 +24,40 @@
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Platform-specific DMA support for the Gdium Liberty 1000.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gdium_dma.c,v 1.2 2009/08/06 16:37:01 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gdium_dma.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $");
 #include <sys/param.h>
 #define	_MIPS_BUS_DMA_PRIVATE
 #include <machine/bus.h>
 #include <evbmips/gdium/gdiumreg.h>
 #include <evbmips/gdium/gdiumvar.h>
 void
 gdium_dma_init(struct gdium_config *gc)
+{
 	bus_dma_tag_t t;
 	/*
 	 * Initialize the DMA tag used for PCI DMA.
 	 */
 	t = &gc->gc_pci_dmat;
 	t->_cookie = gc;
 	t->_wbase = GDIUM_DMA_PCI_PCIBASE;
-	t->_physbase = GDIUM_DMA_PCI_PHYSBASE;
+	t->_bounce_alloc_lo = GDIUM_DMA_PCI_PHYSBASE;
-	t->_wsize = GDIUM_DMA_PCI_SIZE;
+	t->_bounce_alloc_hi = GDIUM_DMA_PCI_PHYSBASE + GDIUM_DMA_PCI_SIZE;
-	t->_dmamap_create = _bus_dmamap_create;
+	t->_dmamap_ops = mips_bus_dmamap_ops;
-	t->_dmamap_destroy = _bus_dmamap_destroy;
+	t->_dmamem_ops = mips_bus_dmamem_ops;
-	t->_dmamap_load = _bus_dmamap_load;
+	t->_dmatag_ops = mips_bus_dmatag_ops;
 	t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
 	t->_dmamap_load_uio = _bus_dmamap_load_uio;
 	t->_dmamap_load_raw = _bus_dmamap_load_raw;
 	t->_dmamap_unload = _bus_dmamap_unload;
 	t->_dmamap_sync = _bus_dmamap_sync;
 	t->_dmamem_alloc = _bus_dmamem_alloc;
 	t->_dmamem_free = _bus_dmamem_free;
 	t->_dmamem_map = _bus_dmamem_map;
 	t->_dmamem_unmap = _bus_dmamem_unmap;
 	t->_dmamem_mmap = _bus_dmamem_mmap;
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $	*/
+/*	$NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $	*/
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -27,27 +27,30 @@
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Platform-specific interrupt support for the Algorithmics P-6032.
+ *
  * The Algorithmics P-6032's interrupts are wired to GPIO pins
  * on the BONITO system controller.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $");
 #define __INTR_PRIVATE
 #include "opt_ddb.h"
 #include <sys/param.h>
 #include <sys/queue.h>
 #include <sys/malloc.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/cpu.h>
 #include <machine/bus.h>
 #include <machine/intr.h>
 @@ -119,98 +122,78 @@ struct gdium_intrhead {
 	int intr_refcnt;
 };
 struct gdium_intrhead gdium_intrtab[__arraycount(gdium_irqmap)];
 #define	NINTRS			2	/* MIPS INT0 - INT1 */
 struct gdium_cpuintr {
 	LIST_HEAD(, evbmips_intrhand) cintr_list;
 	struct evcnt cintr_count;
 	int cintr_refcnt;
 };
 struct gdium_cpuintr gdium_cpuintrs[NINTRS];
-const char *gdium_cpuintrnames[NINTRS] = {
+const char * const gdium_cpuintrnames[NINTRS] = {
 	"int 0 (pci)",
 	"int 1 (errors)",
 };
 /*
  * This is a mask of bits to clear in the SR when we go to a
  * given hardware interrupt priority level.
  */
-const uint32_t ipl_sr_bits[_IPL_N] = {
+static const struct ipl_sr_map gdium_ipl_sr_map = {
-	[IPL_NONE] = 0,
+    .sr_bits = {
-	[IPL_SOFTCLOCK] =
+	[IPL_NONE] =		0,
-	    MIPS_SOFT_INT_MASK_0,
+	[IPL_SOFTCLOCK] =	MIPS_SOFT_INT_MASK_0,
-#if IPL_SOFTCLOCK != IPL_SOFTBIO
+	[IPL_SOFTNET] =		MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
 	[IPL_SOFTBIO] =
 	    MIPS_SOFT_INT_MASK_0,
 #endif
 	[IPL_SOFTNET] =
 	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
 #if IPL_SOFTNET != IPL_SOFTSERIAL
 	[IPL_SOFTSERIAL] =
 	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
 #endif
 	[IPL_VM] =
 	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
 	    MIPS_INT_MASK_0 |
 	    MIPS_INT_MASK_1 |
 	    MIPS_INT_MASK_2 |
 	    MIPS_INT_MASK_3 |
 	    MIPS_INT_MASK_4,
 	[IPL_SCHED] =
 	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
 	    MIPS_INT_MASK_0 |
 	    MIPS_INT_MASK_1 |
 	    MIPS_INT_MASK_2 |
 	    MIPS_INT_MASK_3 |
 	    MIPS_INT_MASK_4 |
 	    MIPS_INT_MASK_5,
 	[IPL_DDB] =		MIPS_INT_MASK,
 	[IPL_HIGH] =            MIPS_INT_MASK,
     },
 };
-/*
+int	gdium_pci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
  * This is a mask of bits to clear in the SR when we go to a
  * given software interrupt priority level.
  * Hardware ipls are port/board specific.
  */
 const uint32_t mips_ipl_si_to_sr[] = {
 	[IPL_SOFTCLOCK-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
 #if IPL_SOFTCLOCK != IPL_SOFTBIO
 	[IPL_SOFTBIO-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
 #endif
 	[IPL_SOFTNET-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
 #if IPL_SOFTNET != IPL_SOFTSERIAL
 	[IPL_SOFTSERIAL-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
 #endif
 };
 int	gdium_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
 const char *gdium_pci_intr_string(void *, pci_intr_handle_t);
 const struct evcnt *gdium_pci_intr_evcnt(void *, pci_intr_handle_t);
 void	*gdium_pci_intr_establish(void *, pci_intr_handle_t, int,
 	    int (*)(void *), void *);
 void	gdium_pci_intr_disestablish(void *, void *);
 void	gdium_pci_conf_interrupt(void *, int, int, int, int, int *);
 void
 evbmips_intr_init(void)
+{
-	struct gdium_config *gc = &gdium_configuration;
+	struct gdium_config * const gc = &gdium_configuration;
 	struct bonito_config *bc = &gc->gc_bonito;
 	const struct gdium_irqmap *irqmap;
 	uint32_t intbit;
-	int i;
+	size_t i;
 	ipl_sr_map = gdium_ipl_sr_map;
 	for (i = 0; i < NINTRS; i++) {
 		LIST_INIT(&gdium_cpuintrs[i].cintr_list);
 		evcnt_attach_dynamic(&gdium_cpuintrs[i].cintr_count,
 		    EVCNT_TYPE_INTR, NULL, "mips", gdium_cpuintrnames[i]);
+	}
 	//evcnt_attach_static(&mips_int5_evcnt);
 	for (i = 0; i < __arraycount(gdium_irqmap); i++) {
 		irqmap = &gdium_irqmap[i];
 		intbit = 1 << irqmap->irqidx;
 		evcnt_attach_dynamic(&gdium_intrtab[i].intr_count,
 @@ -306,64 +289,59 @@ evbmips_intr_disestablish(void *cookie)
 	/*
 	 * Now, disable it, if there is nothing remaining on the
 	 * list.
 	 */
 	if (gdium_intrtab[ih->ih_irq].intr_refcnt-- == 1)
 		REGVAL(BONITO_INTENCLR) = (1 << ih->ih_irq);
 	splx(s);
 	free(ih, M_DEVBUF);
+}
 void
-evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc,
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
 	uint32_t ipending)
+{
 	const struct gdium_irqmap *irqmap;
 	struct evbmips_intrhand *ih;
 	int level;
 	uint32_t isr;
 	/*
 	 * Read the interrupt pending registers, mask them with the
 	 * ones we have enabled, and service them in order of decreasing
 	 * priority.
 	 */
 	isr = REGVAL(BONITO_INTISR) & REGVAL(BONITO_INTEN);
 	for (level = 1; level >= 0; level--) {
 		if ((ipending & (MIPS_INT_MASK_4 << level)) == 0)
 			continue;
 		gdium_cpuintrs[level].cintr_count.ev_count++;
 		LIST_FOREACH (ih, &gdium_cpuintrs[level].cintr_list, ih_q) {
 			irqmap = &gdium_irqmap[ih->ih_irq];
 			if (isr & (1 << ih->ih_irq)) {
 				gdium_intrtab[ih->ih_irq].intr_count.ev_count++;
 				(*ih->ih_func)(ih->ih_arg);
+			}
+		}
 		cause &= ~(MIPS_INT_MASK_0 << level);
+	}
 	/* Re-enable anything that we have processed. */
 	_splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
+}
 /*****************************************************************************
  * PCI interrupt support
  *****************************************************************************/
 int
-gdium_pci_intr_map(struct pci_attach_args *pa,
+gdium_pci_intr_map(const struct pci_attach_args *pa,
     pci_intr_handle_t *ihp)
+{
 	static const int8_t pciirqmap[5/*device*/] = {
 	    GDIUM_IRQ_PCI_INTC, /* 13: PCI 802.11 */
 	    GDIUM_IRQ_PCI_INTA, /* 14: SM501 */
 	    GDIUM_IRQ_PCI_INTB, /* 15: NEC USB (2 func) */
 	    GDIUM_IRQ_PCI_INTD, /* 16: Ethernet */
 	    GDIUM_IRQ_PCI_INTC, /* 17: NEC USB (2 func) */
 	};
 	pcitag_t bustag = pa->pa_intrtag;
 	int buspin = pa->pa_intrpin;
 	pci_chipset_tag_t pc = pa->pa_pc;
 	int device;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $	*/
+/*	$NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $	*/
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -64,27 +64,27 @@
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)machdep.c   8.3 (Berkeley) 1/12/94
  *	from: Utah Hdr: machdep.c 1.63 91/04/24
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $");
 #include "opt_ddb.h"
 #include "opt_execfmt.h"
 #include "opt_modular.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/buf.h>
 #include <sys/reboot.h>
 #include <sys/mount.h>
 #include <sys/kcore.h>
 #include <sys/boot_flag.h>
 @@ -96,49 +96,48 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v
 #include <dev/cons.h>
 #include "ksyms.h"
 #if NKSYMS || defined(DDB) || defined(MODULAR)
 #include <machine/db_machdep.h>
 #include <ddb/db_extern.h>
 #endif
 #include <machine/cpu.h>
 #include <machine/psl.h>
 #include <mips/locore.h>
 #include <mips/bonito/bonitoreg.h>
 #include <evbmips/gdium/gdiumvar.h>
 #include "com.h"
 #if NCOM > 0
 #include <dev/ic/comreg.h>
 #include <dev/ic/comvar.h>
 int	comcnrate = 38400;	/* XXX should be config option */
 #endif /* NCOM > 0 */
 struct gdium_config gdium_configuration = {
 	.gc_bonito = {
 		.bc_adbase = 11,	/* magic */
 	},
 };
 /* For sysctl_hw. */
 extern char cpu_model[];
 /* Our exported CPU info; we can have only one. */
 struct cpu_info cpu_info_store;
 /* Maps for VM objects. */
 struct vm_map *phys_map = NULL;
 int	netboot;		/* Are we netbooting? */
 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
 int mem_cluster_cnt;
 void	configure(void);
 void	mach_init(int, char **, char **, void *);
 /*
  * For some reason, PMON doesn't assign a real address to the Ralink's BAR.
 @@ -190,52 +189,49 @@ gdium_pci_attach_hook(device_t parent, d
+		}
+	}
 #endif
+}
 /*
  * Do all the stuff that locore normally does before calling main().
  */
 void
 mach_init(int argc, char **argv, char **envp, void *callvec)
+{
 	struct gdium_config *gc = &gdium_configuration;
 	void *kernend;
 	u_long first, last;
 	struct pcb *pcb0;
 	vaddr_t v;
 #ifdef NOTYET
 	char *cp;
 	int howto;
 #endif
 	int i;
 	psize_t memsize;
 	extern char edata[], end[];
 	/*
 	 * Clear the BSS segment.
 	 */
 	kernend = (void *)mips_round_page(end);
 	memset(edata, 0, (char *)kernend - edata);
 	/*
 	 * Set up the exception vectors and CPU-specific function
 	 * vectors early on.  We need the wbflush() vector set up
 	 * before comcnattach() is called (or at least before the
 	 * first printf() after that is called).
 	 * Also clears the I+D caches.
 	 */
-	mips_vector_init(NULL, bool);
+	mips_vector_init(NULL, false);
 	/* set the VM page size */
 	uvm_setpagesize();
 	memsize = 256*1024*1024;
 	physmem = btoc(memsize);
 	bonito_pci_init(&gc->gc_pc, &gc->gc_bonito);
 	/*
 	 * Override the null bonito_pci_attach_hook with our own to we can
 	 * fix the ralink (device 13).
 	 */
 	gc->gc_pc.pc_attach_hook = gdium_pci_attach_hook;
 @@ -251,41 +247,41 @@ mach_init(int argc, char **argv, char **
 	pci_conf_write(&gc->gc_pc, pci_make_tag(&gc->gc_pc, 0, 0, 0), 18, 0);
 	/*
 	 * Get the timer from PMON.
 	 */
 	for (i = 0; envp[i] != NULL; i++) {
 		if (!strncmp(envp[i], "cpuclock=", 9)) {
 			curcpu()->ci_cpu_freq =
 			    strtoul(&envp[i][9], NULL, 10);
 			break;
+		}
+	}
-	if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+	if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
 		curcpu()->ci_cpu_freq /= 2;
 	/* Compute the number of ticks for hz. */
 	curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
 	/* Compute the delay divisor. */
 	curcpu()->ci_divisor_delay =
 	    ((curcpu()->ci_cpu_freq + 500000) / 1000000);
 	/*
 	 * Get correct cpu frequency if the CPU runs at twice the
 	 * external/cp0-count frequency.
 	 */
-	if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+	if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
 		curcpu()->ci_cpu_freq *= 2;
 #ifdef DEBUG
 	printf("Timer calibration: %lu cycles/sec\n",
 	    curcpu()->ci_cpu_freq);
 #endif
 #if NCOM > 0
 	/*
 	 * Delay to allow firmware putchars to complete.
 	 * FIFO depth * character time.
 	 * character time = (1000000 / (defaultrate / 10))
 	 */
 @@ -320,116 +316,87 @@ mach_init(int argc, char **argv, char **
 			howto = 0;
 			BOOT_FLAG(*cp, howto);
 			if (! howto)
 				printf("bootflag '%c' not recognised\n", *cp);
 			else
 				boothowto |= howto;
+		}
+	}
 #endif
 	/*
 	 * Load the rest of the available pages into the VM system.
 	 */
-	first = round_page(MIPS_KSEG0_TO_PHYS(kernend));
+	mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
-	last = mem_clusters[0].start + mem_clusters[0].size;
+	    mem_clusters, mem_cluster_cnt, NULL, 0);
 	uvm_page_physload(atop(first), atop(last), atop(first), atop(last),
 		VM_FREELIST_DEFAULT);
 	/*
 	 * Initialize error message buffer (at end of core).
 	 */
 	mips_init_msgbuf();
 	pmap_bootstrap();
 	/*
 	 * Allocate uarea page for lwp0 and set it.
 	 */
-	v = uvm_pageboot_alloc(USPACE);
+	mips_init_lwp0_uarea();
 	uvm_lwp_setuarea(&lwp0, v);
 	pcb0 = lwp_getpcb(&lwp0);
 	pcb0->pcb_context[11] = MIPS_INT_MASK | MIPS_SR_INT_IE; /* SR */
 	lwp0.l_md.md_regs = (struct frame *)(v + USPACE) - 1;
 	/*
 	 * Initialize debuggers, and break into them, if appropriate.
 	 */
 #if defined(DDB)
 	if (boothowto & RB_KDB)
 		Debugger();
 #endif
+}
 void
 consinit(void)
+{
 	/*
 	 * Everything related to console initialization is done
 	 * in mach_init().
 	 */
+}
 /*
  * Allocate memory for variable-sized tables,
  */
 void
 cpu_startup(void)
+{
 	vaddr_t minaddr, maxaddr;
 	char pbuf[9];
 	/*
-	 * Good {morning,afternoon,evening,night}.
+	 *  Do the common startup items.
 	 */
-	printf("%s%s", copyright, version);
+	cpu_startup_common();
 	format_bytes(pbuf, sizeof(pbuf), ctob(physmem));
 	printf("total memory = %s\n", pbuf);
 	/*
 	 * Virtual memory is bootstrapped -- notify the bus spaces
 	 * that memory allocation is now safe.
 	 */
 	gdium_configuration.gc_mallocsafe = 1;
 	minaddr = 0;
 	/*
 	 * Allocate a submap for physio.
 	 */
 	phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
 				    VM_PHYS_SIZE, 0, FALSE, NULL);
 	/*
 	 * (No need to allocate an mbuf cluster submap.  Mbuf clusters
 	 * are allocated via the pool allocator, and we use KSEG to
 	 * map those pages.)
 	 */
 	format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free));
 	printf("avail memory = %s\n", pbuf);
+}
 int	waittime = -1;
 void
 cpu_reboot(int howto, char *bootstr)
+{
 	/* Take a snapshot before clobbering any registers. */
-	if (curproc)
+	savectx(curpcb);
 		savectx(curpcb);
 	if (cold) {
 		howto |= RB_HALT;
 		goto haltsys;
+	}
 	/* If "always halt" was specified as a boot flag, obey. */
 	if (boothowto & RB_HALT)
 		howto |= RB_HALT;
 	boothowto = howto;
 	if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) {
 		waittime = 0;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cache.c,v 1.46 2011/03/15 07:39:22 matt Exp $	*/
+/*	$NetBSD: cache.c,v 1.47 2011/06/08 17:47:48 bouyer Exp $	*/
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -58,27 +58,27 @@
  *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
  *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
  *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
  *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
  *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.46 2011/03/15 07:39:22 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.47 2011/06/08 17:47:48 bouyer Exp $");
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
 #include <sys/param.h>
 #include <uvm/uvm_extern.h>
 #include <mips/cache.h>
 #include <mips/locore.h>
 #ifdef MIPS1
 #include <mips/cache_r3k.h>
 @@ -576,60 +576,60 @@ primary_cache_is_2way:
 		    r10k_pdcache_wbinv_all;
 		mco->mco_pdcache_wbinv_range =
 		    r10k_pdcache_wbinv_range;
 		mco->mco_pdcache_wbinv_range_index =
 		    r10k_pdcache_wbinv_range_index;
 		mco->mco_pdcache_inv_range =
 		    r10k_pdcache_inv_range;
 		mco->mco_pdcache_wb_range =
 		    r10k_pdcache_wb_range;
 		break;
 #endif /* ENABLE_MIPS4_CACHE_R10K */
 #ifdef MIPS3_LOONGSON2
 	case MIPS_LOONGSON2:
-		mips_picache_ways = 4;
+		mci->mci_picache_ways = 4;
-		mips_pdcache_ways = 4;
+		mci->mci_pdcache_ways = 4;
 		mips3_get_cache_config(csizebase);
-		mips_sdcache_line_size = 32;	/* don't trust config reg */
+		mci->mci_sdcache_line_size = 32;	/* don't trust config reg */
-		if (mips_picache_size / mips_picache_ways > PAGE_SIZE ||
+		if (mci->mci_picache_size / mci->mci_picache_ways > PAGE_SIZE ||
-		    mips_pdcache_size / mips_pdcache_ways > PAGE_SIZE)
+		    mci->mci_pdcache_size / mci->mci_pdcache_ways > PAGE_SIZE)
-			mips_cache_virtual_alias = 1;
+			mci->mci_cache_virtual_alias = 1;
-		mips_cache_ops.mco_icache_sync_all =
+		mco->mco_icache_sync_all =
 		    ls2_icache_sync_all;
-		mips_cache_ops.mco_icache_sync_range =
+		mco->mco_icache_sync_range =
 		    ls2_icache_sync_range;
-		mips_cache_ops.mco_icache_sync_range_index =
+		mco->mco_icache_sync_range_index =
 		    ls2_icache_sync_range_index;
-		mips_cache_ops.mco_pdcache_wbinv_all =
+		mco->mco_pdcache_wbinv_all =
 		    ls2_pdcache_wbinv_all;
-		mips_cache_ops.mco_pdcache_wbinv_range =
+		mco->mco_pdcache_wbinv_range =
 		    ls2_pdcache_wbinv_range;
-		mips_cache_ops.mco_pdcache_wbinv_range_index =
+		mco->mco_pdcache_wbinv_range_index =
 		    ls2_pdcache_wbinv_range_index;
-		mips_cache_ops.mco_pdcache_inv_range =
+		mco->mco_pdcache_inv_range =
 		    ls2_pdcache_inv_range;
-		mips_cache_ops.mco_pdcache_wb_range =
+		mco->mco_pdcache_wb_range =
 		    ls2_pdcache_wb_range;
 		/*
 		 * For current version chips, [the] operating system is
 		 * obliged to eliminate the potential for virtual aliasing.
 		 */
-		uvmexp.ncolors = mips_pdcache_ways;
+		uvmexp.ncolors = mci->mci_pdcache_ways;
 		break;
 #endif
 #endif /* MIPS3 || MIPS4 */
 	default:
 		panic("can't handle primary cache on impl 0x%x",
 		    MIPS_PRID_IMPL(cpu_id));
+	}
 	/*
 	 * Compute the "way mask" for each cache.
 	 */
 	if (mci->mci_picache_size) {
 		KASSERT(mci->mci_picache_ways != 0);
 @@ -758,39 +758,39 @@ primary_cache_is_2way:
 		    r10k_sdcache_wbinv_all;
 		mco->mco_sdcache_wbinv_range =
 		    r10k_sdcache_wbinv_range;
 		mco->mco_sdcache_wbinv_range_index =
 		    r10k_sdcache_wbinv_range_index;
 		mco->mco_sdcache_inv_range =
 		    r10k_sdcache_inv_range;
 		mco->mco_sdcache_wb_range =
 		    r10k_sdcache_wb_range;
 		break;
 #endif /* ENABLE_MIPS4_CACHE_R10K */
 #ifdef MIPS3_LOONGSON2
 	case MIPS_LOONGSON2:
-		mips_sdcache_ways = 4;
+		mci->mci_sdcache_ways = 4;
-		mips_sdcache_size = 512*1024;
+		mci->mci_sdcache_size = 512*1024;
-		mips_scache_unified = 1;
+		mci->mci_scache_unified = 1;
-		mips_cache_ops.mco_sdcache_wbinv_all =
+		mco->mco_sdcache_wbinv_all =
 		    ls2_sdcache_wbinv_all;
-		mips_cache_ops.mco_sdcache_wbinv_range =
+		mco->mco_sdcache_wbinv_range =
 		    ls2_sdcache_wbinv_range;
-		mips_cache_ops.mco_sdcache_wbinv_range_index =
+		mco->mco_sdcache_wbinv_range_index =
 		    ls2_sdcache_wbinv_range_index;
-		mips_cache_ops.mco_sdcache_inv_range =
+		mco->mco_sdcache_inv_range =
 		    ls2_sdcache_inv_range;
-		mips_cache_ops.mco_sdcache_wb_range =
+		mco->mco_sdcache_wb_range =
 		    ls2_sdcache_wb_range;
 		/*
 		 * The secondary cache is physically indexed and tagged
 		 */
 		break;
 #endif
 #endif /* MIPS3 || MIPS4 */
 	default:
 		panic("can't handle secondary cache on impl 0x%x",
 		    MIPS_PRID_IMPL(cpu_id));
+	}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $	*/
+/*	$NetBSD: cache_ls2.c,v 1.4 2011/06/08 17:47:48 bouyer Exp $	*/
 /*-
  * Copyright (c) 2009 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas <matt@3am-software.com>.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -20,111 +20,114 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.4 2011/06/08 17:47:48 bouyer Exp $");
 #include <sys/param.h>
 #include <mips/cache.h>
 #include <mips/cache_ls2.h>
 #include <mips/locore.h>
 /*
  * Cache operations for Loongson2-style caches:
+ *
  *	- 4-way set-associative 32b/l
  *	- Write-back
  *	- Primary is virtually indexed, physically tagged
  *	- Seconadry is physically indexed, physically tagged
  */
 #define	round_line(x)		(((x) + 31) & ~31)
 #define	trunc_line(x)		((x) & ~31)
 __asm(".set mips3");
 void
 ls2_icache_sync_range(vaddr_t va, vsize_t size)
+{
 	struct mips_cache_info * const mci = &mips_cache_info;
 	const vaddr_t eva = round_line(va + size);
 	va = trunc_line(va);
-	if (va + mips_picache_size <= eva) {
+	if (va + mci->mci_picache_size <= eva) {
 		ls2_icache_sync_all();
 		return;
+	}
 	for (; va + 8 * 32 <= eva; va += 8 * 32) {
 		cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV);
 		cache_op_ls2_8line(va, CACHEOP_LS2_I_INDEX_INV);
+	}
 	for (; va < eva; va += 32) {
 		cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV);
 		cache_op_ls2_line(va, CACHEOP_LS2_I_INDEX_INV);
+	}
 	__asm volatile("sync");
+}
 void
 ls2_icache_sync_range_index(vaddr_t va, vsize_t size)
+{
 	vaddr_t eva;
 	struct mips_cache_info * const mci = &mips_cache_info;
 	/*
 	 * Since we're doing Index ops, we expect to not be able
 	 * to access the address we've been given.  So, get the
 	 * bits that determine the cache index, and make a KSEG0
 	 * address out of them.
 	 */
-	va = MIPS_PHYS_TO_KSEG0(va & mips_picache_way_mask);
+	va = MIPS_PHYS_TO_KSEG0(va & mci->mci_picache_way_mask);
 	eva = round_line(va + size);
 	va = trunc_line(va);
-	if (va + mips_picache_way_size < eva) {
+	if (va + mci->mci_picache_way_size < eva) {
 		va = MIPS_PHYS_TO_KSEG0(0);
-		eva = mips_picache_way_size;
+		eva = mci->mci_picache_way_size;
+	}
 	for (; va + 8 * 32 <= eva; va += 8 * 32) {
 		cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
 		cache_op_ls2_8line(va, CACHEOP_LS2_I_INDEX_INV);
+	}
 	for (; va < eva; va += 32) {
 		cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
 		cache_op_ls2_line(va, CACHEOP_LS2_I_INDEX_INV);
+	}
 	__asm volatile("sync");
+}
 void
 ls2_icache_sync_all(void)
+{
-	ls2_icache_sync_range_index(0, mips_picache_way_size);
+	struct mips_cache_info * const mci = &mips_cache_info;
 	ls2_icache_sync_range_index(0, mci->mci_picache_way_size);
+}
 void
 ls2_pdcache_inv_range(vaddr_t va, vsize_t size)
+{
 	const vaddr_t eva = round_line(va + size);
 	va = trunc_line(va);
 	for (; va + 8 * 32 <= eva; va += 8 * 32) {
 		cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_INV);
+	}
 @@ -156,58 +159,60 @@ ls2_pdcache_wbinv_range(vaddr_t va, vsiz
 void
 ls2_pdcache_wb_range(vaddr_t va, vsize_t size)
+{
 	/*
 	 * Alas, can't writeback without invalidating...
 	 */
 	ls2_pdcache_wbinv_range(va, size);
+}
 void
 ls2_pdcache_wbinv_range_index(vaddr_t va, vsize_t size)
+{
 	vaddr_t eva;
 	struct mips_cache_info * const mci = &mips_cache_info;
 	/*
 	 * Since we're doing Index ops, we expect to not be able
 	 * to access the address we've been given.  So, get the
 	 * bits that determine the cache index, and make a KSEG0
 	 * address out of them.
 	 */
-	va = MIPS_PHYS_TO_KSEG0(va & mips_pdcache_way_mask);
+	va = MIPS_PHYS_TO_KSEG0(va & mci->mci_pdcache_way_mask);
 	eva = round_line(va + size);
 	va = trunc_line(va);
-	if (va + mips_pdcache_way_size > eva) {
+	if (va + mci->mci_pdcache_way_size > eva) {
 		va = MIPS_PHYS_TO_KSEG0(0);
-		eva = mips_pdcache_way_size;
+		eva = mci->mci_pdcache_way_size;
+	}
 	for (; va + 8 * 32 <= eva; va += 8 * 32) {
 		cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
+	}
 	for (; va < eva; va += 32) {
 		cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
+	}
 	__asm volatile("sync");
+}
 void
 ls2_pdcache_wbinv_all(void)
+{
-	ls2_pdcache_wbinv_range_index(0, mips_pdcache_way_size);
+	struct mips_cache_info * const mci = &mips_cache_info;
 	ls2_pdcache_wbinv_range_index(0, mci->mci_pdcache_way_size);
+}
 /*
  * Cache operations for secondary caches:
+ *
  *	- Direct-mapped
  *	- Write-back
  *	- Physically indexed, physically tagged
+ *
  */
 void
 ls2_sdcache_inv_range(vaddr_t va, vsize_t size)
 @@ -252,48 +257,50 @@ ls2_sdcache_wbinv_range(vaddr_t va, vsiz
 void
 ls2_sdcache_wb_range(vaddr_t va, vsize_t size)
+{
 	/*
 	 * Alas, can't writeback without invalidating...
 	 */
 	ls2_sdcache_wbinv_range(va, size);
+}
 void
 ls2_sdcache_wbinv_range_index(vaddr_t va, vsize_t size)
+{
 	vaddr_t eva;
 	struct mips_cache_info * const mci = &mips_cache_info;
 	/*
 	 * Since we're doing Index ops, we expect to not be able
 	 * to access the address we've been given.  So, get the
 	 * bits that determine the cache index, and make a KSEG0
 	 * address out of them.
 	 */
-	va = MIPS_PHYS_TO_KSEG0(va & mips_sdcache_way_mask);
+	va = MIPS_PHYS_TO_KSEG0(va & mci->mci_sdcache_way_mask);
 	eva = round_line(va + size);
 	va = trunc_line(va);
-	if (va + mips_sdcache_way_size > eva) {
+	if (va + mci->mci_sdcache_way_size > eva) {
 		va = MIPS_PHYS_TO_KSEG0(0);
-		eva = va + mips_sdcache_way_size;
+		eva = va + mci->mci_sdcache_way_size;
+	}
 	for (; va + 8 * 32 <= eva; va += 8 * 32) {
 		cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
 		cache_op_ls2_8line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV);
+	}
 	for (; va < eva; va += 32) {
 		cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
 		cache_op_ls2_line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV);
+	}
 	__asm volatile("sync");
+}
 void
 ls2_sdcache_wbinv_all(void)
+{
-	ls2_sdcache_wbinv_range_index(0, mips_sdcache_way_size);
+	struct mips_cache_info * const mci = &mips_cache_info;
 	ls2_sdcache_wbinv_range_index(0, mci->mci_sdcache_way_size);
+}

 @@ -1,31 +1,30 @@
-#	$NetBSD: files.gdium,v 1.1 2009/08/06 00:50:25 matt Exp $
+#	$NetBSD: files.gdium,v 1.2 2011/06/08 17:47:48 bouyer Exp $
 file	arch/evbmips/gdium/gdium_bus_io.c
 file	arch/evbmips/gdium/gdium_bus_mem.c
 file	arch/evbmips/gdium/gdium_dma.c
 file	arch/evbmips/gdium/gdium_genfb.c	wsdisplay
 file	arch/evbmips/gdium/gdium_intr.c
 file	arch/evbmips/gdium/autoconf.c
 file	arch/evbmips/gdium/machdep.c
 file	arch/mips/mips/bus_dma.c
 file	arch/evbmips/evbmips/disksubr.c
 file	arch/evbmips/evbmips/interrupt.c
 file	arch/mips/mips/mips3_clock.c
 file	arch/mips/mips/mips3_clockintr.c
 file	arch/mips/mips/softintr.c
 # The autoconfiguration root.
 device	mainbus { [addr = -1] }
 attach	mainbus at root
 file	arch/evbmips/gdium/mainbus.c		mainbus
 device	cpu
 attach	cpu at mainbus
 file	arch/evbmips/evbmips/cpu.c		cpu
 # Machine-independent I2O drivers.
 include "dev/i2o/files.i2o"