| @@ -381,27 +381,31 @@ static const struct pci_device_id pciidl | | | @@ -381,27 +381,31 @@ static const struct pci_device_id pciidl |
381 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ | | 381 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ |
382 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */ | | 382 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */ |
383 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ | | 383 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ |
384 | INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */ | | 384 | INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */ |
385 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */ | | 385 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */ |
386 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ | | 386 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ |
387 | INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */ | | 387 | INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */ |
388 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */ | | 388 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */ |
389 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ | | 389 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ |
390 | INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */ | | 390 | INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */ |
391 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), | | 391 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
392 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), | | 392 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
393 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), | | 393 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), |
| | | 394 | #ifdef __NetBSD__ |
| | | 395 | {0, 0, 0, 0, 0, 0, 0} |
| | | 396 | #else |
394 | {0, 0, 0} | | 397 | {0, 0, 0} |
| | | 398 | #endif |
395 | }; | | 399 | }; |
396 | | | 400 | |
397 | #if defined(CONFIG_DRM_I915_KMS) | | 401 | #if defined(CONFIG_DRM_I915_KMS) |
398 | MODULE_DEVICE_TABLE(pci, pciidlist); | | 402 | MODULE_DEVICE_TABLE(pci, pciidlist); |
399 | #endif | | 403 | #endif |
400 | | | 404 | |
401 | void intel_detect_pch(struct drm_device *dev) | | 405 | void intel_detect_pch(struct drm_device *dev) |
402 | { | | 406 | { |
403 | struct drm_i915_private *dev_priv = dev->dev_private; | | 407 | struct drm_i915_private *dev_priv = dev->dev_private; |
404 | struct pci_dev *pch; | | 408 | struct pci_dev *pch; |
405 | | | 409 | |
406 | /* | | 410 | /* |
407 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | | 411 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |