Fri Jan 10 17:48:11 2014 UTC ()
Flush out the PSR definitions.


(matt)
diff -r1.84 -r1.85 src/sys/arch/arm/include/armreg.h
cvs diff -r1.84 -r1.85 src/sys/arch/arm/include/armreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/include/armreg.h 2013/12/27 12:16:01 1.84
+++ src/sys/arch/arm/include/armreg.h 2014/01/10 17:48:11 1.85
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: armreg.h,v 1.84 2013/12/27 12:16:01 matt Exp $ */ 1/* $NetBSD: armreg.h,v 1.85 2014/01/10 17:48:11 matt Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1998, 2001 Ben Harris 4 * Copyright (c) 1998, 2001 Ben Harris
5 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994-1996 Mark Brinicombe.
6 * Copyright (c) 1994 Brini. 6 * Copyright (c) 1994 Brini.
7 * All rights reserved. 7 * All rights reserved.
8 * 8 *
9 * This code is derived from software written for Brini by Mark Brinicombe 9 * This code is derived from software written for Brini by Mark Brinicombe
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -48,33 +48,44 @@ @@ -48,33 +48,44 @@
48 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 48 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
49 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 49 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M|
50 * | | | | | | | | | |4 3 2 1 0| 50 * | | | | | | | | | |4 3 2 1 0|
51 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 51 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
52 */ 52 */
53 53
54#define PSR_FLAGS 0xf0000000 /* flags */ 54#define PSR_FLAGS 0xf0000000 /* flags */
55#define PSR_N_bit (1 << 31) /* negative */ 55#define PSR_N_bit (1 << 31) /* negative */
56#define PSR_Z_bit (1 << 30) /* zero */ 56#define PSR_Z_bit (1 << 30) /* zero */
57#define PSR_C_bit (1 << 29) /* carry */ 57#define PSR_C_bit (1 << 29) /* carry */
58#define PSR_V_bit (1 << 28) /* overflow */ 58#define PSR_V_bit (1 << 28) /* overflow */
59 59
60#define PSR_Q_bit (1 << 27) /* saturation */ 60#define PSR_Q_bit (1 << 27) /* saturation */
 61#define PSR_IT1_bit (1 << 26)
 62#define PSR_IT0_bit (1 << 25)
 63#define PSR_J_bit (1 << 24) /* Jazelle mode */
 64#define PSR_GE_bits (15 << 16) /* SIMD GE bits */
 65#define PSR_IT7_bit (1 << 15)
 66#define PSR_IT6_bit (1 << 14)
 67#define PSR_IT5_bit (1 << 13)
 68#define PSR_IT4_bit (1 << 12)
 69#define PSR_IT3_bit (1 << 11)
 70#define PSR_IT2_bit (1 << 10)
 71#define PSR_E_BIT (1 << 9) /* Endian state */
 72#define PSR_A_BIT (1 << 8) /* Async abort disable */
61 73
62#define I32_bit (1 << 7) /* IRQ disable */ 74#define I32_bit (1 << 7) /* IRQ disable */
63#define F32_bit (1 << 6) /* FIQ disable */ 75#define F32_bit (1 << 6) /* FIQ disable */
64#define IF32_bits (3 << 6) /* IRQ/FIQ disable */ 76#define IF32_bits (3 << 6) /* IRQ/FIQ disable */
65 77
66#define PSR_T_bit (1 << 5) /* Thumb state */ 78#define PSR_T_bit (1 << 5) /* Thumb state */
67#define PSR_J_bit (1 << 24) /* Java mode */ 
68 79
69#define PSR_MODE 0x0000001f /* mode mask */ 80#define PSR_MODE 0x0000001f /* mode mask */
70#define PSR_USR26_MODE 0x00000000 81#define PSR_USR26_MODE 0x00000000
71#define PSR_FIQ26_MODE 0x00000001 82#define PSR_FIQ26_MODE 0x00000001
72#define PSR_IRQ26_MODE 0x00000002 83#define PSR_IRQ26_MODE 0x00000002
73#define PSR_SVC26_MODE 0x00000003 84#define PSR_SVC26_MODE 0x00000003
74#define PSR_USR32_MODE 0x00000010 85#define PSR_USR32_MODE 0x00000010
75#define PSR_FIQ32_MODE 0x00000011 86#define PSR_FIQ32_MODE 0x00000011
76#define PSR_IRQ32_MODE 0x00000012 87#define PSR_IRQ32_MODE 0x00000012
77#define PSR_SVC32_MODE 0x00000013 88#define PSR_SVC32_MODE 0x00000013
78#define PSR_MON32_MODE 0x00000016 89#define PSR_MON32_MODE 0x00000016
79#define PSR_ABT32_MODE 0x00000017 90#define PSR_ABT32_MODE 0x00000017
80#define PSR_HYP32_MODE 0x0000001a 91#define PSR_HYP32_MODE 0x0000001a