 @@ -1,39 +1,39 @@
-/*	$NetBSD: sdhc.c,v 1.54 2015/02/27 15:53:09 nonaka Exp $	*/
+/*	$NetBSD: sdhc.c,v 1.55 2015/04/14 18:34:29 bouyer Exp $	*/
 /*	$OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 /*
  * SD Host Controller driver based on the SD Host Controller Standard
  * Simplified Specification Version 1.00 (www.sdcard.com).
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.54 2015/02/27 15:53:09 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.55 2015/04/14 18:34:29 bouyer Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_sdmmc.h"
 #endif
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/kthread.h>
 #include <sys/malloc.h>
 #include <sys/systm.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 @@ -76,26 +76,27 @@ struct sdhc_host {
 	uint8_t regs[14];		/* host controller state */
 	uint16_t intr_status;		/* soft interrupt status */
 	uint16_t intr_error_status;	/* soft error status */
 	struct kmutex intr_mtx;
 	struct kcondvar intr_cv;
 	int specver;			/* spec. version */
 	uint32_t flags;			/* flags for this host */
 #define SHF_USE_DMA		0x0001
 #define SHF_USE_4BIT_MODE	0x0002
 #define SHF_USE_8BIT_MODE	0x0004
 #define SHF_MODE_DMAEN		0x0008 /* needs SDHC_DMA_ENABLE in mode */
 };
 #define HDEVNAME(hp)	(device_xname((hp)->sc->sc_dev))
 static uint8_t
 hread1(struct sdhc_host *hp, bus_size_t reg)
+{
 	if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS))
 		return bus_space_read_1(hp->iot, hp->ioh, reg);
 	return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3));
+}
 @@ -299,31 +300,39 @@ sdhc_host_found(struct sdhc_softc *sc, b
 	 * Reset the host controller and enable interrupts.
 	 */
 	(void)sdhc_host_reset(hp);
 	/* Determine host capabilities. */
 	if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) {
 		caps = sc->sc_caps;
 	} else {
 		mutex_enter(&hp->host_mtx);
 		caps = HREAD4(hp, SDHC_CAPABILITIES);
 		mutex_exit(&hp->host_mtx);
+	}
-	/* Use DMA if the host system and the controller support it. */
+	/*
 	 * Use DMA if the host system and the controller support it.
 	 * Suports integrated or external DMA egine, with or without
 	 * SDHC_DMA_ENABLE in the command.
 	 */
 	if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) ||
 	    (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA &&
 	     ISSET(caps, SDHC_DMA_SUPPORT)))) {
 		SET(hp->flags, SHF_USE_DMA);
 		if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) ||
 		    ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN))
 			SET(hp->flags, SHF_MODE_DMAEN);
 		aprint_normal_dev(sc->sc_dev, "using DMA transfer\n");
+	}
 	/*
 	 * Determine the base clock frequency. (2.2.24)
 	 */
 	if (hp->specver == SDHC_SPEC_VERS_300) {
 		hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps);
 	} else {
 		hp->clkbase = SDHC_BASE_FREQ_KHZ(caps);
+	}
 	if (hp->clkbase == 0) {
 		if (sc->sc_clkbase == 0) {
 @@ -1195,27 +1204,27 @@ sdhc_start_command(struct sdhc_host *hp,
 		return EINVAL;
+	}
 	/* Prepare transfer mode register value. (2.2.5) */
 	mode = SDHC_BLOCK_COUNT_ENABLE;
 	if (ISSET(cmd->c_flags, SCF_CMD_READ))
 		mode |= SDHC_READ_MODE;
 	if (blkcount > 1) {
 		mode |= SDHC_MULTI_BLOCK_MODE;
 		/* XXX only for memory commands? */
 		mode |= SDHC_AUTO_CMD12_ENABLE;
+	}
 	if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 &&
-	    !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) {
+	    ISSET(hp->flags,  SHF_MODE_DMAEN)) {
 		mode |= SDHC_DMA_ENABLE;
+	}
 	/*
 	 * Prepare command register value. (2.2.6)
 	 */
 	command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT;
 	if (ISSET(cmd->c_flags, SCF_RSP_CRC))
 		command |= SDHC_CRC_CHECK_ENABLE;
 	if (ISSET(cmd->c_flags, SCF_RSP_IDX))
 		command |= SDHC_INDEX_CHECK_ENABLE;
 	if (cmd->c_data != NULL)
 @@ -1241,27 +1250,28 @@ sdhc_start_command(struct sdhc_host *hp,
 	if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
 		blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) <<
 		    SDHC_DMA_BOUNDARY_SHIFT;	/* PAGE_SIZE DMA boundary */
+	}
 	mutex_enter(&hp->host_mtx);
 	if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
 		/* Alert the user not to remove the card. */
 		HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
+	}
 	/* Set DMA start address. */
-	if (ISSET(mode, SDHC_DMA_ENABLE))
+	if (ISSET(mode, SDHC_DMA_ENABLE) &&
 	    !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA))
 		HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr);
 	/*
 	 * Start a CPU data transfer.  Writing to the high order byte
 	 * of the SDHC_COMMAND register triggers the SD command. (1.5)
 	 */
 	if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
 		HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16));
 		HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
 		HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16));
 	} else {
 		HWRITE2(hp, SDHC_BLOCK_SIZE, blksize);
 		HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: sdhcvar.h,v 1.15 2014/10/04 18:09:32 jmcneill Exp $	*/
+/*	$NetBSD: sdhcvar.h,v 1.16 2015/04/14 18:34:29 bouyer Exp $	*/
 /*	$OpenBSD: sdhcvar.h,v 1.3 2007/09/06 08:01:01 jsg Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 @@ -26,41 +26,42 @@
 struct sdhc_host;
 struct sdmmc_command;
 struct sdhc_softc {
 	device_t		sc_dev;
 	struct sdhc_host	**sc_host;
 	int			sc_nhosts;
 	bus_dma_tag_t		sc_dmat;
 	uint32_t		sc_flags;
-#define	SDHC_FLAG_USE_DMA	0x0001
+#define	SDHC_FLAG_USE_DMA	0x00000001
-#define	SDHC_FLAG_FORCE_DMA	0x0002
+#define	SDHC_FLAG_FORCE_DMA	0x00000002
-#define	SDHC_FLAG_NO_PWR0	0x0004	/* Freescale ESDHC */
+#define	SDHC_FLAG_NO_PWR0	0x00000004 /* Freescale ESDHC */
-#define	SDHC_FLAG_HAVE_DVS	0x0008	/* Freescale ESDHC */
+#define	SDHC_FLAG_HAVE_DVS	0x00000008 /* Freescale ESDHC */
-#define	SDHC_FLAG_32BIT_ACCESS	0x0010	/* Freescale ESDHC */
+#define	SDHC_FLAG_32BIT_ACCESS	0x00000010 /* Freescale ESDHC */
-#define	SDHC_FLAG_ENHANCED	0x0020	/* Freescale ESDHC */
+#define	SDHC_FLAG_ENHANCED	0x00000020 /* Freescale ESDHC */
-#define	SDHC_FLAG_8BIT_MODE	0x0040	/* MMC 8bit mode is supported */
+#define	SDHC_FLAG_8BIT_MODE	0x00000040 /* MMC 8bit mode is supported */
-#define	SDHC_FLAG_HAVE_CGM	0x0080	/* Netlogic XLP */
+#define	SDHC_FLAG_HAVE_CGM	0x00000080 /* Netlogic XLP */
-#define	SDHC_FLAG_NO_LED_ON	0x0100	/* LED_ON unsupported in HOST_CTL */
+#define	SDHC_FLAG_NO_LED_ON	0x00000100 /* LED_ON unsupported in HOST_CTL */
-#define	SDHC_FLAG_HOSTCAPS	0x0200	/* No device provided capabilities */
+#define	SDHC_FLAG_HOSTCAPS	0x00000200 /* No device provided capabilities */
-#define	SDHC_FLAG_RSP136_CRC	0x0400	/* Resp 136 with CRC and end-bit */
+#define	SDHC_FLAG_RSP136_CRC	0x00000400 /* Resp 136 with CRC and end-bit */
-#define	SDHC_FLAG_SINGLE_ONLY	0x0800	/* Single transfer only */
+#define	SDHC_FLAG_SINGLE_ONLY	0x00000800 /* Single transfer only */
-#define	SDHC_FLAG_WAIT_RESET	0x1000	/* Wait for soft resets to start */
+#define	SDHC_FLAG_WAIT_RESET	0x00001000 /* Wait for soft resets to start */
-#define	SDHC_FLAG_NO_HS_BIT	0x2000	/* Don't set SDHC_HIGH_SPEED bit */
+#define	SDHC_FLAG_NO_HS_BIT	0x00002000 /* Don't set SDHC_HIGH_SPEED bit */
-#define	SDHC_FLAG_EXTERNAL_DMA	0x4000
+#define	SDHC_FLAG_EXTERNAL_DMA	0x00004000
 #define	SDHC_FLAG_EXTDMA_DMAEN	0x00008000 /* ext. dma need SDHC_DMA_ENABLE */
 	uint32_t		sc_clkbase;
 	int			sc_clkmsk;	/* Mask for SDCLK */
 	uint32_t		sc_caps;/* attachment provided capabilities */
 	int (*sc_vendor_rod)(struct sdhc_softc *, int);
 	int (*sc_vendor_write_protect)(struct sdhc_softc *);
 	int (*sc_vendor_card_detect)(struct sdhc_softc *);
 	int (*sc_vendor_bus_clock)(struct sdhc_softc *, int);
 	int (*sc_vendor_transfer_data_dma)(struct sdhc_softc *, struct sdmmc_command *);
 };
 /* Host controller functions called by the attachment driver. */