 @@ -1,14 +1,14 @@
-/*	$NetBSD: a9tmr.c,v 1.13 2015/07/24 05:19:13 ryo Exp $	*/
+/*	$NetBSD: a9tmr.c,v 1.14 2015/07/24 05:20:01 ryo Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -20,27 +20,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.13 2015/07/24 05:19:13 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.14 2015/07/24 05:20:01 ryo Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 #include <sys/timetc.h>
 #include <sys/xcall.h>
 #include <prop/proplib.h>
 @@ -106,27 +106,27 @@ a9tmr_match(device_t parent, cfdata_t cf
 	/*
 	 * This isn't present on UP A9s (since CBAR isn't present).
 	 */
 	uint32_t mpidr = armreg_mpidr_read();
 	if (mpidr == 0 || (mpidr & MPIDR_U))
 		return 0;
 	return 1;
+}
 static void
 a9tmr_attach(device_t parent, device_t self, void *aux)
+{
-        struct a9tmr_softc *sc = &a9tmr_sc;
+	struct a9tmr_softc *sc = &a9tmr_sc;
 	struct mpcore_attach_args * const mpcaa = aux;
 	prop_dictionary_t dict = device_properties(self);
 	char freqbuf[sizeof("XXX SHz")];
 	const char *cpu_type;
 	/*
 	 * This runs at the ARM PERIPHCLOCK which should be 1/2 of the CPU clock.
 	 * The MD code should have setup our frequency for us.
 	 */
 	prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq);
 	humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000);
 @@ -181,41 +181,43 @@ a9tmr_init_cpu_clock(struct cpu_info *ci
 	uint64_t now = a9tmr_gettime(sc);
 	KASSERT(ci == curcpu());
 	ci->ci_lastintr = now;
 	a9tmr_global_write(sc, TMR_GBL_AUTOINC, sc->sc_autoinc);
 	/*
 	 * To update the compare register we have to disable comparisions first.
 	 */
 	uint32_t ctl = a9tmr_global_read(sc, TMR_GBL_CTL);
 	if (ctl & TMR_GBL_CTL_CMP_ENABLE) {
-		a9tmr_global_write(sc, TMR_GBL_CTL, ctl & ~TMR_GBL_CTL_CMP_ENABLE);
+		a9tmr_global_write(sc, TMR_GBL_CTL,
 		    ctl & ~TMR_GBL_CTL_CMP_ENABLE);
+	}
 	/*
 	 * Schedule the next interrupt.
 	 */
 	now += sc->sc_autoinc;
 	a9tmr_global_write(sc, TMR_GBL_CMP_L, (uint32_t) now);
 	a9tmr_global_write(sc, TMR_GBL_CMP_H, (uint32_t) (now >> 32));
 	/*
 	 * Re-enable the comparator and now enable interrupts.
 	 */
 	a9tmr_global_write(sc, TMR_GBL_INT, 1);	/* clear interrupt pending */
-	ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE | TMR_GBL_CTL_AUTO_INC | TMR_CTL_ENABLE;
+	ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE |
 	    TMR_GBL_CTL_AUTO_INC | TMR_CTL_ENABLE;
 	a9tmr_global_write(sc, TMR_GBL_CTL, ctl);
 #if 0
 	printf("%s: %s: ctl %#x autoinc %u cmp %#x%08x now %#"PRIx64"\n",
 	    __func__, ci->ci_data.cpu_name,
 	    a9tmr_global_read(sc, TMR_GBL_CTL),
 	    a9tmr_global_read(sc, TMR_GBL_AUTOINC),
 	    a9tmr_global_read(sc, TMR_GBL_CMP_H),
 	    a9tmr_global_read(sc, TMR_GBL_CMP_L),
 	    a9tmr_gettime(sc));
 	int s = splsched();
 	uint64_t when = now;
 	u_int n = 0;
 @@ -232,27 +234,27 @@ a9tmr_init_cpu_clock(struct cpu_info *ci
 	    a9tmr_global_read(sc, TMR_GBL_CMP_H),
 	    a9tmr_global_read(sc, TMR_GBL_CMP_L),
 	    a9tmr_gettime(sc));
 	splx(s);
 #elif 0
 	delay(1000000 / hz + 1000);
 #endif
+}
 void
 cpu_initclocks(void)
+{
 	struct a9tmr_softc * const sc = &a9tmr_sc;
 	KASSERT(sc->sc_dev != NULL);
 	KASSERT(sc->sc_freq != 0);
 	sc->sc_autoinc = sc->sc_freq / hz;
 	a9tmr_init_cpu_clock(curcpu());
 	a9tmr_timecounter.tc_name = device_xname(sc->sc_dev);
 	a9tmr_timecounter.tc_frequency = sc->sc_freq;
 	tc_init(&a9tmr_timecounter);
+}
 @@ -280,27 +282,28 @@ a9tmr_update_freq(uint32_t freq)
 	xc_wait(xc);
 	a9tmr_timecounter.tc_frequency = sc->sc_freq;
 	tc_init(&a9tmr_timecounter);
+}
 void
 a9tmr_delay(unsigned int n)
+{
 	struct a9tmr_softc * const sc = &a9tmr_sc;
 	KASSERT(sc != NULL);
-	uint32_t freq = sc->sc_freq ? sc->sc_freq : curcpu()->ci_data.cpu_cc_freq / 2;
+	uint32_t freq = sc->sc_freq ? sc->sc_freq :
 	    curcpu()->ci_data.cpu_cc_freq / 2;
 	KASSERT(freq != 0);
 	/*
 	 * not quite divide by 1000000 but close enough
 	 * (higher by 1.3% which means we wait 1.3% longer).
 	 */
 	const uint64_t incr_per_us = (freq >> 20) + (freq >> 24);
 	const uint64_t delta = n * incr_per_us;
 	const uint64_t base = a9tmr_gettime(sc);
 	const uint64_t finish = base + delta;
 	while (a9tmr_gettime(sc) < finish) {
 @@ -309,31 +312,31 @@ a9tmr_delay(unsigned int n)
+}
 /*
  * clockhandler:
+ *
  *	Handle the hardclock interrupt.
  */
 static int
 clockhandler(void *arg)
+{
 	struct clockframe * const cf = arg;
 	struct a9tmr_softc * const sc = &a9tmr_sc;
 	struct cpu_info * const ci = curcpu();
 	const uint64_t now = a9tmr_gettime(sc);
 	uint64_t delta = now - ci->ci_lastintr;
-	a9tmr_global_write(sc, TMR_GBL_INT, 1);	// Ack the interrupt
+	a9tmr_global_write(sc, TMR_GBL_INT, 1);	/* Ack the interrupt */
 #if 0
 	printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n",
 	     __func__, cf, ci->ci_data.cpu_name, now, delta);
 #endif
 	KASSERTMSG(delta > sc->sc_autoinc / 64,
 	    "%s: interrupting too quickly (delta=%"PRIu64")",
 	    ci->ci_data.cpu_name, delta);
 	ci->ci_lastintr = now;
 	hardclock(cf);