 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_car.c,v 1.23 2015/07/23 18:22:05 jmcneill Exp $ */
+/* $NetBSD: tegra_car.c,v 1.24 2015/07/25 15:50:42 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -19,27 +19,27 @@
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "locators.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.23 2015/07/23 18:22:05 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.24 2015/07/25 15:50:42 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/rndpool.h>
 #include <sys/rndsource.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_carreg.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 @@ -525,44 +525,47 @@ tegra_car_utmip_enable(u_int port)
+	}
 	tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 0, bit);
+}
 void
 tegra_car_periph_hda_enable(void)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	tegra_car_get_bs(&bst, &bsh);
 	/* HDA */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG, CAR_DEV_V_HDA);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_HDA);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_HDA);
 	/* HDA2CODEC_2X */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG,
 	    CAR_DEV_V_HDA2CODEC_2X);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG,
 	    CAR_DEV_V_HDA2CODEC_2X);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG,
 	    CAR_DEV_V_HDA2CODEC_2X);
 	/* HDA2HDMICODEC */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_W_SET_REG,
 	    CAR_DEV_W_HDA2HDMICODEC);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG,
 	    CAR_DEV_W_HDA2HDMICODEC);
 	/* configure HDA2CODEC_2X for 48 MHz */
 	const u_int div = howmany(tegra_car_pllp0_rate() * 2, 48000000) - 2;
 	bus_space_write_4(bst, bsh, CAR_CLKSRC_HDA2CODEC_2X_REG,
 	    __SHIFTIN(CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0,
 		      CAR_CLKSRC_HDA2CODEC_2X_SRC) |
 	    __SHIFTIN(div, CAR_CLKSRC_HDA2CODEC_2X_DIV));
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_HDA);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG,
 	    CAR_DEV_V_HDA2CODEC_2X);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG,
 	    CAR_DEV_W_HDA2HDMICODEC);
+}
 void
 tegra_car_periph_sata_enable(void)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	tegra_car_get_bs(&bst, &bsh);
 	/* Assert resets */

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_carreg.h,v 1.19 2015/07/23 15:07:31 skrll Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.20 2015/07/25 15:50:42 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -380,26 +380,36 @@
 #define CAR_DEV_X_I2C6			__BIT(6)
 #define CAR_DEV_X_CAM_MCLK2		__BIT(5)
 #define CAR_DEV_X_CAM_MCLK		__BIT(4)
 #define CAR_DEV_X_SPARE			__BIT(0)
 #define CAR_CCLKG_BURST_POLICY_REG	0x368
 #define CAR_CCLKG_BURST_POLICY_CPU_STATE	__BITS(31,28)
 #define CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE			1
 #define CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN			2
 #define CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE __BITS(3,0)
 #define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM		0
 #define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ	8
 #define CAR_CLKSRC_HDA2CODEC_2X_REG	0x3e4
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC	__BITS(31,29)
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC2_OUT0	1
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC_OUT0	2
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC3_OUT0	3
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLM_OUT0	4
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_CLKM	6
 #define CAR_CLKSRC_HDA2CODEC_2X_DIV	__BITS(7,0)
 #define CAR_CLKSRC_SATA_OOB_REG		0x420
 #define CAR_CLKSRC_SATA_OOB_SRC		__BITS(31,29)
 #define CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_SATA_OOB_SRC_PLLC_OUT0	2
 #define CAR_CLKSRC_SATA_OOB_SRC_PLLM_OUT0	4
 #define CAR_CLKSRC_SATA_OOB_SRC_CLKM		6
 #define CAR_CLKSRC_SATA_OOB_DIV		__BITS(7,0)
 #define CAR_CLKSRC_SATA_REG		0x424
 #define CAR_CLKSRC_SATA_SRC		__BITS(31,29)
 #define CAR_CLKSRC_SATA_SRC_PLLP_OUT0		0
 #define CAR_CLKSRC_SATA_SRC_PLLC_OUT0		2
 #define CAR_CLKSRC_SATA_SRC_PLLM_OUT0		4
 @@ -452,14 +462,22 @@
 #define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
 #define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE	__BIT(5)
 #define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL		__BIT(4)
 #define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET	__BIT(2)
 #define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
 #define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL	__BIT(0)
 #define CAR_SATA_PLL_CFG1_REG		0x494
 #define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24)
 #define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16)
 #define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY	__BITS(15,8)
 #define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0)
 #define CAR_CLKSRC_HDMI_AUDIO_REG	0x668
 #define CAR_CLKSRC_HDMI_AUDIO_SRC	__BITS(31,29)
 #define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC_OUT0	1
 #define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC2_OUT0	2
 #define CAR_CLKSRC_HDMI_AUDIO_SRC_CLKM		3
 #define CAR_CLKSRC_HDMI_AUDIO_DIV	__BITS(7,0)
 #endif /* _ARM_TEGRA_CARREG_H */

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_hdmi.c,v 1.5 2015/07/23 15:43:06 jmcneill Exp $ */
+/* $NetBSD: tegra_hdmi.c,v 1.6 2015/07/25 15:50:42 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -19,27 +19,27 @@
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "locators.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_hdmi.c,v 1.5 2015/07/23 15:43:06 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_hdmi.c,v 1.6 2015/07/25 15:50:42 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <dev/i2c/i2cvar.h>
 #include <dev/i2c/ddcvar.h>
 #include <dev/videomode/videomode.h>
 #include <dev/videomode/edidvar.h>
 @@ -77,33 +77,38 @@ static const struct tegra_hdmi_tmds_conf
 struct tegra_hdmi_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	device_t		sc_displaydev;
 	device_t		sc_ddcdev;
 	struct tegra_gpio_pin	*sc_pin_hpd;
 	struct tegra_gpio_pin	*sc_pin_pll;
 	struct tegra_gpio_pin	*sc_pin_power;
 	bool			sc_connected;
 	const struct videomode	*sc_curmode;
 	bool			sc_hdmimode;
 };
 static void	tegra_hdmi_hpd(struct tegra_hdmi_softc *);
 static void	tegra_hdmi_connect(struct tegra_hdmi_softc *);
 static void	tegra_hdmi_disconnect(struct tegra_hdmi_softc *);
 static void	tegra_hdmi_enable(struct tegra_hdmi_softc *, const uint8_t *);
 static int	tegra_hdmi_sor_start(struct tegra_hdmi_softc *);
 static bool	tegra_hdmi_is_hdmi(struct tegra_hdmi_softc *,
 				   const struct edid_info *);
 static void	tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi_softc *);
 static uint8_t	tegra_hdmi_infoframe_csum(const uint8_t *, size_t);
 CFATTACH_DECL_NEW(tegra_hdmi, sizeof(struct tegra_hdmi_softc),
 	tegra_hdmi_match, tegra_hdmi_attach, NULL, NULL);
 #define HDMI_READ(sc, reg)			\
     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
 #define HDMI_WRITE(sc, reg, val)		\
     bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
 #define HDMI_SET_CLEAR(sc, reg, set, clr)	\
     tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
 static int
 tegra_hdmi_match(device_t parent, cfdata_t cf, void *aux)
 @@ -220,68 +225,74 @@ tegra_hdmi_connect(struct tegra_hdmi_sof
 				edid_print(&ei);
 #endif
 				pedid = edid;
+			}
+		}
+	}
 	mode = ei.edid_preferred_mode;
 	if (mode == NULL) {
 		mode = pick_mode_by_ref(640, 480, 60);
+	}
 	sc->sc_curmode = mode;
 	sc->sc_hdmimode = tegra_hdmi_is_hdmi(sc, &ei);
 device_printf(sc->sc_dev, "connected to %s display\n", sc->sc_hdmimode ? "HDMI" : "DVI");
 	if (sc->sc_hdmimode == false) {
 		device_printf(sc->sc_dev, "forcing HDMI mode\n");
 		sc->sc_hdmimode = true;
+	}
 	tegra_hdmi_enable(sc, pedid);
+}
 static void
 tegra_hdmi_disconnect(struct tegra_hdmi_softc *sc)
+{
+}
 static void
 tegra_hdmi_enable(struct tegra_hdmi_softc *sc, const uint8_t *edid)
+{
 	const struct tegra_hdmi_tmds_config *tmds = NULL;
 	const struct videomode *mode = sc->sc_curmode;
 	uint32_t input_ctrl;
-	u_int n;
+	u_int i;
 	KASSERT(sc->sc_curmode != NULL);
 	tegra_pmc_hdmi_enable();
 	tegra_car_hdmi_enable(mode->dot_clock * 1000);
-	for (n = 0; n < __arraycount(tegra_hdmi_tmds_config); n++) {
+	for (i = 0; i < __arraycount(tegra_hdmi_tmds_config); i++) {
-		if (tegra_hdmi_tmds_config[n].dot_clock >= mode->dot_clock) {
+		if (tegra_hdmi_tmds_config[i].dot_clock >= mode->dot_clock) {
 			break;
+		}
+	}
-	if (n < __arraycount(tegra_hdmi_tmds_config)) {
+	if (i < __arraycount(tegra_hdmi_tmds_config)) {
-		tmds = &tegra_hdmi_tmds_config[n];
+		tmds = &tegra_hdmi_tmds_config[i];
 	} else {
 		tmds = &tegra_hdmi_tmds_config[__arraycount(tegra_hdmi_tmds_config) - 1];
+	}
 	if (tmds != NULL) {
-		HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0);
+	HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0);
-		HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1);
+	HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1);
-		HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG,
+	HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG,
-		    tmds->sor_lane_drive_current);
+	    tmds->sor_lane_drive_current);
-		HDMI_WRITE(sc, HDMI_NV_PDISP_PE_CURRENT_REG, tmds->pe_current);
+	HDMI_WRITE(sc, HDMI_NV_PDISP_PE_CURRENT_REG, tmds->pe_current);
-		HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG,
+	HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG,
-		    tmds->sor_io_peak_current);
+	    tmds->sor_io_peak_current);
-		HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG,
+	HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG,
-		    tmds->sor_pad_ctls0);
+	    tmds->sor_pad_ctls0);
 	tegra_dc_enable(sc->sc_displaydev, sc->sc_dev, mode, edid);
 	const u_int div = (mode->dot_clock / 1000) * 4;
 	HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_REFCLK_REG,
 	    __SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) |
 	    __SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC));
 	HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_CSTM_REG,
 	    __SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS,
 		      HDMI_NV_PDISP_SOR_CSTM_MODE) |
 	    __SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) |
 	    HDMI_NV_PDISP_SOR_CSTM_PLLDIV,
 @@ -304,37 +315,77 @@ tegra_hdmi_enable(struct tegra_hdmi_soft
 	HDMI_WRITE(sc, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl);
 	if (tegra_hdmi_sor_start(sc) != 0)
 		return;
 	const u_int rekey = 56;
 	const u_int hspw = mode->hsync_end - mode->hsync_start;
 	const u_int hbp = mode->htotal - mode->hsync_end;
 	const u_int hfp = mode->hsync_start - mode->hdisplay;
 	const u_int max_ac_packet = (hspw + hbp + hfp - rekey - 18) / 32;
 	uint32_t ctrl =
 	    __SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) |
 	    __SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET);
-#if notyet
+	if (sc->sc_hdmimode) {
 	if (HDMI mode) {
 		ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */
+	}
 #endif
 	HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl);
-	/* XXX DVI */
+	if (sc->sc_hdmimode) {
-	HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0);
+		const u_int n = 6144;	/* 48 kHz */
-	HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0);
+		const u_int cts = ((mode->dot_clock * 10) * (n / 128)) / 480;
 	HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG,
 		    __SHIFTIN(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO,
 			      HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT) |
 		    HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_AUDIO_N_REG,
 		    HDMI_NV_PDISP_AUDIO_N_RESETF |
 		    HDMI_NV_PDISP_AUDIO_N_GENERATE |
 		    __SHIFTIN(n - 1, HDMI_NV_PDISP_AUDIO_N_VALUE));
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_SPARE_REG,
 		    HDMI_NV_PDISP_HDMI_SPARE_HW_CTS |
 		    HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS |
 		    __SHIFTIN(1, HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL));
 		/*
 		 * When HW_CTS=1 and FORCE_SW_CTS=1, the CTS is programmed by
 		 * software in the 44.1 kHz register regardless of chosen rate.
 		 */
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG,
 		    cts << 8);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG,
 x80000000 | n);
 		HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_AUDIO_N_REG, 0,
 		    HDMI_NV_PDISP_AUDIO_N_RESETF);
 		HDMI_WRITE(sc, 24000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG);
 		tegra_hdmi_setup_audio_infoframe(sc);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG,
 		    HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG,
 		    HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0);
 	} else {
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0);
 		HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0);
+	}
 	/* Start HDMI output */
 	tegra_dc_hdmi_start(sc->sc_displaydev);
+}
 static int
 tegra_hdmi_sor_start(struct tegra_hdmi_softc *sc)
+{
 	int retry;
 	HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_PLL0_REG,
 ,
 	    HDMI_NV_PDISP_SOR_PLL0_PWR |
 @@ -381,13 +432,109 @@ tegra_hdmi_sor_start(struct tegra_hdmi_s
 	HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE0_REG, 0);
 	HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE0_REG,
 	    HDMI_NV_PDISP_SOR_STATE0_UPDATE);
 	HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_STATE1_REG,
 	    HDMI_NV_PDISP_SOR_STATE1_ATTACHED, 0);
 	HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE0_REG, 0);
 	return 0;
+}
 static bool
 tegra_hdmi_is_hdmi(struct tegra_hdmi_softc *sc, const struct edid_info *ei)
+{
 	char edid[128];
 	bool found_hdmi = false;
 	unsigned int n, p;
 	/*
 	 * Scan through extension blocks, looking for a CEA-861-D v3
 	 * block. If an HDMI Vendor-Specific Data Block (HDMI VSDB) is
 	 * found in that, assume HDMI mode.
 	 */
 	for (n = 1; n <= MIN(ei->edid_ext_block_count, 4); n++) {
 		if (ddc_dev_read_edid_block(sc->sc_ddcdev, edid,
 		    sizeof(edid), n)) {
 			break;
+		}
 		const uint8_t tag = edid[0];
 		const uint8_t rev = edid[1];
 		const uint8_t off = edid[2];
 		/* We are looking for a CEA-861-D tag (02h) with revision 3 */
 		if (tag != 0x02 || rev != 3)
 			continue;
 		/*
 		 * CEA data block collection starts at byte 4, so the
 		 * DTD blocks must start after it.
 		 */
 		if (off <= 4)
 			continue;
 		/* Parse the CEA data blocks */
 		for (p = 4; p < off;) {
 			const uint8_t btag = (edid[p] >> 5) & 0x7;
 			const uint8_t blen = edid[p] & 0x1f;
 			/* Make sure the length is sane */
 			if (p + blen + 1 > off)
 				break;
 			/* Looking for a VSDB tag */
 			if (btag != 3)
 				goto next_block;
 			/* HDMI VSDB is at least 5 bytes long */
 			if (blen < 5)
 				goto next_block;
 			/* HDMI 24-bit IEEE registration ID is 0x000C03 */
 			if (memcmp(&edid[p + 1], "\x03\x0c\x00", 3) == 0)
 				found_hdmi = true;
 next_block:
 			p += (1 + blen);
+		}
+	}
 	return found_hdmi;
+}
 static void
 tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi_softc *sc)
+{
 	uint8_t data[10] = {
 x84, 0x01, 0x10,
 x00,	/* PB0 (checksum) */
 x01,	/* CT=0, CC=2ch */
 xc0,	/* SS=0, SF=48kHz */
 x00,	/* CA=FR/FL */
 x00,	/* LSV=0dB, DM_INH=permitted */
 x00, 0x00
 	};
 	data[3] = tegra_hdmi_infoframe_csum(data, sizeof(data));
 	HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG,
 	    data[0] | (data[1] << 8) | (data[2] << 16));
 	HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG,
 	    data[3] | (data[4] << 8) | (data[5] << 16) | (data[6] << 24));
 	HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG,
 	    data[7] | (data[8] << 8) | (data[9] << 16));
+}
 static uint8_t
 tegra_hdmi_infoframe_csum(const uint8_t *data, size_t len)
+{
 	uint8_t csum = 0;
 	u_int n;
 	for (n = 0; n < len; n++)
 		csum += data[n];
 	if (csum)
 		csum = 0x100 - csum;
 	return csum;
+}

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_hdmireg.h,v 1.3 2015/07/23 15:08:19 skrll Exp $ */
+/* $NetBSD: tegra_hdmireg.h,v 1.4 2015/07/25 15:50:42 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -49,39 +49,58 @@
 #define HDMI_NV_PDISP_SOR_STATE2_REG				0x00c
 #define HDMI_NV_PDISP_SOR_STATE2_ASY_DEPOL			__BIT(14)
 #define HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL			__BIT(13)
 #define HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL			__BIT(12)
 #define HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL			__BITS(11,8)
 #define HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE			__BITS(7,6)
 #define HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER			__BITS(5,4)
 #define HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER			__BITS(3,0)
 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU0_REG			0x068
 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0_REG			0x06c
 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU1_REG			0x070
 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU2_REG			0x074
 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG		0x078
 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_CHKSUM_HW	__BIT(9)
 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_SINGLE		__BIT(8)
 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_OTHER		__BIT(4)
 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE		__BIT(0)
 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS_REG		0x07c
 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG		0x080
 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG	0x084
 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG	0x088
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG		0x08c
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW	__BIT(9)
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_SINGLE		__BIT(8)
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_OTHER		__BIT(4)
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE		__BIT(0)
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS_REG		0x090
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG		0x094
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG	0x098
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG	0x09c
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG	0x0a0
 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG	0x0a4
 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG			0x0a8
 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO			__BIT(16)
 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_HBLANK			__BIT(12)
 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_SINGLE			__BIT(8)
 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_OTHER			__BIT(4)
 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_ENABLE			__BIT(0)
 #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS_REG			0x0ac
 #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER_REG			0x0b0
 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK0_LOW_REG	0x0b4
 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK0_HIGH_REG	0x0b8
 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK1_LOW_REG	0x0bc
 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK1_HIGH_REG	0x0c0
 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK2_LOW_REG	0x0c4
 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK2_HIGH_REG	0x0c8
 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK3_LOW_REG	0x0cc
 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK3_HIGH_REG	0x0d0
 #define HDMI_NV_PDISP_HDMI_ACR_CTRL_REG				0x0d4
 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW_REG		0x0d8
 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH_REG		0x0dc
 @@ -111,27 +130,32 @@
 #define HDMI_NV_PDISP_HDMI_CTRL_AUDIO_LAYOUT			__BIT(8)
 #define HDMI_NV_PDISP_HDMI_CTRL_REKEY				__BITS(6,0)
 #define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT_REG			0x114
 #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW_REG			0x118
 #define HDMI_NV_PDISP_HDMI_GCP_CTRL_REG				0x11c
 #define HDMI_NV_PDISP_HDMI_GCP_STATUS_REG			0x120
 #define HDMI_NV_PDISP_HDMI_GCP_SUBPACK_REG			0x124
 #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1_REG			0x128
 #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2_REG			0x12c
 #define HDMI_NV_PDISP_HDMI_EMU0_REG				0x130
 #define HDMI_NV_PDISP_HDMI_EMU1_REG				0x134
 #define HDMI_NV_PDISP_HDMI_EMU1_RDATA_REG			0x138
 #define HDMI_NV_PDISP_HDMI_SPARE_REG				0x13c
 #define HDMI_NV_PDISP_HDMI_SPARE_HW_CTS				__BIT(0)
 #define HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS			__BIT(1)
 #define HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL			__BITS(18,16)
 #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1_REG		0x140
 #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STAUTS2_REG		0x144
 #define HDMI_NV_PDISP_CRC_CONTROL_REG				0x258
 #define HDMI_NV_PDISP_INPUT_CONTROL_REG				0x25c
 #define HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE		__BIT(1)
 #define HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT		__BIT(0)
 #define HDMI_NV_PDISP_SCRATCH_REG				0x260
 #define HDMI_NV_PDISP_PE_CURRENT_REG				0x264
 #define HDMI_NV_PDISP_KEY_CTRL_REG				0x268
 #define HDMI_NV_PDISP_KEY_DEBUG0_REG				0x26c
 #define HDMI_NV_PDISP_KEY_DEBUG1_REG				0x270
 @@ -261,27 +285,50 @@
 #define HDMI_NV_PDISP_SOR_REFCLK_REG				0x254
 #define HDMI_NV_PDISP_SOR_REFCLK_DIV_INT			__BITS(15,8)
 #define HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC			__BITS(7,6)
 #define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG			0x344
 #define HDMI_NV_PDISP_SOR_PAD_CTLS0_REG				0x348
 #define HDMI_NV_PDISP_SOR_PAD_CTLS1_REG				0x34c
 /*
  * Audio Registers
  */
 #define HDMI_NV_PDISP_AUDIO_N_REG				0x230
 #define HDMI_NV_PDISP_AUDIO_N_LOOKUP				__BIT(28)
 #define HDMI_NV_PDISP_AUDIO_N_GENERATE				__BIT(24)
 #define HDMI_NV_PDISP_AUDIO_N_RESETF				__BIT(20)
 #define HDMI_NV_PDISP_AUDIO_N_VALUE				__BITS(19,0)
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG			0x2b0
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INPUT_MODE		__BIT(31)
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL		__BIT(29)
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT		__BITS(21,20)
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO	0
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF	1
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL	2
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ		__BITS(19,16)
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_32_0KHZ	3
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_44_1KHZ	0
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_88_2KHZ	8
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_176_4KHZ	12
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_48_0KHZ	2
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_96_0KHZ	10
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_192_0KHZ	14
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_UNKNOWN	1
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_AFIFO_FLUSH		__BIT(12)
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_PORT_CONNECTIVITY	__BIT(0)
 #define HDMI_NV_PDISP_SOR_AUDIO_DEBUG_REG			0x2b4
 #define HDMI_NV_PDISP_SOR_AUDIO_SPARE0_REG			0x2b8
 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0320_REG			0x2bc
 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0441_REG			0x2c0
 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0882_REG			0x2c4
 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1764_REG			0x2c8
 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0480_REG			0x2cc
 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0960_REG			0x2d0
 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1920_REG			0x2d4
 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_REG		0x2d8
 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_REG		0x2dc
 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_REG		0x2e0
 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_REG		0x2e4