Sat Oct 17 21:14:49 2015 UTC ()
GPU power is controlled by a different register on Tegra124, handle this in tegra_pmc_remove_clamping


(jmcneill)
diff -r1.6 -r1.7 src/sys/arch/arm/nvidia/tegra_pmc.c
diff -r1.4 -r1.5 src/sys/arch/arm/nvidia/tegra_pmcreg.h
cvs diff -r1.6 -r1.7 src/sys/arch/arm/nvidia/tegra_pmc.c (expand / switch to unified diff)

--- src/sys/arch/arm/nvidia/tegra_pmc.c 2015/05/25 10:40:23 1.6
+++ src/sys/arch/arm/nvidia/tegra_pmc.c 2015/10/17 21:14:49 1.7
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: tegra_pmc.c,v 1.6 2015/05/25 10:40:23 jmcneill Exp $ */ 1/* $NetBSD: tegra_pmc.c,v 1.7 2015/10/17 21:14:49 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -19,27 +19,27 @@ @@ -19,27 +19,27 @@
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#include "locators.h" 29#include "locators.h"
30 30
31#include <sys/cdefs.h> 31#include <sys/cdefs.h>
32__KERNEL_RCSID(0, "$NetBSD: tegra_pmc.c,v 1.6 2015/05/25 10:40:23 jmcneill Exp $"); 32__KERNEL_RCSID(0, "$NetBSD: tegra_pmc.c,v 1.7 2015/10/17 21:14:49 jmcneill Exp $");
33 33
34#include <sys/param.h> 34#include <sys/param.h>
35#include <sys/bus.h> 35#include <sys/bus.h>
36#include <sys/device.h> 36#include <sys/device.h>
37#include <sys/intr.h> 37#include <sys/intr.h>
38#include <sys/systm.h> 38#include <sys/systm.h>
39#include <sys/kernel.h> 39#include <sys/kernel.h>
40 40
41#include <arm/nvidia/tegra_reg.h> 41#include <arm/nvidia/tegra_reg.h>
42#include <arm/nvidia/tegra_pmcreg.h> 42#include <arm/nvidia/tegra_pmcreg.h>
43#include <arm/nvidia/tegra_var.h> 43#include <arm/nvidia/tegra_var.h>
44 44
45static int tegra_pmc_match(device_t, cfdata_t, void *); 45static int tegra_pmc_match(device_t, cfdata_t, void *);
@@ -142,26 +142,35 @@ tegra_pmc_power(u_int partid, bool enabl @@ -142,26 +142,35 @@ tegra_pmc_power(u_int partid, bool enabl
142 bus_space_write_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG, 142 bus_space_write_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG,
143 __SHIFTIN(partid, PMC_PWRGATE_TOGGLE_0_PARTID) | 143 __SHIFTIN(partid, PMC_PWRGATE_TOGGLE_0_PARTID) |
144 PMC_PWRGATE_TOGGLE_0_START); 144 PMC_PWRGATE_TOGGLE_0_START);
145} 145}
146 146
147void 147void
148tegra_pmc_remove_clamping(u_int partid) 148tegra_pmc_remove_clamping(u_int partid)
149{ 149{
150 bus_space_tag_t bst; 150 bus_space_tag_t bst;
151 bus_space_handle_t bsh; 151 bus_space_handle_t bsh;
152 152
153 tegra_pmc_get_bs(&bst, &bsh); 153 tegra_pmc_get_bs(&bst, &bsh);
154 154
 155 if (tegra_chip_id() == CHIP_ID_TEGRA124) {
 156 /*
 157 * On Tegra124 the GPU power clamping is controlled by a
 158 * separate register
 159 */
 160 bus_space_write_4(bst, bsh, PMC_GPU_RG_CNTRL_REG, 0);
 161 return;
 162 }
 163
155 bus_space_write_4(bst, bsh, PMC_REMOVE_CLAMPING_CMD_0_REG, 164 bus_space_write_4(bst, bsh, PMC_REMOVE_CLAMPING_CMD_0_REG,
156 __BIT(partid)); 165 __BIT(partid));
157} 166}
158 167
159void 168void
160tegra_pmc_hdmi_enable(void) 169tegra_pmc_hdmi_enable(void)
161{ 170{
162 bus_space_tag_t bst; 171 bus_space_tag_t bst;
163 bus_space_handle_t bsh; 172 bus_space_handle_t bsh;
164 173
165 tegra_pmc_get_bs(&bst, &bsh); 174 tegra_pmc_get_bs(&bst, &bsh);
166 175
167 tegra_reg_set_clear(bst, bsh, PMC_IO_DPD_STATUS_REG, 176 tegra_reg_set_clear(bst, bsh, PMC_IO_DPD_STATUS_REG,
cvs diff -r1.4 -r1.5 src/sys/arch/arm/nvidia/tegra_pmcreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/nvidia/tegra_pmcreg.h 2015/05/18 21:03:36 1.4
+++ src/sys/arch/arm/nvidia/tegra_pmcreg.h 2015/10/17 21:14:49 1.5
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: tegra_pmcreg.h,v 1.4 2015/05/18 21:03:36 jmcneill Exp $ */ 1/* $NetBSD: tegra_pmcreg.h,v 1.5 2015/10/17 21:14:49 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -83,14 +83,17 @@ @@ -83,14 +83,17 @@
83#define PMC_PARTID_L2C 5 83#define PMC_PARTID_L2C 5
84#define PMC_PARTID_VDE 4 84#define PMC_PARTID_VDE 4
85#define PMC_PARTID_PCX 3 85#define PMC_PARTID_PCX 3
86#define PMC_PARTID_VE 2 86#define PMC_PARTID_VE 2
87#define PMC_PARTID_TD 1 87#define PMC_PARTID_TD 1
88#define PMC_PARTID_CPU0 0 88#define PMC_PARTID_CPU0 0
89 89
90#define PMC_IO_DPD_STATUS_REG 0x1bc 90#define PMC_IO_DPD_STATUS_REG 0x1bc
91#define PMC_IO_DPD_STATUS_HDMI __BIT(28) 91#define PMC_IO_DPD_STATUS_HDMI __BIT(28)
92 92
93#define PMC_IO_DPD2_STATUS_REG 0x1c4 93#define PMC_IO_DPD2_STATUS_REG 0x1c4
94#define PMC_IO_DPD2_STATUS_HV __BIT(6) 94#define PMC_IO_DPD2_STATUS_HV __BIT(6)
95 95
 96#define PMC_GPU_RG_CNTRL_REG 0x2d4
 97#define PMC_GPU_RG_CNTRL_RAIL_CLAMP __BIT(0)
 98
96#endif /* _ARM_TEGRA_PMCREG_H */ 99#endif /* _ARM_TEGRA_PMCREG_H */