Sat Mar 26 09:07:31 2016 UTC ()
Restore HOST1X and AHB_A2 to pmap_devmap to give pmap less work to do


(skrll)
diff -r1.20 -r1.21 src/sys/arch/arm/nvidia/tegra_reg.h
diff -r1.8 -r1.9 src/sys/arch/arm/nvidia/tegra_soc.c
diff -r1.37 -r1.38 src/sys/arch/evbarm/tegra/tegra_machdep.c

cvs diff -r1.20 -r1.21 src/sys/arch/arm/nvidia/tegra_reg.h (expand / switch to context diff)
--- src/sys/arch/arm/nvidia/tegra_reg.h 2015/11/21 22:55:32 1.20
+++ src/sys/arch/arm/nvidia/tegra_reg.h 2016/03/26 09:07:31 1.21
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_reg.h,v 1.20 2015/11/21 22:55:32 jmcneill Exp $ */
+/* $NetBSD: tegra_reg.h,v 1.21 2016/03/26 09:07:31 skrll Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@@ -72,8 +72,10 @@
 #define TEGRA_AHB_A2_BASE	0x7c000000
 #define TEGRA_AHB_A2_SIZE	0x02000000
 
-#define TEGRA_PPSB_VBASE	0xfd000000
-#define TEGRA_APB_VBASE		0xfe000000
+#define TEGRA_HOST1X_VBASE	0xfaf00000
+#define TEGRA_PPSB_VBASE	0xfb000000
+#define TEGRA_APB_VBASE		0xfc000000
+#define TEGRA_AHB_A2_VBASE	0xfd000000
 
 #define TEGRA_REF_FREQ		12000000
 

cvs diff -r1.8 -r1.9 src/sys/arch/arm/nvidia/tegra_soc.c (expand / switch to context diff)
--- src/sys/arch/arm/nvidia/tegra_soc.c 2015/12/22 22:10:36 1.8
+++ src/sys/arch/arm/nvidia/tegra_soc.c 2016/03/26 09:07:31 1.9
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_soc.c,v 1.8 2015/12/22 22:10:36 jmcneill Exp $ */
+/* $NetBSD: tegra_soc.c,v 1.9 2016/03/26 09:07:31 skrll Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@@ -30,7 +30,7 @@
 #include "opt_multiprocessor.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.8 2015/12/22 22:10:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.9 2016/03/26 09:07:31 skrll Exp $");
 
 #define	_ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
@@ -48,8 +48,10 @@
 #include <arm/nvidia/tegra_mcreg.h>
 #include <arm/nvidia/tegra_var.h>
 
+bus_space_handle_t tegra_host1x_bsh;
 bus_space_handle_t tegra_ppsb_bsh;
 bus_space_handle_t tegra_apb_bsh;
+bus_space_handle_t tegra_ahb_a2_bsh;
 
 struct arm32_bus_dma_tag tegra_dma_tag = {
 	_BUS_DMAMAP_FUNCS,
@@ -63,6 +65,10 @@
 tegra_bootstrap(void)
 {
 	if (bus_space_map(&armv7_generic_bs_tag,
+	    TEGRA_HOST1X_BASE, TEGRA_HOST1X_SIZE, 0,
+	    &tegra_host1x_bsh) != 0)
+		panic("couldn't map HOST1X");
+	if (bus_space_map(&armv7_generic_bs_tag,
 	    TEGRA_PPSB_BASE, TEGRA_PPSB_SIZE, 0,
 	    &tegra_ppsb_bsh) != 0)
 		panic("couldn't map PPSB");
@@ -70,6 +76,10 @@
 	    TEGRA_APB_BASE, TEGRA_APB_SIZE, 0,
 	    &tegra_apb_bsh) != 0)
 		panic("couldn't map APB");
+	if (bus_space_map(&armv7_generic_bs_tag,
+	    TEGRA_AHB_A2_BASE, TEGRA_AHB_A2_SIZE, 0,
+	    &tegra_ahb_a2_bsh) != 0)
+		panic("couldn't map AHB A2");
 
 	tegra_mpinit();
 }

cvs diff -r1.37 -r1.38 src/sys/arch/evbarm/tegra/Attic/tegra_machdep.c (expand / switch to context diff)
--- src/sys/arch/evbarm/tegra/Attic/tegra_machdep.c 2015/12/22 22:10:36 1.37
+++ src/sys/arch/evbarm/tegra/Attic/tegra_machdep.c 2016/03/26 09:07:31 1.38
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_machdep.c,v 1.37 2015/12/22 22:10:36 jmcneill Exp $ */
+/* $NetBSD: tegra_machdep.c,v 1.38 2016/03/26 09:07:31 skrll Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_machdep.c,v 1.37 2015/12/22 22:10:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_machdep.c,v 1.38 2016/03/26 09:07:31 skrll Exp $");
 
 #include "opt_tegra.h"
 #include "opt_machdep.h"
@@ -122,6 +122,13 @@
 
 static const struct pmap_devmap devmap[] = {
 	{
+		.pd_va = _A(TEGRA_HOST1X_VBASE),
+		.pd_pa = _A(TEGRA_HOST1X_BASE),
+		.pd_size = _S(TEGRA_HOST1X_SIZE),
+		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
+		.pd_cache = PTE_NOCACHE
+	},
+	{
 		.pd_va = _A(TEGRA_PPSB_VBASE),
 		.pd_pa = _A(TEGRA_PPSB_BASE),
 		.pd_size = _S(TEGRA_PPSB_SIZE),
@@ -132,6 +139,13 @@
 		.pd_va = _A(TEGRA_APB_VBASE),
 		.pd_pa = _A(TEGRA_APB_BASE),
 		.pd_size = _S(TEGRA_APB_SIZE),
+		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
+		.pd_cache = PTE_NOCACHE
+	},
+	{
+		.pd_va = _A(TEGRA_AHB_A2_VBASE),
+		.pd_pa = _A(TEGRA_AHB_A2_BASE),
+		.pd_size = _S(TEGRA_AHB_A2_SIZE),
 		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
 		.pd_cache = PTE_NOCACHE
 	},