Get the EXYNOS kernel building again with recent FDT changes. Untested.diff -r1.1 -r0 src/sys/arch/arm/samsung/exynos5422_dma.c
(jmcneill)
--- src/sys/arch/arm/samsung/exynos_intr.h 2014/09/05 08:01:05 1.2
+++ src/sys/arch/arm/samsung/exynos_intr.h 2017/06/10 15:13:18 1.3
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: exynos_intr.h,v 1.2 2014/09/05 08:01:05 skrll Exp $ */ | 1 | /* $NetBSD: exynos_intr.h,v 1.3 2017/06/10 15:13:18 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /*- | 3 | /*- | |
4 | * Copyright (c) 2014 The NetBSD Foundation, Inc. | 4 | * Copyright (c) 2014 The NetBSD Foundation, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * This code is derived from software contributed to The NetBSD Foundation | 7 | * This code is derived from software contributed to The NetBSD Foundation | |
8 | * by Nick Hudson | 8 | * by Nick Hudson | |
9 | * | 9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | 10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | 11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | 12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | 13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer. | 14 | * notice, this list of conditions and the following disclaimer. | |
@@ -22,48 +22,32 @@ | @@ -22,48 +22,32 @@ | |||
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
29 | * POSSIBILITY OF SUCH DAMAGE. | 29 | * POSSIBILITY OF SUCH DAMAGE. | |
30 | */ | 30 | */ | |
31 | 31 | |||
32 | #ifndef _ARM_SAMSUNG_EXYNOS_INTR_H_ | 32 | #ifndef _ARM_SAMSUNG_EXYNOS_INTR_H_ | |
33 | #define _ARM_SAMSUNG_EXYNOS_INTR_H_ | 33 | #define _ARM_SAMSUNG_EXYNOS_INTR_H_ | |
34 | 34 | |||
35 | #define PIC_MAXSOURCES GIC_MAXSOURCES(224) | |||
36 | #define PIC_MAXMAXSOURCES (PIC_MAXSOURCES + 32) /* XXX */ | |||
37 | ||||
38 | /* | |||
39 | * The Exynos uses a generic interrupt controller | |||
40 | */ | |||
41 | #include <arm/cortex/gic_intr.h> | |||
42 | ||||
43 | #ifdef _KERNEL_OPT | |||
44 | #include "opt_exynos.h" | |||
45 | #endif | |||
46 | ||||
47 | /* | 35 | /* | |
48 | * The GIC supports | 36 | * The GIC supports | |
49 | * - 16 Software Generated Interrupts (SGIs) | 37 | * - 16 Software Generated Interrupts (SGIs) | |
50 | * - 16 Private Peripheral Interrupts (PPIs) | 38 | * - 16 Private Peripheral Interrupts (PPIs) | |
51 | * - 127 Shared Peripheral Interrupts (SPIs) | 39 | * - 127 Shared Peripheral Interrupts (SPIs) | |
52 | */ | 40 | */ | |
53 | 41 | |||
54 | #define EXYNOS_NSPI 128 | 42 | #define EXYNOS_NSPI 128 | |
55 | #define EXYNOS_COMBINERBASE EXYNOS_SPIBASE + EXYNOS_NSPI | 43 | #define EXYNOS_COMBINERBASE EXYNOS_SPIBASE + EXYNOS_NSPI | |
56 | 44 | |||
57 | #define EXYNOS_BITSPERGROUP 8 | 45 | #define EXYNOS_BITSPERGROUP 8 | |
58 | 46 | |||
59 | #define EXYNOS_COMBINERIRQ(g, b) \ | 47 | #define EXYNOS_COMBINERIRQ(g, b) \ | |
60 | (EXYNOS_COMBINERBASE + ((g) * EXYNOS_BITSPERGROUP + (b))) | 48 | (EXYNOS_COMBINERBASE + ((g) * EXYNOS_BITSPERGROUP + (b))) | |
61 | 49 | |||
62 | #define IRQ_MCT_LTIMER IRQ_PPI(12) | 50 | #define IRQ_MCT_LTIMER IRQ_PPI(12) | |
63 | 51 | |||
64 | #ifdef EXYNOS5 | |||
65 | #include <arm/cortex/gtmr_intr.h> | |||
66 | #endif | |||
67 | ||||
68 | #endif /* _ARM_SAMSUNG_EXYNOS_INTR_H_ */ | 52 | #endif /* _ARM_SAMSUNG_EXYNOS_INTR_H_ */ | |
69 | 53 |
/* $NetBSD: exynos_platform.c,v 1.1 2017/06/10 15:13:18 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "opt_exynos.h"
#include "opt_multiprocessor.h"
#include "opt_fdt_arm.h"
#include "ukbd.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.1 2017/06/10 15:13:18 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/cpu.h>
#include <sys/device.h>
#include <sys/termios.h>
#include <dev/fdt/fdtvar.h>
#include <uvm/uvm_extern.h>
#include <machine/bootconfig.h>
#include <arm/cpufunc.h>
#include <arm/samsung/exynos_reg.h>
#include <arm/samsung/exynos_var.h>
#include <arm/cortex/gtmr_var.h>
#include <arm/fdt/arm_fdtvar.h>
#define EXYNOS_CORE_VBASE 0xf0000000
#define DEVMAP_ALIGN(a) ((a) & ~L1_S_OFFSET)
#define DEVMAP_SIZE(s) roundup2((s), L1_S_SIZE)
#define DEVMAP_ENTRY(va, pa, sz) \
{ \
.pd_va = DEVMAP_ALIGN(va), \
.pd_pa = DEVMAP_ALIGN(pa), \
.pd_size = DEVMAP_SIZE(sz), \
.pd_prot = VM_PROT_READ|VM_PROT_WRITE, \
.pd_cache = PTE_NOCACHE \
}
#define DEVMAP_ENTRY_END { 0 }
static const struct pmap_devmap *
exynos_platform_devmap(void)
{
static const struct pmap_devmap devmap[] = {
DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
EXYNOS_CORE_PBASE,
EXYNOS_CORE_SIZE),
DEVMAP_ENTRY_END
};
return devmap;
}
static void
exynos_platform_bootstrap(void)
{
exynos_bootstrap(EXYNOS_CORE_PBASE, 0 /* XXX */);
}
static void
exynos_platform_init_attach_args(struct fdt_attach_args *faa)
{
extern struct bus_space armv7_generic_bs_tag;
extern struct bus_space armv7_generic_a4x_bs_tag;
extern struct arm32_bus_dma_tag armv7_generic_dma_tag;
faa->faa_bst = &armv7_generic_bs_tag;
faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
faa->faa_dmat = &armv7_generic_dma_tag;
}
static void
exynos_platform_early_putchar(char c)
{
}
static void
exynos_platform_device_register(device_t self, void *aux)
{
exynos_device_register(self, aux);
}
static void
exynos_platform_reset(void)
{
printf("%s: not implemented\n", __func__);
}
static void
exynos_platform_delay(u_int us)
{
gtmr_delay(us);
}
static u_int
exynos_platform_uart_freq(void)
{
return EXYNOS_UART_FREQ;
}
static const struct arm_platform exynos5_platform = {
.devmap = exynos_platform_devmap,
.bootstrap = exynos_platform_bootstrap,
.init_attach_args = exynos_platform_init_attach_args,
.early_putchar = exynos_platform_early_putchar,
.device_register = exynos_platform_device_register,
.reset = exynos_platform_reset,
.delay = exynos_platform_delay,
.uart_freq = exynos_platform_uart_freq,
};
ARM_PLATFORM(exynos5, "samsung,exynos5", &exynos5_platform);
--- src/sys/arch/arm/samsung/exynos_reg.h 2014/09/30 14:20:55 1.13
+++ src/sys/arch/arm/samsung/exynos_reg.h 2017/06/10 15:13:18 1.14
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: exynos_reg.h,v 1.13 2014/09/30 14:20:55 reinoud Exp $ */ | 1 | /* $NetBSD: exynos_reg.h,v 1.14 2017/06/10 15:13:18 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /*- | 3 | /*- | |
4 | * Copyright (c) 2014 The NetBSD Foundation, Inc. | 4 | * Copyright (c) 2014 The NetBSD Foundation, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * This code is derived from software contributed to The NetBSD Foundation | 7 | * This code is derived from software contributed to The NetBSD Foundation | |
8 | * by Reinoud Zandijk. | 8 | * by Reinoud Zandijk. | |
9 | * | 9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | 10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | 11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | 12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | 13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer. | 14 | * notice, this list of conditions and the following disclaimer. | |
@@ -87,30 +87,30 @@ | @@ -87,30 +87,30 @@ | |||
87 | #define EXYNOS_CORE_SIZE 0x10000000 | 87 | #define EXYNOS_CORE_SIZE 0x10000000 | |
88 | 88 | |||
89 | 89 | |||
90 | #define EXYNOS_CHIPID_OFFSET 0x00000000 | 90 | #define EXYNOS_CHIPID_OFFSET 0x00000000 | |
91 | #define EXYNOS_PROD_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 0) | 91 | #define EXYNOS_PROD_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 0) | |
92 | #define EXYNOS_PACKAGE_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 4) | 92 | #define EXYNOS_PACKAGE_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 4) | |
93 | 93 | |||
94 | #define EXYNOS_PACKAGE_ID_2_GIG 0x06030058 | 94 | #define EXYNOS_PACKAGE_ID_2_GIG 0x06030058 | |
95 | 95 | |||
96 | /* standard block size for offsets defined below */ | 96 | /* standard block size for offsets defined below */ | |
97 | #define EXYNOS_BLOCK_SIZE 0x00010000 | 97 | #define EXYNOS_BLOCK_SIZE 0x00010000 | |
98 | 98 | |||
99 | 99 | |||
100 | #if defined(EXYNOS5) | 100 | #if defined(SOC_EXYNOS5) | |
101 | #include <arm/samsung/exynos5_reg.h> | 101 | #include <arm/samsung/exynos5_reg.h> | |
102 | #endif | 102 | #endif | |
103 | #if defined(EXYNOS4) | 103 | #if defined(SOC_EXYNOS4) | |
104 | #include <arm/samsung/exynos4_reg.h> | 104 | #include <arm/samsung/exynos4_reg.h> | |
105 | #endif | 105 | #endif | |
106 | 106 | |||
107 | 107 | |||
108 | /* standard frequency settings */ | 108 | /* standard frequency settings */ | |
109 | #define EXYNOS_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */ | 109 | #define EXYNOS_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */ | |
110 | #define EXYNOS_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */ | 110 | #define EXYNOS_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */ | |
111 | 111 | |||
112 | #define EXYNOS_F_IN_FREQ (24*1000*1000) /* 24 Mhz */ | 112 | #define EXYNOS_F_IN_FREQ (24*1000*1000) /* 24 Mhz */ | |
113 | #define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */ | 113 | #define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */ | |
114 | 114 | |||
115 | 115 | |||
116 | /* PLLs */ | 116 | /* PLLs */ |
--- src/sys/arch/arm/samsung/exynos_soc.c 2015/12/21 04:58:50 1.31
+++ src/sys/arch/arm/samsung/exynos_soc.c 2017/06/10 15:13:18 1.32
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: exynos_soc.c,v 1.31 2015/12/21 04:58:50 marty Exp $ */ | 1 | /* $NetBSD: exynos_soc.c,v 1.32 2017/06/10 15:13:18 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /*- | 3 | /*- | |
4 | * Copyright (c) 2014 The NetBSD Foundation, Inc. | 4 | * Copyright (c) 2014 The NetBSD Foundation, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * This code is derived from software contributed to The NetBSD Foundation | 7 | * This code is derived from software contributed to The NetBSD Foundation | |
8 | * by Reinoud Zandijk. | 8 | * by Reinoud Zandijk. | |
9 | * | 9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | 10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | 11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | 12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | 13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer. | 14 | * notice, this list of conditions and the following disclaimer. | |
@@ -21,30 +21,28 @@ | @@ -21,30 +21,28 @@ | |||
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
29 | * POSSIBILITY OF SUCH DAMAGE. | 29 | * POSSIBILITY OF SUCH DAMAGE. | |
30 | */ | 30 | */ | |
31 | 31 | |||
32 | #include "opt_exynos.h" | 32 | #include "opt_exynos.h" | |
33 | 33 | |||
34 | #define _ARM32_BUS_DMA_PRIVATE | |||
35 | ||||
36 | #include <sys/cdefs.h> | 34 | #include <sys/cdefs.h> | |
37 | __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.31 2015/12/21 04:58:50 marty Exp $"); | 35 | __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.32 2017/06/10 15:13:18 jmcneill Exp $"); | |
38 | 36 | |||
39 | #include <sys/param.h> | 37 | #include <sys/param.h> | |
40 | #include <sys/bus.h> | 38 | #include <sys/bus.h> | |
41 | #include <sys/cpu.h> | 39 | #include <sys/cpu.h> | |
42 | #include <sys/device.h> | 40 | #include <sys/device.h> | |
43 | 41 | |||
44 | #include <prop/proplib.h> | 42 | #include <prop/proplib.h> | |
45 | 43 | |||
46 | #include <net/if.h> | 44 | #include <net/if.h> | |
47 | #include <net/if_ether.h> | 45 | #include <net/if_ether.h> | |
48 | 46 | |||
49 | #include <arm/locore.h> | 47 | #include <arm/locore.h> | |
50 | 48 | |||
@@ -66,51 +64,51 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c | @@ -66,51 +64,51 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c | |||
66 | /* these variables are retrieved in start.S and stored in .data */ | 64 | /* these variables are retrieved in start.S and stored in .data */ | |
67 | uint32_t exynos_soc_id = 0; | 65 | uint32_t exynos_soc_id = 0; | |
68 | uint32_t exynos_pop_id = 0; | 66 | uint32_t exynos_pop_id = 0; | |
69 | 67 | |||
70 | /* cpu frequencies */ | 68 | /* cpu frequencies */ | |
71 | struct cpu_freq { | 69 | struct cpu_freq { | |
72 | uint64_t freq; | 70 | uint64_t freq; | |
73 | int P; | 71 | int P; | |
74 | int M; | 72 | int M; | |
75 | int S; | 73 | int S; | |
76 | }; | 74 | }; | |
77 | 75 | |||
78 | 76 | |||
79 | #ifdef EXYNOS4 | 77 | #ifdef SOC_EXYNOS4 | |
80 | const struct cpu_freq cpu_freq_settings_exynos4[] = { | 78 | const struct cpu_freq cpu_freq_settings_exynos4[] = { | |
81 | { 200, 3, 100, 2}, | 79 | { 200, 3, 100, 2}, | |
82 | { 300, 4, 200, 2}, | 80 | { 300, 4, 200, 2}, | |
83 | { 400, 3, 100, 1}, | 81 | { 400, 3, 100, 1}, | |
84 | { 500, 3, 125, 1}, | 82 | { 500, 3, 125, 1}, | |
85 | { 600, 4, 200, 1}, | 83 | { 600, 4, 200, 1}, | |
86 | { 700, 3, 175, 1}, | 84 | { 700, 3, 175, 1}, | |
87 | { 800, 3, 100, 0}, | 85 | { 800, 3, 100, 0}, | |
88 | { 900, 4, 150, 0}, | 86 | { 900, 4, 150, 0}, | |
89 | {1000, 3, 125, 0}, | 87 | {1000, 3, 125, 0}, | |
90 | {1100, 6, 275, 0}, | 88 | {1100, 6, 275, 0}, | |
91 | {1200, 4, 200, 0}, | 89 | {1200, 4, 200, 0}, | |
92 | {1300, 6, 325, 0}, | 90 | {1300, 6, 325, 0}, | |
93 | {1400, 3, 175, 0}, | 91 | {1400, 3, 175, 0}, | |
94 | {1600, 3, 200, 0}, | 92 | {1600, 3, 200, 0}, | |
95 | // {1704, 3, 213, 0}, | 93 | // {1704, 3, 213, 0}, | |
96 | // {1800, 4, 300, 0}, | 94 | // {1800, 4, 300, 0}, | |
97 | // {1920, 3, 240, 0}, | 95 | // {1920, 3, 240, 0}, | |
98 | // {2000, 3, 250, 0}, | 96 | // {2000, 3, 250, 0}, | |
99 | }; | 97 | }; | |
100 | #endif | 98 | #endif | |
101 | 99 | |||
102 | 100 | |||
103 | #ifdef EXYNOS5 | 101 | #ifdef SOC_EXYNOS5 | |
104 | #define EXYNOS5_DEFAULT_ENTRY 7 | 102 | #define EXYNOS5_DEFAULT_ENTRY 7 | |
105 | const struct cpu_freq cpu_freq_settings_exynos5[] = { | 103 | const struct cpu_freq cpu_freq_settings_exynos5[] = { | |
106 | { 200, 3, 100, 2}, | 104 | { 200, 3, 100, 2}, | |
107 | { 333, 4, 222, 2}, | 105 | { 333, 4, 222, 2}, | |
108 | { 400, 3, 100, 1}, | 106 | { 400, 3, 100, 1}, | |
109 | { 533, 12, 533, 1}, | 107 | { 533, 12, 533, 1}, | |
110 | { 600, 4, 200, 1}, | 108 | { 600, 4, 200, 1}, | |
111 | { 667, 7, 389, 1}, | 109 | { 667, 7, 389, 1}, | |
112 | { 800, 3, 100, 0}, | 110 | { 800, 3, 100, 0}, | |
113 | { 900, 4, 150, 0}, | 111 | { 900, 4, 150, 0}, | |
114 | {1000, 3, 125, 0}, | 112 | {1000, 3, 125, 0}, | |
115 | {1066, 12, 533, 0}, | 113 | {1066, 12, 533, 0}, | |
116 | {1200, 3, 150, 0}, | 114 | {1200, 3, 150, 0}, | |
@@ -197,27 +195,27 @@ exynos_set_cpu_boot_addr(int cpu, vaddr_ | @@ -197,27 +195,27 @@ exynos_set_cpu_boot_addr(int cpu, vaddr_ | |||
197 | return 0; | 195 | return 0; | |
198 | } | 196 | } | |
199 | 197 | |||
200 | 198 | |||
201 | int | 199 | int | |
202 | exynos_cpu_boot(int cpu) | 200 | exynos_cpu_boot(int cpu) | |
203 | { | 201 | { | |
204 | exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); | 202 | exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); | |
205 | 203 | |||
206 | return 0; | 204 | return 0; | |
207 | } | 205 | } | |
208 | 206 | |||
209 | 207 | |||
210 | #ifdef EXYNOS4 | 208 | #ifdef SOC_EXYNOS4 | |
211 | /* | 209 | /* | |
212 | * The latency values used below are `magic' and probably chosen empirically. | 210 | * The latency values used below are `magic' and probably chosen empirically. | |
213 | * For the 4210 variant the data latency is lower, a 0x110. This is currently | 211 | * For the 4210 variant the data latency is lower, a 0x110. This is currently | |
214 | * not enforced. | 212 | * not enforced. | |
215 | * | 213 | * | |
216 | * The prefetch values are also different for the revision 0 of the | 214 | * The prefetch values are also different for the revision 0 of the | |
217 | * Exynos4412, but why? | 215 | * Exynos4412, but why? | |
218 | */ | 216 | */ | |
219 | 217 | |||
220 | int | 218 | int | |
221 | exynos4_l2cc_init(void) | 219 | exynos4_l2cc_init(void) | |
222 | { | 220 | { | |
223 | const uint32_t tag_latency = 0x110; | 221 | const uint32_t tag_latency = 0x110; | |
@@ -446,64 +444,73 @@ sysctl_cpufreq_current(SYSCTLFN_ARGS) | @@ -446,64 +444,73 @@ sysctl_cpufreq_current(SYSCTLFN_ARGS) | |||
446 | regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_bsh, reg); \ | 444 | regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_bsh, reg); \ | |
447 | freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \ | 445 | freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \ | |
448 | printf("%8s at %d Mhz\n", #var, freq/(1000*1000)); | 446 | printf("%8s at %d Mhz\n", #var, freq/(1000*1000)); | |
449 | 447 | |||
450 | 448 | |||
451 | static void | 449 | static void | |
452 | exynos_dump_clocks(void) | 450 | exynos_dump_clocks(void) | |
453 | { | 451 | { | |
454 | uint32_t reg = 0; | 452 | uint32_t reg = 0; | |
455 | uint32_t regval; | 453 | uint32_t regval; | |
456 | uint32_t freq; | 454 | uint32_t freq; | |
457 | 455 | |||
458 | printf("Initial PLL settings\n"); | 456 | printf("Initial PLL settings\n"); | |
459 | #ifdef EXYNOS4 | 457 | #ifdef SOC_EXYNOS4 | |
460 | DUMP_PLL(4, APLL); | 458 | DUMP_PLL(4, APLL); | |
461 | DUMP_PLL(4, MPLL); | 459 | DUMP_PLL(4, MPLL); | |
462 | DUMP_PLL(4, EPLL); | 460 | DUMP_PLL(4, EPLL); | |
463 | DUMP_PLL(4, VPLL); | 461 | DUMP_PLL(4, VPLL); | |
464 | #endif | 462 | #endif | |
465 | #ifdef EXYNOS5 | 463 | #ifdef SOC_EXYNOS5 | |
466 | DUMP_PLL(5, APLL); | 464 | DUMP_PLL(5, APLL); | |
467 | DUMP_PLL(5, MPLL); | 465 | DUMP_PLL(5, MPLL); | |
468 | DUMP_PLL(5, KPLL); | 466 | DUMP_PLL(5, KPLL); | |
469 | DUMP_PLL(5, DPLL); | 467 | DUMP_PLL(5, DPLL); | |
470 | DUMP_PLL(5, VPLL); | 468 | DUMP_PLL(5, VPLL); | |
471 | DUMP_PLL(5, CPLL); | 469 | DUMP_PLL(5, CPLL); | |
472 | DUMP_PLL(5, GPLL); | 470 | DUMP_PLL(5, GPLL); | |
473 | DUMP_PLL(5, BPLL); | 471 | DUMP_PLL(5, BPLL); | |
474 | #endif | 472 | #endif | |
475 | } | 473 | } | |
476 | #undef DUMP_PLL | 474 | #undef DUMP_PLL | |
477 | #endif | 475 | #endif | |
478 | 476 | |||
479 | 477 | |||
480 | /* XXX clock stuff needs major work XXX */ | 478 | /* XXX clock stuff needs major work XXX */ | |
481 | 479 | |||
482 | void | 480 | void | |
481 | exynos_init_clkout_for_usb(void) | |||
482 | { | |||
483 | /* Select XUSBXTI as source for CLKOUT */ | |||
484 | bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, | |||
485 | EXYNOS_PMU_DEBUG_CLKOUT, 0x1000); | |||
486 | } | |||
487 | ||||
488 | ||||
489 | void | |||
483 | exynos_clocks_bootstrap(void) | 490 | exynos_clocks_bootstrap(void) | |
484 | { | 491 | { | |
485 | KASSERT(ncpu_freq_settings != 0); | 492 | KASSERT(ncpu_freq_settings != 0); | |
486 | KASSERT(ncpu_freq_settings < NFRQS); | 493 | KASSERT(ncpu_freq_settings < NFRQS); | |
487 | int fsel; | 494 | int fsel; | |
488 | 495 | |||
489 | #ifdef VERBOSE_INIT_ARM | 496 | #ifdef VERBOSE_INIT_ARM | |
490 | exynos_dump_clocks(); | 497 | exynos_dump_clocks(); | |
491 | #endif | 498 | #endif | |
492 | 499 | |||
493 | /* set (max) cpufreq */ | 500 | /* set (max) cpufreq */ | |
494 | fsel = ncpu_freq_settings-1; | 501 | fsel = ncpu_freq_settings-1; | |
495 | 502 | |||
496 | #ifdef EXYNOS5 | 503 | #ifdef SOC_EXYNOS5 | |
497 | /* XXX BUGFIX selecting freq on E5 goes wrong for now XXX */ | 504 | /* XXX BUGFIX selecting freq on E5 goes wrong for now XXX */ | |
498 | fsel = EXYNOS5_DEFAULT_ENTRY; | 505 | fsel = EXYNOS5_DEFAULT_ENTRY; | |
499 | #endif | 506 | #endif | |
500 | 507 | |||
501 | exynos_set_cpufreq(&cpu_freq_settings[fsel]); | 508 | exynos_set_cpufreq(&cpu_freq_settings[fsel]); | |
502 | 509 | |||
503 | /* set external USB frequency to XCLKOUT */ | 510 | /* set external USB frequency to XCLKOUT */ | |
504 | exynos_init_clkout_for_usb(); | 511 | exynos_init_clkout_for_usb(); | |
505 | } | 512 | } | |
506 | 513 | |||
507 | 514 | |||
508 | void | 515 | void | |
509 | exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase) | 516 | exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase) | |
@@ -514,41 +521,41 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t | @@ -514,41 +521,41 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t | |||
514 | bus_addr_t audiocore_vbase __diagused; | 521 | bus_addr_t audiocore_vbase __diagused; | |
515 | bus_addr_t exynos_wdt_offset; | 522 | bus_addr_t exynos_wdt_offset; | |
516 | bus_addr_t exynos_pmu_offset; | 523 | bus_addr_t exynos_pmu_offset; | |
517 | bus_addr_t exynos_sysreg_offset; | 524 | bus_addr_t exynos_sysreg_offset; | |
518 | bus_addr_t exynos_cmu_apll_offset; | 525 | bus_addr_t exynos_cmu_apll_offset; | |
519 | 526 | |||
520 | /* set up early console so we can use printf() and friends */ | 527 | /* set up early console so we can use printf() and friends */ | |
521 | #ifdef EXYNOS_CONSOLE_EARLY | 528 | #ifdef EXYNOS_CONSOLE_EARLY | |
522 | uart_base = (volatile uint8_t *) uartbase; | 529 | uart_base = (volatile uint8_t *) uartbase; | |
523 | cn_tab = &exynos_earlycons; | 530 | cn_tab = &exynos_earlycons; | |
524 | printf("Exynos early console operational\n\n"); | 531 | printf("Exynos early console operational\n\n"); | |
525 | #endif | 532 | #endif | |
526 | 533 | |||
527 | #ifdef EXYNOS4 | 534 | #ifdef SOC_EXYNOS4 | |
528 | core_size = EXYNOS4_CORE_SIZE; | 535 | core_size = EXYNOS4_CORE_SIZE; | |
529 | audiocore_size = EXYNOS4_AUDIOCORE_SIZE; | 536 | audiocore_size = EXYNOS4_AUDIOCORE_SIZE; | |
530 | audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE; | 537 | audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE; | |
531 | audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE; | 538 | audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE; | |
532 | exynos_wdt_offset = EXYNOS4_WDT_OFFSET; | 539 | exynos_wdt_offset = EXYNOS4_WDT_OFFSET; | |
533 | exynos_pmu_offset = EXYNOS4_PMU_OFFSET; | 540 | exynos_pmu_offset = EXYNOS4_PMU_OFFSET; | |
534 | exynos_sysreg_offset = EXYNOS4_SYSREG_OFFSET; | 541 | exynos_sysreg_offset = EXYNOS4_SYSREG_OFFSET; | |
535 | exynos_cmu_apll_offset = EXYNOS4_CMU_APLL; | 542 | exynos_cmu_apll_offset = EXYNOS4_CMU_APLL; | |
536 | 543 | |||
537 | cpu_freq_settings = cpu_freq_settings_exynos4; | 544 | cpu_freq_settings = cpu_freq_settings_exynos4; | |
538 | ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4); | 545 | ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4); | |
539 | #endif | 546 | #endif | |
540 | 547 | |||
541 | #ifdef EXYNOS5 | 548 | #ifdef SOC_EXYNOS5 | |
542 | core_size = EXYNOS5_CORE_SIZE; | 549 | core_size = EXYNOS5_CORE_SIZE; | |
543 | audiocore_size = EXYNOS5_AUDIOCORE_SIZE; | 550 | audiocore_size = EXYNOS5_AUDIOCORE_SIZE; | |
544 | audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE; | 551 | audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE; | |
545 | audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE; | 552 | audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE; | |
546 | exynos_wdt_offset = EXYNOS5_WDT_OFFSET; | 553 | exynos_wdt_offset = EXYNOS5_WDT_OFFSET; | |
547 | exynos_pmu_offset = EXYNOS5_PMU_OFFSET; | 554 | exynos_pmu_offset = EXYNOS5_PMU_OFFSET; | |
548 | exynos_sysreg_offset = EXYNOS5_SYSREG_OFFSET; | 555 | exynos_sysreg_offset = EXYNOS5_SYSREG_OFFSET; | |
549 | exynos_cmu_apll_offset = EXYNOS5_CMU_APLL; | 556 | exynos_cmu_apll_offset = EXYNOS5_CMU_APLL; | |
550 | 557 | |||
551 | cpu_freq_settings = cpu_freq_settings_exynos5; | 558 | cpu_freq_settings = cpu_freq_settings_exynos5; | |
552 | ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5); | 559 | ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5); | |
553 | #endif | 560 | #endif | |
554 | 561 | |||
@@ -584,29 +591,26 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t | @@ -584,29 +591,26 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t | |||
584 | bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, | 591 | bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, | |
585 | exynos_sysreg_offset, EXYNOS_BLOCK_SIZE, | 592 | exynos_sysreg_offset, EXYNOS_BLOCK_SIZE, | |
586 | &exynos_sysreg_bsh); | 593 | &exynos_sysreg_bsh); | |
587 | if (error) | 594 | if (error) | |
588 | panic("%s: failed to subregion sysreg registers: %d", | 595 | panic("%s: failed to subregion sysreg registers: %d", | |
589 | __func__, error); | 596 | __func__, error); | |
590 | 597 | |||
591 | error = bus_space_subregion(&armv7_generic_bs_tag, exynos_cmu_bsh, | 598 | error = bus_space_subregion(&armv7_generic_bs_tag, exynos_cmu_bsh, | |
592 | exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh); | 599 | exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh); | |
593 | if (error) | 600 | if (error) | |
594 | panic("%s: failed to subregion cmu apll registers: %d", | 601 | panic("%s: failed to subregion cmu apll registers: %d", | |
595 | __func__, error); | 602 | __func__, error); | |
596 | 603 | |||
597 | /* init bus dma tags */ | |||
598 | exynos_dma_bootstrap(physmem * PAGE_SIZE); | |||
599 | ||||
600 | /* gpio bootstrapping delayed */ | 604 | /* gpio bootstrapping delayed */ | |
601 | } | 605 | } | |
602 | 606 | |||
603 | 607 | |||
604 | void | 608 | void | |
605 | exynos_device_register(device_t self, void *aux) | 609 | exynos_device_register(device_t self, void *aux) | |
606 | { | 610 | { | |
607 | if (device_is_a(self, "armperiph") | 611 | if (device_is_a(self, "armperiph") | |
608 | && device_is_a(device_parent(self), "mainbus")) { | 612 | && device_is_a(device_parent(self), "mainbus")) { | |
609 | /* | 613 | /* | |
610 | * XXX KLUDGE ALERT XXX | 614 | * XXX KLUDGE ALERT XXX | |
611 | * The iot mainbus supplies is completely wrong since it scales | 615 | * The iot mainbus supplies is completely wrong since it scales | |
612 | * addresses by 2. The simplest remedy is to replace with our | 616 | * addresses by 2. The simplest remedy is to replace with our | |
@@ -615,63 +619,63 @@ exynos_device_register(device_t self, vo | @@ -615,63 +619,63 @@ exynos_device_register(device_t self, vo | |||
615 | struct mainbus_attach_args * const mb = aux; | 619 | struct mainbus_attach_args * const mb = aux; | |
616 | mb->mb_iot = &armv7_generic_bs_tag; | 620 | mb->mb_iot = &armv7_generic_bs_tag; | |
617 | return; | 621 | return; | |
618 | } | 622 | } | |
619 | if (device_is_a(self, "armgic") | 623 | if (device_is_a(self, "armgic") | |
620 | && device_is_a(device_parent(self), "armperiph")) { | 624 | && device_is_a(device_parent(self), "armperiph")) { | |
621 | /* | 625 | /* | |
622 | * The Exynos4420 armgic is located at a different location! | 626 | * The Exynos4420 armgic is located at a different location! | |
623 | */ | 627 | */ | |
624 | 628 | |||
625 | extern uint32_t exynos_soc_id; | 629 | extern uint32_t exynos_soc_id; | |
626 | 630 | |||
627 | switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) { | 631 | switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) { | |
628 | #ifdef EXYNOS5 | 632 | #ifdef SOC_EXYNOS5 | |
629 | case 0xe5410: | 633 | case 0xe5410: | |
630 | /* offsets not changed on matt's request */ | 634 | /* offsets not changed on matt's request */ | |
631 | #if 0 | 635 | #if 0 | |
632 | mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; | 636 | mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; | |
633 | mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; | 637 | mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; | |
634 | mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; | 638 | mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; | |
635 | #endif | 639 | #endif | |
636 | break; | 640 | break; | |
637 | case 0xe5422: { | 641 | case 0xe5422: { | |
638 | struct mpcore_attach_args * const mpcaa = aux; | 642 | struct mpcore_attach_args * const mpcaa = aux; | |
639 | 643 | |||
640 | mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; | 644 | mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; | |
641 | mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; | 645 | mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; | |
642 | mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; | 646 | mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; | |
643 | break; | 647 | break; | |
644 | } | 648 | } | |
645 | #endif | 649 | #endif | |
646 | #ifdef EXYNOS4 | 650 | #ifdef SOC_EXYNOS4 | |
647 | case 0xe4410: | 651 | case 0xe4410: | |
648 | case 0xe4412: { | 652 | case 0xe4412: { | |
649 | struct mpcore_attach_args * const mpcaa = aux; | 653 | struct mpcore_attach_args * const mpcaa = aux; | |
650 | 654 | |||
651 | mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; | 655 | mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; | |
652 | mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET; | 656 | mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET; | |
653 | mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET; | 657 | mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET; | |
654 | break; | 658 | break; | |
655 | } | 659 | } | |
656 | #endif | 660 | #endif | |
657 | default: | 661 | default: | |
658 | panic("%s: unknown SoC product id %#x", __func__, | 662 | panic("%s: unknown SoC product id %#x", __func__, | |
659 | (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id)); | 663 | (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id)); | |
660 | } | 664 | } | |
661 | return; | 665 | return; | |
662 | } | 666 | } | |
663 | if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) { | 667 | if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) { | |
664 | #ifdef EXYNOS5 | 668 | #ifdef SOC_EXYNOS5 | |
665 | /* | 669 | /* | |
666 | * The global timer is dependent on the MCT running. | 670 | * The global timer is dependent on the MCT running. | |
667 | */ | 671 | */ | |
668 | bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON; | 672 | bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON; | |
669 | uint32_t v = bus_space_read_4(&armv7_generic_bs_tag, exynos_core_bsh, | 673 | uint32_t v = bus_space_read_4(&armv7_generic_bs_tag, exynos_core_bsh, | |
670 | o); | 674 | o); | |
671 | v |= G_TCON_START; | 675 | v |= G_TCON_START; | |
672 | bus_space_write_4(&armv7_generic_bs_tag, exynos_core_bsh, o, v); | 676 | bus_space_write_4(&armv7_generic_bs_tag, exynos_core_bsh, o, v); | |
673 | #endif | 677 | #endif | |
674 | /* | 678 | /* | |
675 | * The frequencies of the timers are the reference | 679 | * The frequencies of the timers are the reference | |
676 | * frequency. | 680 | * frequency. | |
677 | */ | 681 | */ | |
@@ -723,27 +727,27 @@ exynos_usb2_set_isolation(bool on) | @@ -723,27 +727,27 @@ exynos_usb2_set_isolation(bool on) | |||
723 | 727 | |||
724 | bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, | 728 | bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, | |
725 | reg, regval); | 729 | reg, regval); | |
726 | 730 | |||
727 | if (IS_EXYNOS4X12_P()) { | 731 | if (IS_EXYNOS4X12_P()) { | |
728 | bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, | 732 | bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, | |
729 | EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval); | 733 | EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval); | |
730 | bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, | 734 | bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, | |
731 | EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval); | 735 | EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval); | |
732 | } | 736 | } | |
733 | } | 737 | } | |
734 | 738 | |||
735 | 739 | |||
736 | #ifdef EXYNOS4 | 740 | #ifdef SOC_EXYNOS4 | |
737 | static void | 741 | static void | |
738 | exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh) | 742 | exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh) | |
739 | { | 743 | { | |
740 | uint32_t phypwr, rstcon, clkreg; | 744 | uint32_t phypwr, rstcon, clkreg; | |
741 | 745 | |||
742 | /* write clock value */ | 746 | /* write clock value */ | |
743 | clkreg = FSEL_CLKSEL_24M; | 747 | clkreg = FSEL_CLKSEL_24M; | |
744 | bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, | 748 | bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, | |
745 | USB_PHYCLK, clkreg); | 749 | USB_PHYCLK, clkreg); | |
746 | 750 | |||
747 | /* set device and host to normal */ | 751 | /* set device and host to normal */ | |
748 | phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, | 752 | phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, | |
749 | USB_PHYPWR); | 753 | USB_PHYPWR); | |
@@ -784,27 +788,27 @@ exynos4_usb2phy_enable(bus_space_handle_ | @@ -784,27 +788,27 @@ exynos4_usb2phy_enable(bus_space_handle_ | |||
784 | USB_RSTCON, rstcon); | 788 | USB_RSTCON, rstcon); | |
785 | DELAY(10000); | 789 | DELAY(10000); | |
786 | rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST); | 790 | rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST); | |
787 | bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, | 791 | bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, | |
788 | USB_RSTCON, rstcon); | 792 | USB_RSTCON, rstcon); | |
789 | } | 793 | } | |
790 | 794 | |||
791 | /* wait for everything to be initialized */ | 795 | /* wait for everything to be initialized */ | |
792 | DELAY(80000); | 796 | DELAY(80000); | |
793 | } | 797 | } | |
794 | #endif | 798 | #endif | |
795 | 799 | |||
796 | 800 | |||
797 | #ifdef EXYNOS5 | 801 | #ifdef SOC_EXYNOS5 | |
798 | static void | 802 | static void | |
799 | exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh) | 803 | exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh) | |
800 | { | 804 | { | |
801 | uint32_t phyhost; //, phyotg; | 805 | uint32_t phyhost; //, phyotg; | |
802 | uint32_t phyhsic; | 806 | uint32_t phyhsic; | |
803 | uint32_t ehcictrl, ohcictrl; | 807 | uint32_t ehcictrl, ohcictrl; | |
804 | 808 | |||
805 | /* host configuration: */ | 809 | /* host configuration: */ | |
806 | phyhost = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, | 810 | phyhost = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, | |
807 | USB_PHY_HOST_CTRL0); | 811 | USB_PHY_HOST_CTRL0); | |
808 | 812 | |||
809 | /* host phy reference clock; assumption its 24 MHz now */ | 813 | /* host phy reference clock; assumption its 24 MHz now */ | |
810 | phyhost &= ~HOST_CTRL0_FSEL_MASK; | 814 | phyhost &= ~HOST_CTRL0_FSEL_MASK; | |
@@ -899,28 +903,28 @@ static void | @@ -899,28 +903,28 @@ static void | |||
899 | exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh) | 903 | exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh) | |
900 | { | 904 | { | |
901 | aprint_error("%s not implemented\n", __func__); | 905 | aprint_error("%s not implemented\n", __func__); | |
902 | } | 906 | } | |
903 | #endif | 907 | #endif | |
904 | 908 | |||
905 | 909 | |||
906 | void | 910 | void | |
907 | exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh) | 911 | exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh) | |
908 | { | 912 | { | |
909 | /* disable phy isolation */ | 913 | /* disable phy isolation */ | |
910 | exynos_usb2_set_isolation(false); | 914 | exynos_usb2_set_isolation(false); | |
911 | 915 | |||
912 | #ifdef EXYNOS4 | 916 | #ifdef SOC_EXYNOS4 | |
913 | exynos4_usb2phy_enable(usb2phy_bsh); | 917 | exynos4_usb2phy_enable(usb2phy_bsh); | |
914 | #endif | 918 | #endif | |
915 | #ifdef EXYNOS5 | 919 | #ifdef SOC_EXYNOS5 | |
916 | if (IS_EXYNOS5410_P()) { | 920 | if (IS_EXYNOS5410_P()) { | |
917 | exynos5410_usb2phy_enable(usb2phy_bsh); | 921 | exynos5410_usb2phy_enable(usb2phy_bsh); | |
918 | /* TBD: USB3 phy init */ | 922 | /* TBD: USB3 phy init */ | |
919 | } else if (IS_EXYNOS5422_P()) { | 923 | } else if (IS_EXYNOS5422_P()) { | |
920 | exynos5422_usb2phy_enable(usb2phy_bsh); | 924 | exynos5422_usb2phy_enable(usb2phy_bsh); | |
921 | /* TBD: USB3 phy init */ | 925 | /* TBD: USB3 phy init */ | |
922 | } | 926 | } | |
923 | #endif | 927 | #endif | |
924 | } | 928 | } | |
925 | 929 | |||
926 | 930 |
--- src/sys/arch/arm/samsung/Attic/exynos_sscom.c 2015/12/21 00:54:35 1.7
+++ src/sys/arch/arm/samsung/Attic/exynos_sscom.c 2017/06/10 15:13:18 1.8
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: exynos_sscom.c,v 1.7 2015/12/21 00:54:35 marty Exp $ */ | 1 | /* $NetBSD: exynos_sscom.c,v 1.8 2017/06/10 15:13:18 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /* | 3 | /* | |
4 | * Copyright (c) 2014 Reinoud Zandijk | 4 | * Copyright (c) 2014 Reinoud Zandijk | |
5 | * Copyright (c) 2002, 2003 Fujitsu Component Limited | 5 | * Copyright (c) 2002, 2003 Fujitsu Component Limited | |
6 | * Copyright (c) 2002, 2003 Genetec Corporation | 6 | * Copyright (c) 2002, 2003 Genetec Corporation | |
7 | * All rights reserved. | 7 | * All rights reserved. | |
8 | * | 8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | 9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | 10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | 11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | 12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions and the following disclaimer. | 13 | * notice, this list of conditions and the following disclaimer. | |
14 | * 2. Redistributions in binary form must reproduce the above copyright | 14 | * 2. Redistributions in binary form must reproduce the above copyright | |
@@ -24,27 +24,27 @@ | @@ -24,27 +24,27 @@ | |||
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | 24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 | * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC | 25 | * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC | |
26 | * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | 26 | * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
27 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | 27 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
28 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | 28 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | 29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
30 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | 30 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
31 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | 31 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
32 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | 32 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
33 | * SUCH DAMAGE. | 33 | * SUCH DAMAGE. | |
34 | */ | 34 | */ | |
35 | 35 | |||
36 | #include <sys/cdefs.h> | 36 | #include <sys/cdefs.h> | |
37 | __KERNEL_RCSID(0, "$NetBSD: exynos_sscom.c,v 1.7 2015/12/21 00:54:35 marty Exp $"); | 37 | __KERNEL_RCSID(0, "$NetBSD: exynos_sscom.c,v 1.8 2017/06/10 15:13:18 jmcneill Exp $"); | |
38 | 38 | |||
39 | #include "opt_sscom.h" | 39 | #include "opt_sscom.h" | |
40 | #include "opt_ddb.h" | 40 | #include "opt_ddb.h" | |
41 | #include "opt_kgdb.h" | 41 | #include "opt_kgdb.h" | |
42 | 42 | |||
43 | #include <sys/param.h> | 43 | #include <sys/param.h> | |
44 | #include <sys/systm.h> | 44 | #include <sys/systm.h> | |
45 | #include <sys/ioctl.h> | 45 | #include <sys/ioctl.h> | |
46 | #include <sys/select.h> | 46 | #include <sys/select.h> | |
47 | #include <sys/tty.h> | 47 | #include <sys/tty.h> | |
48 | #include <sys/proc.h> | 48 | #include <sys/proc.h> | |
49 | #include <sys/conf.h> | 49 | #include <sys/conf.h> | |
50 | #include <sys/file.h> | 50 | #include <sys/file.h> | |
@@ -69,30 +69,34 @@ __KERNEL_RCSID(0, "$NetBSD: exynos_sscom | @@ -69,30 +69,34 @@ __KERNEL_RCSID(0, "$NetBSD: exynos_sscom | |||
69 | #include <dev/fdt/fdtvar.h> | 69 | #include <dev/fdt/fdtvar.h> | |
70 | 70 | |||
71 | #include <evbarm/exynos/platform.h> | 71 | #include <evbarm/exynos/platform.h> | |
72 | 72 | |||
73 | extern int num_exynos_uarts_entries; | 73 | extern int num_exynos_uarts_entries; | |
74 | extern int exynos_uarts[]; | 74 | extern int exynos_uarts[]; | |
75 | 75 | |||
76 | static int sscom_match(device_t, cfdata_t, void *); | 76 | static int sscom_match(device_t, cfdata_t, void *); | |
77 | static void sscom_attach(device_t, device_t, void *); | 77 | static void sscom_attach(device_t, device_t, void *); | |
78 | 78 | |||
79 | CFATTACH_DECL_NEW(exynos_sscom, sizeof(struct sscom_softc), sscom_match, | 79 | CFATTACH_DECL_NEW(exynos_sscom, sizeof(struct sscom_softc), sscom_match, | |
80 | sscom_attach, NULL, NULL); | 80 | sscom_attach, NULL, NULL); | |
81 | 81 | |||
82 | static const char * const compatible[] = { | |||
83 | "samsung,exynos4210-uart", | |||
84 | NULL | |||
85 | }; | |||
86 | ||||
82 | static int | 87 | static int | |
83 | sscom_match(device_t parent, cfdata_t cf, void *aux) | 88 | sscom_match(device_t parent, cfdata_t cf, void *aux) | |
84 | { | 89 | { | |
85 | const char * const compatible[] = { "samsung,exynos4210-uart", NULL }; | |||
86 | struct fdt_attach_args * const faa = aux; | 90 | struct fdt_attach_args * const faa = aux; | |
87 | 91 | |||
88 | return of_match_compatible(faa->faa_phandle, compatible); | 92 | return of_match_compatible(faa->faa_phandle, compatible); | |
89 | } | 93 | } | |
90 | 94 | |||
91 | static void | 95 | static void | |
92 | exynos_unmask_interrupts(struct sscom_softc *sc, int intbits) | 96 | exynos_unmask_interrupts(struct sscom_softc *sc, int intbits) | |
93 | { | 97 | { | |
94 | int psw = disable_interrupts(IF32_bits); | 98 | int psw = disable_interrupts(IF32_bits); | |
95 | uint32_t val; | 99 | uint32_t val; | |
96 | 100 | |||
97 | val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM); | 101 | val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM); | |
98 | val &= ~intbits; | 102 | val &= ~intbits; | |
@@ -137,92 +141,134 @@ exynos_clear_interrupts(struct sscom_sof | @@ -137,92 +141,134 @@ exynos_clear_interrupts(struct sscom_sof | |||
137 | 141 | |||
138 | if (flags & SSCOM_HW_RXINT) | 142 | if (flags & SSCOM_HW_RXINT) | |
139 | val |= UINT_RXD; | 143 | val |= UINT_RXD; | |
140 | if (flags & SSCOM_HW_TXINT) | 144 | if (flags & SSCOM_HW_TXINT) | |
141 | val |= UINT_TXD; | 145 | val |= UINT_TXD; | |
142 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTP, val); | 146 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTP, val); | |
143 | } | 147 | } | |
144 | 148 | |||
145 | static void | 149 | static void | |
146 | sscom_attach(device_t parent, device_t self, void *aux) | 150 | sscom_attach(device_t parent, device_t self, void *aux) | |
147 | { | 151 | { | |
148 | struct sscom_softc *sc = device_private(self); | 152 | struct sscom_softc *sc = device_private(self); | |
149 | struct fdt_attach_args *faa = aux; | 153 | struct fdt_attach_args *faa = aux; | |
150 | int unit = -1; | 154 | const int phandle = faa->faa_phandle; | |
155 | bus_space_tag_t bst = faa->faa_bst; | |||
151 | bus_space_handle_t bsh; | 156 | bus_space_handle_t bsh; | |
152 | bus_space_tag_t bst; | 157 | struct clk *clk_uart, *clk_uart_baud0; | |
153 | bus_addr_t addr; | 158 | bus_addr_t addr; | |
154 | bus_size_t size; | 159 | bus_size_t size; | |
155 | int error; | |||
156 | int i; | |||
157 | 160 | |||
158 | if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { | 161 | if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { | |
159 | aprint_error(": couldn't get registers\n"); | 162 | aprint_error(": couldn't get registers\n"); | |
160 | return; | 163 | return; | |
161 | } | 164 | } | |
162 | /* unit is required for the sscom driver, which desperately | 165 | ||
163 | * needs to be rewritten. For now, this hack gets the answer. | 166 | if (bus_space_map(bst, addr, size, 0, &bsh) != 0) { | |
164 | * MJF: FIX ME | 167 | aprint_error(": couldn't map registers\n"); | |
165 | */ | 168 | return; | |
166 | for (i = 1; i < num_exynos_uarts_entries; i += 2) | 169 | } | |
167 | if (EXYNOS_CORE_PBASE + exynos_uarts[i] == addr) | 170 | ||
168 | break; | 171 | clk_uart = fdtbus_clock_get(phandle, "uart"); | |
169 | unit = exynos_uarts[i-1]; | 172 | clk_uart_baud0 = fdtbus_clock_get(phandle, "clk_uart_baud0"); | |
173 | if (clk_uart == NULL || clk_uart_baud0 == NULL) { | |||
174 | aprint_error(": couldn't get clocks\n"); | |||
175 | return; | |||
176 | } | |||
177 | if (clk_enable(clk_uart) != 0 || clk_enable(clk_uart_baud0) != 0) { | |||
178 | aprint_error(": couldn't enable clocks\n"); | |||
179 | return; | |||
180 | } | |||
170 | 181 | |||
171 | sc->sc_dev = self; | 182 | sc->sc_dev = self; | |
172 | sc->sc_iot = bst = faa->faa_bst; | 183 | sc->sc_iot = bst = faa->faa_bst; | |
173 | sc->sc_ioh = exynos_uarts[i] + EXYNOS_CORE_VBASE; | 184 | sc->sc_ioh = bsh; | |
174 | sc->sc_unit = unit; | 185 | sc->sc_unit = phandle; | |
175 | sc->sc_frequency = EXYNOS_UART_FREQ; | 186 | sc->sc_frequency = clk_get_rate(clk_uart); | |
176 | 187 | |||
177 | sc->sc_change_txrx_interrupts = exynos_change_txrx_interrupts; | 188 | sc->sc_change_txrx_interrupts = exynos_change_txrx_interrupts; | |
178 | sc->sc_clear_interrupts = exynos_clear_interrupts; | 189 | sc->sc_clear_interrupts = exynos_clear_interrupts; | |
179 | 190 | |||
180 | /* not used here, but do initialise */ | 191 | /* not used here, but do initialise */ | |
181 | sc->sc_rx_irqno = 0; | 192 | sc->sc_rx_irqno = 0; | |
182 | sc->sc_tx_irqno = 0; | 193 | sc->sc_tx_irqno = 0; | |
183 | 194 | |||
184 | if (!sscom_is_console(sc->sc_iot, unit, &sc->sc_ioh)) { | 195 | if (sscom_is_console(sc->sc_iot, phandle, &sc->sc_ioh)) | |
185 | error = bus_space_map(bst, addr, size, 0, &bsh); | 196 | aprint_normal(" (console)"); | |
186 | if (error) { | |||
187 | aprint_error(": couldn't map %#llx: %d\n", | |||
188 | (uint64_t)addr, error); | |||
189 | return; | |||
190 | } | |||
191 | sc->sc_ioh = bsh; | |||
192 | } else { | |||
193 | aprint_normal(" (console) "); | |||
194 | } | |||
195 | 197 | |||
196 | aprint_normal("\n"); | 198 | aprint_normal("\n"); | |
197 | 199 | |||
198 | #if 0 | 200 | void *ih = fdtbus_intr_establish(phandle, 0, IPL_SERIAL, | |
199 | void *ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SERIAL, | |||
200 | FDT_INTR_MPSAFE, sscomintr, sc); | 201 | FDT_INTR_MPSAFE, sscomintr, sc); | |
201 | if (ih == NULL) | 202 | if (ih == NULL) | |
202 | aprint_error_dev(self, "failed to establish interrupt\n"); | 203 | aprint_error_dev(self, "failed to establish interrupt\n"); | |
203 | #endif | |||
204 | 204 | |||
205 | sscom_attach_subr(sc); | 205 | sscom_attach_subr(sc); | |
206 | 206 | |||
207 | } | 207 | } | |
208 | 208 | |||
209 | 209 | |||
210 | #if 0 | 210 | #if 0 | |
211 | int | 211 | int | |
212 | exynos_sscom_cnattach(bus_space_tag_t iot, int unit, int rate, | 212 | exynos_sscom_cnattach(bus_space_tag_t iot, int unit, int rate, | |
213 | int frequency, tcflag_t cflag) | 213 | int frequency, tcflag_t cflag) | |
214 | { | 214 | { | |
215 | return sscom_cnattach(iot, exynos_uart_config + unit, | 215 | return sscom_cnattach(iot, exynos_uart_config + unit, | |
216 | rate, frequency, cflag); | 216 | rate, frequency, cflag); | |
217 | } | 217 | } | |
218 | 218 | |||
219 | #ifdef KGDB | 219 | #ifdef KGDB | |
220 | int | 220 | int | |
221 | exynos_sscom_kgdb_attach(bus_space_tag_t iot, int unit, int rate, | 221 | exynos_sscom_kgdb_attach(bus_space_tag_t iot, int unit, int rate, | |
222 | int frequency, tcflag_t cflag) | 222 | int frequency, tcflag_t cflag) | |
223 | { | 223 | { | |
224 | return sscom_kgdb_attach(iot, exynos_uart_config + unit, | 224 | return sscom_kgdb_attach(iot, exynos_uart_config + unit, | |
225 | rate, frequency, cflag); | 225 | rate, frequency, cflag); | |
226 | } | 226 | } | |
227 | #endif /* KGDB */ | 227 | #endif /* KGDB */ | |
228 | #endif | 228 | #endif | |
229 | ||||
230 | ||||
231 | /* | |||
232 | * Console support | |||
233 | */ | |||
234 | ||||
235 | static int | |||
236 | exynos_sscom_console_match(int phandle) | |||
237 | { | |||
238 | return of_match_compatible(phandle, compatible); | |||
239 | } | |||
240 | ||||
241 | static void | |||
242 | exynos_sscom_console_consinit(struct fdt_attach_args *faa, u_int uart_freq) | |||
243 | { | |||
244 | const struct sscom_uart_info info = { | |||
245 | .iobase = 0, /* Offset from bsh */ | |||
246 | .unit = faa->faa_phandle | |||
247 | }; | |||
248 | const int phandle = faa->faa_phandle; | |||
249 | bus_space_tag_t bst = faa->faa_bst; | |||
250 | bus_space_handle_t bsh; | |||
251 | bus_addr_t addr; | |||
252 | bus_size_t size; | |||
253 | tcflag_t flags; | |||
254 | int speed; | |||
255 | ||||
256 | fdtbus_get_reg(phandle, 0, &addr, &size); | |||
257 | speed = fdtbus_get_stdout_speed(); | |||
258 | if (speed < 0) | |||
259 | speed = 115200; /* default */ | |||
260 | flags = fdtbus_get_stdout_flags(); | |||
261 | ||||
262 | if (bus_space_map(bst, addr, size, 0, &bsh) != 0) | |||
263 | panic("cannot map console UART"); | |||
264 | ||||
265 | if (sscom_cnattach(bst, bsh, &info, speed, uart_freq, flags) != 0) | |||
266 | panic("cannot attach console UART"); | |||
267 | } | |||
268 | ||||
269 | static const struct fdt_console exynos_sscom_console = { | |||
270 | .match = exynos_sscom_console_match, | |||
271 | .consinit = exynos_sscom_console_consinit, | |||
272 | }; | |||
273 | ||||
274 | FDT_CONSOLE(exynos_sscom, &exynos_sscom_console); |
--- src/sys/arch/arm/samsung/files.exynos 2016/01/03 04:10:58 1.21
+++ src/sys/arch/arm/samsung/files.exynos 2017/06/10 15:13:18 1.22
@@ -1,62 +1,59 @@ | @@ -1,62 +1,59 @@ | |||
1 | # $NetBSD: files.exynos,v 1.21 2016/01/03 04:10:58 marty Exp $ | 1 | # $NetBSD: files.exynos,v 1.22 2017/06/10 15:13:18 jmcneill Exp $ | |
2 | # | 2 | # | |
3 | # Configuration info for Samsung Exynos SoC ARM Peripherals | 3 | # Configuration info for Samsung Exynos SoC ARM Peripherals | |
4 | # | 4 | # | |
5 | 5 | |||
6 | include "arch/arm/pic/files.pic" | 6 | include "arch/arm/pic/files.pic" | |
7 | include "arch/arm/cortex/files.cortex" | 7 | include "arch/arm/cortex/files.cortex" | |
8 | 8 | |||
9 | defflag opt_cpuoptions.h ARM_TRUSTZONE_FIRMWARE | 9 | defflag opt_cpuoptions.h ARM_TRUSTZONE_FIRMWARE | |
10 | 10 | |||
11 | file arch/arm/arm32/arm32_boot.c | 11 | file arch/arm/arm32/arm32_boot.c | |
12 | file arch/arm/arm32/arm32_kvminit.c | 12 | file arch/arm/arm32/arm32_kvminit.c | |
13 | file arch/arm/arm32/arm32_reboot.c | 13 | file arch/arm/arm32/arm32_reboot.c | |
14 | file arch/arm/arm32/irq_dispatch.S | 14 | file arch/arm/arm32/irq_dispatch.S | |
15 | file arch/arm/arm32/armv7_generic_space.c | 15 | file arch/arm/arm32/armv7_generic_space.c | |
16 | file arch/arm/arm32/armv7_generic_dma.c | |||
16 | file arch/arm/arm/bus_space_a4x.S | 17 | file arch/arm/arm/bus_space_a4x.S | |
17 | 18 | |||
18 | file arch/arm/samsung/exynos_soc.c | 19 | file arch/arm/samsung/exynos_soc.c | |
19 | #file arch/arm/samsung/exynos_space.c | |||
20 | file arch/arm/samsung/exynos_smc.S arm_trustzone_firmware | 20 | file arch/arm/samsung/exynos_smc.S arm_trustzone_firmware | |
21 | 21 | |||
22 | # Console parameters | 22 | # Console parameters | |
23 | defparam opt_exynos.h CONADDR | 23 | defparam opt_exynos.h CONADDR | |
24 | defparam opt_exynos.h CONSPEED | 24 | defparam opt_exynos.h CONSPEED | |
25 | defparam opt_exynos.h CONMODE | 25 | defparam opt_exynos.h CONMODE | |
26 | 26 | |||
27 | # Memory size in megabytes | 27 | # Memory size in megabytes | |
28 | defparam opt_exynos.h MEMSIZE | 28 | defparam opt_exynos.h MEMSIZE | |
29 | defparam opt_exynos.h EXYNOS_WDT_DEFAULT_PERIOD | 29 | defparam opt_exynos.h EXYNOS_WDT_DEFAULT_PERIOD | |
30 | defflag opt_exynos.h EXYNOS_CONSOLE_EARLY | 30 | defflag opt_exynos.h EXYNOS_CONSOLE_EARLY | |
31 | 31 | |||
32 | # | 32 | # | |
33 | defflag opt_exynos.h EXYNOS4: CPU_CORTEXA9 | 33 | defflag opt_exynos.h SOC_EXYNOS4: CPU_CORTEXA9 | |
34 | defflag opt_exynos.h EXYNOS4120: EXYNOS4 | 34 | defflag opt_exynos.h SOC_EXYNOS4120: SOC_EXYNOS4 | |
35 | defflag opt_exynos.h EXYNOS4212: EXYNOS4 | 35 | defflag opt_exynos.h SOC_EXYNOS4212: SOC_EXYNOS4 | |
36 | defflag opt_exynos.h EXYNOS4412: EXYNOS4 | 36 | defflag opt_exynos.h SOC_EXYNOS4412: SOC_EXYNOS4 | |
37 | defflag opt_exynos.h EXYNOS4412P: EXYNOS4 | 37 | defflag opt_exynos.h SOC_EXYNOS4412P: SOC_EXYNOS4 | |
38 | defflag opt_exynos.h EXYNOS5: CPU_CORTEXA15 | 38 | defflag opt_exynos.h SOC_EXYNOS5: CPU_CORTEXA15 | |
39 | defflag opt_exynos.h EXYNOS5250: EXYNOS5 | 39 | defflag opt_exynos.h SOC_EXYNOS5250: SOC_EXYNOS5 | |
40 | defflag opt_exynos.h EXYNOS5260: EXYNOS5 | 40 | defflag opt_exynos.h SOC_EXYNOS5260: SOC_EXYNOS5 | |
41 | defflag opt_exynos.h EXYNOS5410: EXYNOS5 | 41 | defflag opt_exynos.h SOC_EXYNOS5410: SOC_EXYNOS5 | |
42 | defflag opt_exynos.h EXYNOS5420: EXYNOS5 | 42 | defflag opt_exynos.h SOC_EXYNOS5420: SOC_EXYNOS5 | |
43 | defflag opt_exynos.h EXYNOS5440: EXYNOS5 | 43 | defflag opt_exynos.h SOC_EXYNOS5440: SOC_EXYNOS5 | |
44 | defflag opt_exynos.h EXYNOS5422: EXYNOS5 | 44 | defflag opt_exynos.h SOC_EXYNOS5422: SOC_EXYNOS5 | |
45 | 45 | |||
46 | # On-board I/O | 46 | file arch/arm/samsung/exynos_platform.c soc_exynos5 | |
47 | device exynosfdt : bus_space_generic, fdtbus | |||
48 | attach exynosfdt at mainbus with exynos_fdt | |||
49 | file arch/arm/samsung/exynos_fdt.c exynos_fdt | |||
50 | 47 | |||
51 | # Interrupt combiner | 48 | # Interrupt combiner | |
52 | device exyointr | 49 | device exyointr | |
53 | attach exyointr at fdt with exynos_intr | 50 | attach exyointr at fdt with exynos_intr | |
54 | file arch/arm/samsung/exynos_combiner.c exynos_intr | 51 | file arch/arm/samsung/exynos_combiner.c exynos_intr | |
55 | 52 | |||
56 | # CHIP ID register | 53 | # CHIP ID register | |
57 | device chipid : fdtbus | 54 | device chipid : fdtbus | |
58 | attach chipid at fdt with exynos_chipid | 55 | attach chipid at fdt with exynos_chipid | |
59 | file arch/arm/samsung/exynos_chipid.c exynos_chipid | 56 | file arch/arm/samsung/exynos_chipid.c exynos_chipid | |
60 | 57 | |||
61 | # SYSMMU | 58 | # SYSMMU | |
62 | device sysmmu : fdtbus | 59 | device sysmmu : fdtbus | |
@@ -110,18 +107,16 @@ device exyousb : fdtbus | @@ -110,18 +107,16 @@ device exyousb : fdtbus | |||
110 | attach exyousb at fdt with exynos_usb | 107 | attach exyousb at fdt with exynos_usb | |
111 | attach xhci at fdt | 108 | attach xhci at fdt | |
112 | file arch/arm/samsung/exynos_usb3.c exynos_usb | 109 | file arch/arm/samsung/exynos_usb3.c exynos_usb | |
113 | 110 | |||
114 | # SD/MMC Host Controller | 111 | # SD/MMC Host Controller | |
115 | attach dwcmmc at fdt with exynos_dwcmmc | 112 | attach dwcmmc at fdt with exynos_dwcmmc | |
116 | file arch/arm/samsung/exynos_dwcmmc.c exynos_dwcmmc | 113 | file arch/arm/samsung/exynos_dwcmmc.c exynos_dwcmmc | |
117 | 114 | |||
118 | # I2C support, bitbanging through GPIO | 115 | # I2C support, bitbanging through GPIO | |
119 | device exyoi2c: i2cbus, i2c_bitbang | 116 | device exyoi2c: i2cbus, i2c_bitbang | |
120 | attach exyoi2c at fdt with exynos_i2c | 117 | attach exyoi2c at fdt with exynos_i2c | |
121 | file arch/arm/samsung/exynos_i2c.c exynos_i2c needs-flag | 118 | file arch/arm/samsung/exynos_i2c.c exynos_i2c needs-flag | |
122 | 119 | |||
123 | file arch/arm/samsung/exynos5422_dma.c | |||
124 | ||||
125 | device exy5422clk: clk | 120 | device exy5422clk: clk | |
126 | attach exy5422clk at fdt with exynos5422_clock | 121 | attach exy5422clk at fdt with exynos5422_clock | |
127 | file arch/arm/samsung/exynos5422_clock.c exynos5422_clock | 122 | file arch/arm/samsung/exynos5422_clock.c exynos5422_clock |
--- src/sys/arch/arm/samsung/Attic/sscom.c 2015/04/13 21:18:41 1.8
+++ src/sys/arch/arm/samsung/Attic/sscom.c 2017/06/10 15:13:18 1.9
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: sscom.c,v 1.8 2015/04/13 21:18:41 riastradh Exp $ */ | 1 | /* $NetBSD: sscom.c,v 1.9 2017/06/10 15:13:18 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /* | 3 | /* | |
4 | * Copyright (c) 2002, 2003 Fujitsu Component Limited | 4 | * Copyright (c) 2002, 2003 Fujitsu Component Limited | |
5 | * Copyright (c) 2002, 2003 Genetec Corporation | 5 | * Copyright (c) 2002, 2003 Genetec Corporation | |
6 | * All rights reserved. | 6 | * All rights reserved. | |
7 | * | 7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | 8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions | 9 | * modification, are permitted provided that the following conditions | |
10 | * are met: | 10 | * are met: | |
11 | * 1. Redistributions of source code must retain the above copyright | 11 | * 1. Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | 12 | * notice, this list of conditions and the following disclaimer. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | 13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | 14 | * notice, this list of conditions and the following disclaimer in the | |
@@ -88,27 +88,27 @@ | @@ -88,27 +88,27 @@ | |||
88 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | 88 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
89 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | 89 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
90 | * SUCH DAMAGE. | 90 | * SUCH DAMAGE. | |
91 | * | 91 | * | |
92 | * @(#)com.c 7.5 (Berkeley) 5/16/91 | 92 | * @(#)com.c 7.5 (Berkeley) 5/16/91 | |
93 | */ | 93 | */ | |
94 | 94 | |||
95 | /* | 95 | /* | |
96 | * Support integrated UARTs of Samsung S3C2800/2400X/2410X | 96 | * Support integrated UARTs of Samsung S3C2800/2400X/2410X | |
97 | * Derived from sys/dev/ic/com.c | 97 | * Derived from sys/dev/ic/com.c | |
98 | */ | 98 | */ | |
99 | 99 | |||
100 | #include <sys/cdefs.h> | 100 | #include <sys/cdefs.h> | |
101 | __KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.8 2015/04/13 21:18:41 riastradh Exp $"); | 101 | __KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.9 2017/06/10 15:13:18 jmcneill Exp $"); | |
102 | 102 | |||
103 | #include "opt_sscom.h" | 103 | #include "opt_sscom.h" | |
104 | #include "opt_ddb.h" | 104 | #include "opt_ddb.h" | |
105 | #include "opt_kgdb.h" | 105 | #include "opt_kgdb.h" | |
106 | #include "opt_multiprocessor.h" | 106 | #include "opt_multiprocessor.h" | |
107 | #include "opt_lockdebug.h" | 107 | #include "opt_lockdebug.h" | |
108 | 108 | |||
109 | #ifdef RND_COM | 109 | #ifdef RND_COM | |
110 | #include <sys/rndsource.h> | 110 | #include <sys/rndsource.h> | |
111 | #endif | 111 | #endif | |
112 | 112 | |||
113 | /* | 113 | /* | |
114 | * Override cnmagic(9) macro before including <sys/systm.h>. | 114 | * Override cnmagic(9) macro before including <sys/systm.h>. | |
@@ -169,33 +169,29 @@ integrate void sscom_stsoft (struct ssco | @@ -169,33 +169,29 @@ integrate void sscom_stsoft (struct ssco | |||
169 | integrate void sscom_schedrx (struct sscom_softc *); | 169 | integrate void sscom_schedrx (struct sscom_softc *); | |
170 | static void sscom_modem(struct sscom_softc *, int); | 170 | static void sscom_modem(struct sscom_softc *, int); | |
171 | static void sscom_break(struct sscom_softc *, int); | 171 | static void sscom_break(struct sscom_softc *, int); | |
172 | static void sscom_iflush(struct sscom_softc *); | 172 | static void sscom_iflush(struct sscom_softc *); | |
173 | static void sscom_hwiflow(struct sscom_softc *); | 173 | static void sscom_hwiflow(struct sscom_softc *); | |
174 | static void sscom_loadchannelregs(struct sscom_softc *); | 174 | static void sscom_loadchannelregs(struct sscom_softc *); | |
175 | static void tiocm_to_sscom(struct sscom_softc *, u_long, int); | 175 | static void tiocm_to_sscom(struct sscom_softc *, u_long, int); | |
176 | static int sscom_to_tiocm(struct sscom_softc *); | 176 | static int sscom_to_tiocm(struct sscom_softc *); | |
177 | static void tiocm_to_sscom(struct sscom_softc *, u_long, int); | 177 | static void tiocm_to_sscom(struct sscom_softc *, u_long, int); | |
178 | static int sscom_to_tiocm(struct sscom_softc *); | 178 | static int sscom_to_tiocm(struct sscom_softc *); | |
179 | static void sscom_iflush(struct sscom_softc *); | 179 | static void sscom_iflush(struct sscom_softc *); | |
180 | 180 | |||
181 | static int sscomhwiflow(struct tty *tp, int block); | 181 | static int sscomhwiflow(struct tty *tp, int block); | |
182 | #if defined(KGDB) || \ | |||
183 | defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) || \ | |||
184 | defined(SSCOM2CONSOLE) || defined(SSCOM3CONSOLE) | |||
185 | static int sscom_init(bus_space_tag_t, bus_space_handle_t, | 182 | static int sscom_init(bus_space_tag_t, bus_space_handle_t, | |
186 | const struct sscom_uart_info *, | 183 | const struct sscom_uart_info *, | |
187 | int, int, tcflag_t, bus_space_handle_t *); | 184 | int, int, tcflag_t, bus_space_handle_t *); | |
188 | #endif | |||
189 | 185 | |||
190 | extern struct cfdriver sscom_cd; | 186 | extern struct cfdriver sscom_cd; | |
191 | 187 | |||
192 | const struct cdevsw sscom_cdevsw = { | 188 | const struct cdevsw sscom_cdevsw = { | |
193 | .d_open = sscomopen, | 189 | .d_open = sscomopen, | |
194 | .d_close = sscomclose, | 190 | .d_close = sscomclose, | |
195 | .d_read = sscomread, | 191 | .d_read = sscomread, | |
196 | .d_write = sscomwrite, | 192 | .d_write = sscomwrite, | |
197 | .d_ioctl = sscomioctl, | 193 | .d_ioctl = sscomioctl, | |
198 | .d_stop = sscomstop, | 194 | .d_stop = sscomstop, | |
199 | .d_tty = sscomtty, | 195 | .d_tty = sscomtty, | |
200 | .d_poll = sscompoll, | 196 | .d_poll = sscompoll, | |
201 | .d_mmap = nommap, | 197 | .d_mmap = nommap, | |
@@ -1826,29 +1822,26 @@ sscomintr(void *v) | @@ -1826,29 +1822,26 @@ sscomintr(void *v) | |||
1826 | 1822 | |||
1827 | if (sscomrxintr(v)) | 1823 | if (sscomrxintr(v)) | |
1828 | clear |= SSCOM_HW_RXINT; | 1824 | clear |= SSCOM_HW_RXINT; | |
1829 | if (sscomtxintr(v)) | 1825 | if (sscomtxintr(v)) | |
1830 | clear |= SSCOM_HW_TXINT; | 1826 | clear |= SSCOM_HW_TXINT; | |
1831 | 1827 | |||
1832 | if (clear) | 1828 | if (clear) | |
1833 | sc->sc_clear_interrupts(sc, clear); | 1829 | sc->sc_clear_interrupts(sc, clear); | |
1834 | 1830 | |||
1835 | return clear? 1: 0; | 1831 | return clear? 1: 0; | |
1836 | } | 1832 | } | |
1837 | 1833 | |||
1838 | 1834 | |||
1839 | #if defined(KGDB) || \ | |||
1840 | defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) || \ | |||
1841 | defined(SSCOM2CONSOLE) || defined(SSCOM3CONSOLE) | |||
1842 | /* | 1835 | /* | |
1843 | * Initialize UART for use as console or KGDB line. | 1836 | * Initialize UART for use as console or KGDB line. | |
1844 | */ | 1837 | */ | |
1845 | static int | 1838 | static int | |
1846 | sscom_init(bus_space_tag_t iot, bus_space_handle_t base_ioh, | 1839 | sscom_init(bus_space_tag_t iot, bus_space_handle_t base_ioh, | |
1847 | const struct sscom_uart_info *config, | 1840 | const struct sscom_uart_info *config, | |
1848 | int rate, int frequency, tcflag_t cflag, bus_space_handle_t *iohp) | 1841 | int rate, int frequency, tcflag_t cflag, bus_space_handle_t *iohp) | |
1849 | { | 1842 | { | |
1850 | bus_space_handle_t ioh; | 1843 | bus_space_handle_t ioh; | |
1851 | bus_addr_t iobase = config->iobase; | 1844 | bus_addr_t iobase = config->iobase; | |
1852 | int timo = 150000; | 1845 | int timo = 150000; | |
1853 | 1846 | |||
1854 | bus_space_subregion(iot, base_ioh, iobase, SSCOM_SIZE, &ioh); | 1847 | bus_space_subregion(iot, base_ioh, iobase, SSCOM_SIZE, &ioh); | |
@@ -1872,31 +1865,26 @@ sscom_init(bus_space_tag_t iot, bus_spac | @@ -1872,31 +1865,26 @@ sscom_init(bus_space_tag_t iot, bus_spac | |||
1872 | rate = sscomspeed(rate, frequency); | 1865 | rate = sscomspeed(rate, frequency); | |
1873 | bus_space_write_4(iot, ioh, SSCOM_UBRDIV, rate); | 1866 | bus_space_write_4(iot, ioh, SSCOM_UBRDIV, rate); | |
1874 | bus_space_write_4(iot, ioh, SSCOM_ULCON, cflag2lcr(cflag)); | 1867 | bus_space_write_4(iot, ioh, SSCOM_ULCON, cflag2lcr(cflag)); | |
1875 | 1868 | |||
1876 | /* enable UART */ | 1869 | /* enable UART */ | |
1877 | bus_space_write_4(iot, ioh, SSCOM_UCON, | 1870 | bus_space_write_4(iot, ioh, SSCOM_UCON, | |
1878 | UCON_TXMODE_INT|UCON_RXMODE_INT); | 1871 | UCON_TXMODE_INT|UCON_RXMODE_INT); | |
1879 | bus_space_write_4(iot, ioh, SSCOM_UMCON, UMCON_RTS); | 1872 | bus_space_write_4(iot, ioh, SSCOM_UMCON, UMCON_RTS); | |
1880 | 1873 | |||
1881 | *iohp = ioh; | 1874 | *iohp = ioh; | |
1882 | return 0; | 1875 | return 0; | |
1883 | } | 1876 | } | |
1884 | 1877 | |||
1885 | #endif | |||
1886 | ||||
1887 | #if \ | |||
1888 | defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) || \ | |||
1889 | defined(SSCOM2CONSOLE) || defined(SSCOM3CONSOLE) | |||
1890 | /* | 1878 | /* | |
1891 | * Following are all routines needed for SSCOM to act as console | 1879 | * Following are all routines needed for SSCOM to act as console | |
1892 | */ | 1880 | */ | |
1893 | struct consdev sscomcons = { | 1881 | struct consdev sscomcons = { | |
1894 | NULL, NULL, sscomcngetc, sscomcnputc, sscomcnpollc, NULL, | 1882 | NULL, NULL, sscomcngetc, sscomcnputc, sscomcnpollc, NULL, | |
1895 | NULL, NULL, NODEV, CN_NORMAL | 1883 | NULL, NULL, NODEV, CN_NORMAL | |
1896 | }; | 1884 | }; | |
1897 | 1885 | |||
1898 | 1886 | |||
1899 | int | 1887 | int | |
1900 | sscom_cnattach(bus_space_tag_t iot, bus_space_handle_t ioh, | 1888 | sscom_cnattach(bus_space_tag_t iot, bus_space_handle_t ioh, | |
1901 | const struct sscom_uart_info *config, | 1889 | const struct sscom_uart_info *config, | |
1902 | int rate, int frequency, tcflag_t cflag) | 1890 | int rate, int frequency, tcflag_t cflag) | |
@@ -2014,28 +2002,26 @@ sscomcnputc(dev_t dev, int c) | @@ -2014,28 +2002,26 @@ sscomcnputc(dev_t dev, int c) | |||
2014 | UTRSTAT_TXEMPTY) && --timo) | 2002 | UTRSTAT_TXEMPTY) && --timo) | |
2015 | continue; | 2003 | continue; | |
2016 | #endif | 2004 | #endif | |
2017 | splx(s); | 2005 | splx(s); | |
2018 | } | 2006 | } | |
2019 | 2007 | |||
2020 | void | 2008 | void | |
2021 | sscomcnpollc(dev_t dev, int on) | 2009 | sscomcnpollc(dev_t dev, int on) | |
2022 | { | 2010 | { | |
2023 | 2011 | |||
2024 | sscom_readaheadcount = 0; | 2012 | sscom_readaheadcount = 0; | |
2025 | } | 2013 | } | |
2026 | 2014 | |||
2027 | #endif /* SSCOM0CONSOLE||SSCOM1CONSOLE */ | |||
2028 | ||||
2029 | #ifdef KGDB | 2015 | #ifdef KGDB | |
2030 | int | 2016 | int | |
2031 | sscom_kgdb_attach(bus_space_tag_t iot, bus_space_handle_t ioh, | 2017 | sscom_kgdb_attach(bus_space_tag_t iot, bus_space_handle_t ioh, | |
2032 | const struct sscom_uart_info *config, | 2018 | const struct sscom_uart_info *config, | |
2033 | int rate, int frequency, tcflag_t cflag) | 2019 | int rate, int frequency, tcflag_t cflag) | |
2034 | { | 2020 | { | |
2035 | int res; | 2021 | int res; | |
2036 | 2022 | |||
2037 | if (iot == sscomconstag && config->unit == sscomconsunit) { | 2023 | if (iot == sscomconstag && config->unit == sscomconsunit) { | |
2038 | printf( "console==kgdb_port (%d): kgdb disabled\n", sscomconsunit); | 2024 | printf( "console==kgdb_port (%d): kgdb disabled\n", sscomconsunit); | |
2039 | return EBUSY; /* cannot share with console */ | 2025 | return EBUSY; /* cannot share with console */ | |
2040 | } | 2026 | } | |
2041 | 2027 |
--- src/sys/arch/evbarm/conf/Attic/EXYNOS 2017/04/16 15:49:26 1.14
+++ src/sys/arch/evbarm/conf/Attic/EXYNOS 2017/06/10 15:13:19 1.15
@@ -1,301 +1,94 @@ | @@ -1,301 +1,94 @@ | |||
1 | # | 1 | # | |
2 | # $NetBSD: EXYNOS,v 1.14 2017/04/16 15:49:26 jmcneill Exp $ | 2 | # $NetBSD: EXYNOS,v 1.15 2017/06/10 15:13:19 jmcneill Exp $ | |
3 | # | 3 | # | |
4 | # ODROID-XU -- ODROID-XU4 Exynos5422 based kernel | 4 | # Samsung Exynos SoC kernel | |
5 | # | 5 | # | |
6 | 6 | |||
7 | include "arch/evbarm/conf/std.exynos" | 7 | include "arch/evbarm/conf/std.exynos" | |
8 | include "arch/evbarm/conf/GENERIC.common" | |||
8 | 9 | |||
9 | no makeoptions CPUFLAGS | |||
10 | makeoptions CPUFLAGS="-mcpu=cortex-a7 -mfpu=neon" | |||
11 | no makeoptions BOARDTYPE | |||
12 | makeoptions BOARDTYPE="hardkernel_odroid_xu4" | |||
13 | no makeoptions KERNEL_BASE_PHYS | |||
14 | no makeoptions KERNEL_BASE_VIRT | |||
15 | makeoptions KERNEL_BASE_PHYS="0x80000000" | |||
16 | makeoptions KERNEL_BASE_VIRT="0x80000000" | |||
17 | options PMAP_NEED_ALLOC_POOLPAGE | |||
18 | options MEMSIZE=2048 | |||
19 | ||||
20 | # estimated number of users | |||
21 | ||||
22 | maxusers 8 | |||
23 | ||||
24 | # Standard system options | |||
25 | ||||
26 | options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT | |||
27 | #options NTP # NTP phase/frequency locked loop | |||
28 | ||||
29 | # CPU options | |||
30 | options CPU_CORTEX | |||
31 | options CPU_CORTEXA7 | 10 | options CPU_CORTEXA7 | |
32 | options CPU_CORTEXA15 | 11 | options CPU_CORTEXA15 | |
33 | options EXYNOS5422 | 12 | options SOC_EXYNOS5422 | |
34 | #options MULTIPROCESSOR | 13 | options MULTIPROCESSOR | |
35 | 14 | |||
36 | options FDT # not really but soon | 15 | pseudo-device openfirm # /dev/openfirm | |
37 | pseudo-device openfirm # jmcneill: oops, fdtbus should depend on | 16 | ||
38 | # openfirm. don't let me forget. | 17 | #options DIAGNOSTIC # internal consistency checks | |
39 | 18 | #options DEBUG | ||
40 | 19 | #options LOCKDEBUG | ||
41 | options PMAPCOUNTERS | 20 | #options PMAP_DEBUG # Enable pmap_debug_level code | |
42 | options BUSDMA_COUNTERS | |||
43 | options EXYNOS_CONSOLE_EARLY | |||
44 | #options UVMHIST | |||
45 | options USBHIST | |||
46 | options USBHIST_SIZE=100000 | |||
47 | #options UVMHIST_PRINT,KERNHIST_DELAY=0 | |||
48 | options __HAVE_MM_MD_DIRECT_MAPPED_PHYS | |||
49 | #options PMAP_NEED_ALLOC_POOLPAGE | |||
50 | ||||
51 | # Specify the memory size in megabytes (optional). | |||
52 | #options MEMSIZE=2048 | |||
53 | ||||
54 | # File systems | |||
55 | file-system FFS # UFS | |||
56 | #file-system LFS # log-structured file system | |||
57 | file-system MFS # memory file system | |||
58 | file-system NFS # Network file system | |||
59 | #file-system ADOSFS # AmigaDOS-compatible file system | |||
60 | #file-system EXT2FS # second extended file system (linux) | |||
61 | #file-system CD9660 # ISO 9660 + Rock Ridge file system | |||
62 | file-system MSDOSFS # MS-DOS file system | |||
63 | #file-system FDESC # /dev/fd | |||
64 | file-system KERNFS # /kern | |||
65 | #file-system NULLFS # loopback file system | |||
66 | file-system PROCFS # /proc | |||
67 | #file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs) | |||
68 | #file-system UMAPFS # NULLFS + uid and gid remapping | |||
69 | #file-system UNION # union file system | |||
70 | file-system TMPFS # memory file system | |||
71 | file-system PTYFS # /dev/pts/N support | |||
72 | ||||
73 | # File system options | |||
74 | #options QUOTA # legacy UFS quotas | |||
75 | #options QUOTA2 # new, in-filesystem UFS quotas | |||
76 | #options DISKLABEL_EI # disklabel Endian Independent support | |||
77 | #options FFS_EI # FFS Endian Independent support | |||
78 | options NFSSERVER | |||
79 | options WAPBL # File system journaling support | |||
80 | #options FFS_NO_SNAPSHOT # No FFS snapshot support | |||
81 | ||||
82 | # Networking options | |||
83 | ||||
84 | #options GATEWAY # packet forwarding | |||
85 | options INET # IP + ICMP + TCP + UDP | |||
86 | options INET6 # IPV6 | |||
87 | #options IPSEC # IP security | |||
88 | #options IPSEC_DEBUG # debug for IP security | |||
89 | #options MROUTING # IP multicast routing | |||
90 | #options PIM # Protocol Independent Multicast | |||
91 | #options NETATALK # AppleTalk networking | |||
92 | #options PPP_BSDCOMP # BSD-Compress compression support for PPP | |||
93 | #options PPP_DEFLATE # Deflate compression support for PPP | |||
94 | #options PPP_FILTER # Active filter support for PPP (requires bpf) | |||
95 | #options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG | |||
96 | ||||
97 | #options NFS_BOOT_BOOTP | |||
98 | #options NFS_BOOT_DHCP | |||
99 | #options NFS_BOOT_BOOTSTATIC | |||
100 | #options NFS_BOOTSTATIC_MYIP="\"192.168.0.22\"" | |||
101 | #options NFS_BOOTSTATIC_GWIP="\"192.168.0.1\"" | |||
102 | #options NFS_BOOTSTATIC_MASK="\"255.255.255.0\"" | |||
103 | #options NFS_BOOTSTATIC_SERVADDR="\"192.168.0.5\"" | |||
104 | #options NFS_BOOTSTATIC_SERVER="\"192.168.0.5:/stuff/nfs/odroid\"" | |||
105 | ||||
106 | #options NFS_BOOT_RWSIZE=1024 | |||
107 | ||||
108 | # Compatibility options | |||
109 | ||||
110 | options COMPAT_NETBSD32 # allow running arm (e.g. non-earm) binaries | |||
111 | #options COMPAT_43 # 4.3BSD compatibility. | |||
112 | #options COMPAT_09 # NetBSD 0.9, | |||
113 | #options COMPAT_10 # NetBSD 1.0, | |||
114 | #options COMPAT_11 # NetBSD 1.1, | |||
115 | #options COMPAT_12 # NetBSD 1.2, | |||
116 | #options COMPAT_13 # NetBSD 1.3, | |||
117 | #options COMPAT_14 # NetBSD 1.4, | |||
118 | #options COMPAT_15 # NetBSD 1.5, | |||
119 | #options COMPAT_16 # NetBSD 1.6, | |||
120 | #options COMPAT_20 # NetBSD 2.0, | |||
121 | #options COMPAT_30 # NetBSD 3.0, | |||
122 | #options COMPAT_40 # NetBSD 4.0, | |||
123 | #options COMPAT_50 # NetBSD 5.0, | |||
124 | options COMPAT_60 # NetBSD 6.0, and | |||
125 | options COMPAT_70 # NetBSD 7.0 binary compatibility. | |||
126 | #options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended. | |||
127 | #options COMPAT_BSDPTY # /dev/[pt]ty?? ptys. | |||
128 | ||||
129 | # Shared memory options | |||
130 | ||||
131 | options SYSVMSG # System V-like message queues | |||
132 | options SYSVSEM # System V-like semaphores | |||
133 | options SYSVSHM # System V-like memory sharing | |||
134 | ||||
135 | # Device options | |||
136 | ||||
137 | #options MEMORY_DISK_HOOKS # boottime setup of ramdisk | |||
138 | #options MEMORY_DISK_ROOT_SIZE=8192 # Size in blocks | |||
139 | #options MEMORY_DISK_DYNAMIC | |||
140 | #options MINIROOTSIZE=1000 # Size in blocks | |||
141 | #options MEMORY_DISK_IS_ROOT # use memory disk as root | |||
142 | ||||
143 | # Wedge support | |||
144 | options DKWEDGE_AUTODISCOVER # Automatically add dk(4) instances | |||
145 | options DKWEDGE_METHOD_GPT # Supports GPT partitions as wedges | |||
146 | ||||
147 | # Miscellaneous kernel options | |||
148 | options KTRACE # system call tracing, a la ktrace(1) | |||
149 | #options SCSIVERBOSE # Verbose SCSI errors | |||
150 | #options MIIVERBOSE # Verbose MII autoconfuration messages | |||
151 | options DDB_KEYCODE=0x40 | |||
152 | #options USERCONF # userconf(4) support | |||
153 | #options PIPE_SOCKETPAIR # smaller, but slower pipe(2) | |||
154 | ||||
155 | # Development and Debugging options | |||
156 | ||||
157 | #options PERFCTRS # performance counters | |||
158 | options DIAGNOSTIC # internal consistency checks | |||
159 | options DEBUG | |||
160 | options LOCKDEBUG | |||
161 | options PMAP_DEBUG # Enable pmap_debug_level code | |||
162 | #options IPKDB # remote kernel debugging | 21 | #options IPKDB # remote kernel debugging | |
163 | options VERBOSE_INIT_ARM # verbose bootstraping messages | 22 | #options VERBOSE_INIT_ARM # verbose bootstrapping messages | |
164 | options DDB # in-kernel debugger | 23 | # CONSADDR is required for early init messages from VERBOSE_INIT_ARM. | |
165 | options DDB_ONPANIC=1 | 24 | #options CONSADDR=0x70006300 | |
166 | options DDB_HISTORY_SIZE=100 # Enable history editing in DDB | 25 | ||
167 | options DDB_VERBOSE_HELP | |||
168 | #options KGDB | |||
169 | makeoptions DEBUG="-g" # compile full symbol table | 26 | makeoptions DEBUG="-g" # compile full symbol table | |
170 | makeoptions COPY_SYMTAB=1 | 27 | makeoptions COPY_SYMTAB=1 | |
171 | 28 | |||
172 | ## USB Debugging options | |||
173 | options USB_DEBUG | |||
174 | options EHCI_DEBUG | |||
175 | options OHCI_DEBUG | |||
176 | options UHUB_DEBUG | |||
177 | options USBVERBOSE | |||
178 | ||||
179 | ||||
180 | # Valid options for BOOT_ARGS: | |||
181 | # single Boot to single user only | |||
182 | # kdb Give control to kernel debugger | |||
183 | # ask Ask for file name to reboot from | |||
184 | # memorydisk=<n> Set memorydisk size to <n> KB | |||
185 | # quiet Show aprint_naive output | |||
186 | # verbose Show aprint_normal and aprint_verbose output | |||
187 | #options BOOT_ARGS="\"\"" | |||
188 | options BOOT_ARGS="\"verbose\"" | |||
189 | ||||
190 | config netbsd root on ? type ? | 29 | config netbsd root on ? type ? | |
191 | 30 | |||
192 | # The main bus device | 31 | # Device tree support | |
193 | mainbus0 at root | 32 | armfdt0 at root | |
194 | ||||
195 | # The boot cpu and secondary CPUs | |||
196 | cpu0 at mainbus? | |||
197 | cpu* at mainbus? # Multiprocessor | |||
198 | ||||
199 | # core devices | |||
200 | armperiph0 at mainbus? | |||
201 | armgic0 at armperiph? # Interrupt Controller | |||
202 | armgtmr0 at armperiph? # Generic Timer | |||
203 | ||||
204 | # On-board I/O | |||
205 | exynosfdt0 at mainbus? | |||
206 | fdt* at fdtbus? | 33 | fdt* at fdtbus? | |
207 | 34 | |||
208 | fregulator* at fdt? | 35 | # CPUs | |
209 | 36 | cpus* at fdt? pass 0 | ||
210 | #interrupt controller | 37 | cpu* at cpus? | |
211 | exyointr0 at fdt? | 38 | ||
212 | gic* at fdt? | 39 | fclock* at fdt? pass 4 | |
40 | fregulator* at fdt? pass 4 | |||
41 | gpiokeys* at fdt? | |||
42 | ||||
43 | # Timer | |||
44 | gtmr* at fdt? pass 1 # ARM Generic Timer | |||
45 | armgtmr0 at gtmr? | |||
46 | mct* at fdt? # Exynos Multi Core Timer (MCT) | |||
47 | ||||
48 | # Interrupt controller | |||
49 | exyointr* at fdt? pass 1 | |||
50 | gic* at fdt? pass 1 # GIC | |||
51 | armgic0 at gic? | |||
213 | 52 | |||
214 | # Clock controller | 53 | # Clock controller | |
215 | exy5422clk* at fdt? # Exynos5422 clock controller | 54 | exy5422clk* at fdt? pass 3 # Exynos5422 clock controller | |
216 | 55 | |||
217 | # Integrated Samsung UARTs | 56 | # GPIO controller | |
218 | sscom* at fdt? # UART ? | 57 | exyopctl* at fdt? pass 2 # GPIO | |
219 | 58 | gpio* at gpiobus? | ||
220 | # Exynos Watchdog Timer | |||
221 | exyowdt* at fdt? # watchdog | |||
222 | 59 | |||
223 | # Exynos chip id | 60 | # Exynos SoC support | |
224 | chipid* at fdt? | 61 | chipid* at fdt? | |
62 | sysmmu* at fdt? | |||
225 | 63 | |||
226 | # Exynos system MMUs | 64 | # UART | |
227 | sysmmu* at fdt? | 65 | sscom* at fdt? # UART | |
228 | ||||
229 | # Exynos RTC | |||
230 | exyortc* at fdt? | |||
231 | 66 | |||
232 | # Exynos Multi Core timer (MCT) | 67 | # I2C | |
233 | mct* at fdt? | 68 | exyoi2c* at fdt? # I2C | |
69 | iic* at exyoi2c? | |||
234 | 70 | |||
235 | # GPIO | 71 | # RTC | |
236 | exyopctl* at fdt? | 72 | exyortc* at fdt? # RTC | |
237 | gpio* at gpiobus? | |||
238 | ||||
239 | # On-board USB 2.0 | |||
240 | exyousbphy* at fdt? | |||
241 | ohci* at fdt? | |||
242 | ehci* at fdt? | |||
243 | usb* at ohci? | |||
244 | usb* at ehci? | |||
245 | ||||
246 | # On-board USB 3.0 | |||
247 | exyousb* at fdt? | |||
248 | #xhci* at fdt? | |||
249 | #usb* at xhci? | |||
250 | ||||
251 | # I2C devices | |||
252 | exyoi2c* at fdt? | |||
253 | #i2c* at exyoi2c? | |||
254 | 73 | |||
255 | # SD/MMC | 74 | # SDMMC | |
256 | dwcmmc* at fdt? | 75 | dwcmmc* at fdt? # SDMMC | |
257 | sdmmc* at dwcmmc? | 76 | sdmmc* at dwcmmc? | |
258 | ld0 at sdmmc0 | 77 | ld0 at sdmmc0 | |
259 | ld1 at sdmmc1 | 78 | ld1 at sdmmc1 | |
260 | ld2 at sdmmc2 | 79 | ld2 at sdmmc2 | |
80 | ld3 at sdmmc3 | |||
261 | ld* at sdmmc? | 81 | ld* at sdmmc? | |
262 | 82 | |||
263 | # MISSING SUPPORT | 83 | # USB | |
264 | # eMMC | 84 | exyousbphy* at fdt? | |
265 | # uSD | 85 | exyousb* at fdt? | |
266 | # SPI | 86 | ohci* at fdt? # OUSB | |
267 | # ADC | 87 | ehci* at fdt? # EUSB | |
268 | # PMIC (via I2C #4) | 88 | usb* at ohci? | |
269 | # PWM for Cooling fan | 89 | usb* at ehci? | |
270 | # HDMI | |||
271 | # I2S | |||
272 | # GPU | |||
273 | ||||
274 | # serial console connectivity | |||
275 | options SSCOM2CONSOLE, CONSPEED=115200 | |||
276 | 90 | |||
277 | # include all USB devices | |||
278 | include "dev/usb/usbdevices.config" | 91 | include "dev/usb/usbdevices.config" | |
279 | ||||
280 | midi* at midibus? | 92 | midi* at midibus? | |
281 | 93 | |||
282 | # Pseudo-Devices | 94 | cinclude "arch/evbarm/conf/TEGRA.local" | |
283 | ||||
284 | # disk/mass storage pseudo-devices | |||
285 | #pseudo-device md # memory disk device (ramdisk) | |||
286 | #pseudo-device vnd # disk-like interface to files | |||
287 | #pseudo-device fss # file system snapshot device | |||
288 | #pseudo-device putter # for puffs and pud | |||
289 | pseudo-device drvctl # driver control | |||
290 | ||||
291 | # network pseudo-devices | |||
292 | pseudo-device bpfilter # Berkeley packet filter | |||
293 | pseudo-device loop # network loopback | |||
294 | #pseudo-device kttcp # network loopback | |||
295 | ||||
296 | # miscellaneous pseudo-devices | |||
297 | pseudo-device pty # pseudo-terminals | |||
298 | #options RND_COM | |||
299 | #pseudo-device clockctl # user control of clock subsystem | |||
300 | pseudo-device ksyms # /dev/ksyms | |||
301 | #pseudo-device lockstat # lock profiling |
--- src/sys/arch/evbarm/conf/Attic/files.exynos 2015/12/14 22:06:57 1.2
+++ src/sys/arch/evbarm/conf/Attic/files.exynos 2017/06/10 15:13:19 1.3
@@ -1,18 +1,8 @@ | @@ -1,18 +1,8 @@ | |||
1 | # $NetBSD: files.exynos,v 1.2 2015/12/14 22:06:57 marty Exp $ | 1 | # $NetBSD: files.exynos,v 1.3 2017/06/10 15:13:19 jmcneill Exp $ | |
2 | # | 2 | # | |
3 | # EXYNOS 5422 board configuration info | 3 | # EXYNOS board configuration info | |
4 | # | 4 | # | |
5 | 5 | |||
6 | file arch/evbarm/exynos/exynos_machdep.c | 6 | include "arch/evbarm/conf/files.fdt" | |
7 | 7 | |||
8 | # Kernel boot arguments | 8 | include "arch/arm/samsung/files.exynos" | |
9 | defparam opt_machdep.h BOOT_ARGS | |||
10 | ||||
11 | # FDT | |||
12 | ||||
13 | include "dev/ofw/files.ofw" | |||
14 | include "dev/fdt/files.fdt" | |||
15 | include "arch/arm/fdt/files.fdt" | |||
16 | ||||
17 | # Pull in Exynos SoC default | |||
18 | include "arch/arm/samsung/files.exynos" |
--- src/sys/arch/evbarm/conf/Attic/std.exynos 2015/12/06 00:31:24 1.1
+++ src/sys/arch/evbarm/conf/Attic/std.exynos 2017/06/10 15:13:19 1.2
@@ -1,35 +1,35 @@ | @@ -1,35 +1,35 @@ | |||
1 | # $NetBSD: std.exynos,v 1.1 2015/12/06 00:31:24 marty Exp $ | 1 | # $NetBSD: std.exynos,v 1.2 2017/06/10 15:13:19 jmcneill Exp $ | |
2 | # | 2 | # | |
3 | # standard NetBSD/evbarm for EXYNOS options | |||
4 | 3 | |||
5 | machine evbarm arm | 4 | machine evbarm arm | |
6 | include "arch/evbarm/conf/std.evbarm" | 5 | include "arch/evbarm/conf/std.evbarm" | |
7 | 6 | |||
8 | # Pull in EXYNOS config definitions | 7 | include "arch/evbarm/conf/files.exynos" | |
9 | include "arch/evbarm/conf/files.exynos" | |||
10 | 8 | |||
11 | makeoptions CPUFLAGS="-march=armv7-a -mfpu=neon" | 9 | makeoptions CPUFLAGS="-march=armv7-a -mfpu=neon" | |
12 | 10 | |||
13 | # To support easy transit to ../arch/arm/arm32 | 11 | options ARM_TRUSTZONE_FIRMWARE | |
12 | options __NO_FIQ | |||
13 | ||||
14 | options FDT # Flattened Device Tree support | |||
14 | options MODULAR | 15 | options MODULAR | |
15 | options MODULAR_DEFAULT_AUTOLOAD | 16 | options MODULAR_DEFAULT_AUTOLOAD | |
16 | options ARM_HAS_VBAR | |||
17 | options CORTEX_PMC | |||
18 | options __HAVE_CPU_COUNTER | 17 | options __HAVE_CPU_COUNTER | |
19 | options __HAVE_FAST_SOFTINTS # should be in types.h | 18 | options __HAVE_FAST_SOFTINTS # should be in types.h | |
19 | options ARM_HAS_VBAR | |||
20 | #options __HAVE_MM_MD_DIRECT_MAPPED_PHYS | 20 | #options __HAVE_MM_MD_DIRECT_MAPPED_PHYS | |
21 | #options PMAP_NEED_ALLOC_POOLPAGE | |||
21 | options TPIDRPRW_IS_CURCPU | 22 | options TPIDRPRW_IS_CURCPU | |
22 | options KERNEL_BASE_EXT=0x80000000 | 23 | options KERNEL_BASE_EXT=0x80000000 | |
23 | options FPU_VFP | 24 | options FPU_VFP | |
24 | 25 | options PCI_NETBSD_CONFIGURE | ||
25 | # All shipped Samsung SoC's that are not Samsung products have this | 26 | options __HAVE_PCI_CONF_HOOK | |
26 | options ARM_TRUSTZONE_FIRMWARE | 27 | options __BUS_SPACE_HAS_STREAM_METHODS | |
27 | options __NO_FIQ | |||
28 | 28 | |||
29 | makeoptions KERNEL_BASE_PHYS="0x80000000" | 29 | makeoptions KERNEL_BASE_PHYS="0x80000000" | |
30 | makeoptions KERNEL_BASE_VIRT="0x80000000" | 30 | makeoptions KERNEL_BASE_VIRT="0x80000000" | |
31 | makeoptions BOARDTYPE="exynos" | 31 | makeoptions BOARDTYPE="exynos" | |
32 | makeoptions BOARDMKFRAG="${THISARM}/conf/mk.exynos" | 32 | makeoptions BOARDMKFRAG="${THISARM}/conf/mk.exynos" | |
33 | 33 | |||
34 | options ARM_INTR_IMPL="<arch/arm/samsung/exynos_intr.h>" | 34 | options ARM_INTR_IMPL="<arch/arm/fdt/fdt_intr.h>" | |
35 | options ARM_GENERIC_TODR | 35 | options ARM_GENERIC_TODR |
--- src/sys/arch/evbarm/exynos/Attic/platform.h 2015/12/06 00:33:44 1.1
+++ src/sys/arch/evbarm/exynos/Attic/platform.h 2017/06/10 15:13:19 1.2
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: platform.h,v 1.1 2015/12/06 00:33:44 marty Exp $ */ | 1 | /* $NetBSD: platform.h,v 1.2 2017/06/10 15:13:19 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /*- | 3 | /*- | |
4 | * Copyright (c) 2014 The NetBSD Foundation, Inc. | 4 | * Copyright (c) 2014 The NetBSD Foundation, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * This code is derived from software contributed to The NetBSD Foundation | 7 | * This code is derived from software contributed to The NetBSD Foundation | |
8 | * by Nick Hudson | 8 | * by Nick Hudson | |
9 | * | 9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | 10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | 11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | 12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | 13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer. | 14 | * notice, this list of conditions and the following disclaimer. | |
@@ -22,26 +22,22 @@ | @@ -22,26 +22,22 @@ | |||
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
29 | * POSSIBILITY OF SUCH DAMAGE. | 29 | * POSSIBILITY OF SUCH DAMAGE. | |
30 | */ | 30 | */ | |
31 | 31 | |||
32 | #ifndef _ARM_EXYNOS_PLATFORM_H | 32 | #ifndef _ARM_EXYNOS_PLATFORM_H | |
33 | #define _ARM_EXYNOS_PLATFORM_H | 33 | #define _ARM_EXYNOS_PLATFORM_H | |
34 | 34 | |||
35 | /* | 35 | #include <arch/evbarm/fdt/platform.h> | |
36 | * Kernel VM space 16Mb behind KERNEL_BASE upto 0xeff00000 | |||
37 | */ | |||
38 | #define KERNEL_VM_BASE 0xc0000000 | |||
39 | #define KERNEL_VM_SIZE (EXYNOS_CORE_VBASE - KERNEL_VM_BASE) | |||
40 | 36 | |||
41 | /* | 37 | /* | |
42 | * IO space | 38 | * IO space | |
43 | */ | 39 | */ | |
44 | 40 | |||
45 | #define EXYNOS_CORE_VBASE 0xf0000000 | 41 | #define EXYNOS_CORE_VBASE 0xf0000000 | |
46 | 42 | |||
47 | #endif /* _ARM_EXYNOS_PLATFORM_H */ | 43 | #endif /* _ARM_EXYNOS_PLATFORM_H */ |