@@ -1,4 +1,4 @@
-# $NetBSD: md.atari,v 1.54 2014/08/06 12:15:01 martin Exp $
+# $NetBSD: md.atari,v 1.54.16.1 2018/03/13 13:41:14 martin Exp $
 ./sbin/ahdilabel				base-sysutil-root
 ./sbin/binpatch					base-sysutil-root
 ./sbin/edahdi					base-sysutil-root
@@ -10,6 +10,8 @@
 ./usr/mdec/milan/fdboot				base-sysutil-bin
 ./usr/mdec/milan/sdb00t.ahdi			base-sysutil-bin
 ./usr/mdec/milan/sdboot				base-sysutil-bin
+./usr/mdec/milan/wdb00t.ahdi			base-sysutil-bin
+./usr/mdec/milan/wdboot				base-sysutil-bin
 ./usr/mdec/milan/xxboot.ahdi			base-sysutil-bin
 ./usr/mdec/std					base-sysutil-bin
 ./usr/mdec/std/boot.atari			base-sysutil-bin

@@ -1,4 +1,4 @@
-/*	$NetBSD: atari_init.c,v 1.100 2012/08/10 17:43:32 tsutsui Exp $	*/
+/*	$NetBSD: atari_init.c,v 1.100.32.1 2018/03/13 13:41:13 martin Exp $	*/
 
 /*
  * Copyright (c) 1995 Leo Weppelman
@@ -33,7 +33,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: atari_init.c,v 1.100 2012/08/10 17:43:32 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: atari_init.c,v 1.100.32.1 2018/03/13 13:41:13 martin Exp $");
 
 #include "opt_ddb.h"
 #include "opt_mbtype.h"
@@ -91,9 +91,26 @@
 static void mmu040_setup(paddr_t, u_int, paddr_t, psize_t, paddr_t, paddr_t);
 #endif
 
+#if defined(_MILANHW_)
+static u_int milan_probe_bank_1(paddr_t paddr);
+static u_int milan_probe_bank(paddr_t paddr);
+
+#define NBANK	2
+#define NSLOT	4
+
+#define MB(n)		((n) * 1024 * 1024)
+#define MB_END(n)	(MB(n) - 1)
+#define MAGIC_4M	(4 - 1)
+#define MAGIC_4M_INV	((uint8_t)~MAGIC_4M)
+#define MAGIC_8M	(8 - 1)
+#define MAGIC_16M	(16 - 1)
+#define MAGIC_32M	(32 - 1)
+#define MAGIC_64M	(64 - 1)
+#endif
+
 /*
  * Extent maps to manage all memory space, including I/O ranges.  Allocate
- * storage for 8 regions in each, initially.  Later, iomem_malloc_safe
+ * storage for 16 regions in each, initially.  Later, iomem_malloc_safe
  * will indicate that it's safe to use malloc() to dynamically allocate
  * region descriptors.
  * This means that the fixed static storage is only used for registrating
@@ -102,7 +119,7 @@
  * The extent maps are not static!  They are used for bus address space
  * allocation.
  */
-static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
+static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)];
 struct extent *iomem_ex;
 int iomem_malloc_safe;
 
@@ -204,23 +221,67 @@
 	paddr_t		kbase;
 	u_int		kstsize;
 	paddr_t		Sysptmap_pa;
-
 #if defined(_MILANHW_)
-	/* XXX
-	 * XXX The right place todo this is probably the booter (Leo)
-	 * XXX More than 16MB memory is not yet supported on the Milan!
+	/*
 	 * The Milan Lies about the presence of TT-RAM. If you insert
 	 * 16MB it is split in 14MB ST starting at address 0 and 2MB TT RAM,
-	 * starting at address 16MB. 
+	 * starting at address 16MB as the BIOS remapping memory using MMU.
+	 *
+	 * Milan actually has four SIMM slots and each slot has two banks,
+	 * so it could have up to 8 memory segment regions.
 	 */
-	stphysize += ttphysize;
-	ttphysize  = ttphystart = 0;
-#endif
+	const paddr_t simm_base[NBANK][NSLOT] = {
+		/* slot 0-3, bank 0 */
+		{ 0x00000000, 0x04000000, 0x08000000, 0x0c000000 },
+		/* slot 0-3, bank 1 */
+		{ 0x10000000, 0x14000000, 0x18000000, 0x1c000000 }
+	};
+	int slot, bank, seg;
+	u_int mb;
+
+	/* On Milan, all RAMs are fast 32 bit so no need to reloc kernel */
+	reloc_kernel = 0;
+
+	/* probe memory region in all SIMM slots and banks */
+	seg = 0;
+	ttphysize = 0;
+	for (bank = 0; bank < 2; bank++) {
+		for (slot = 0; slot < 4; slot++) {
+			if (bank == 0 && slot == 0) {
+				/*
+				 * The first bank has at least 16MB because
+				 * the Milan's ROM bootloader requires it
+				 * to allocate ST RAM.
+				 */
+				mb = milan_probe_bank_1(simm_base[bank][slot]);
+				boot_segs[0].start = 0;
+				boot_segs[0].end   = MB(mb);
+				stphysize          = MB(mb);
+				seg++;
+			} else {
+				/*
+				 * The rest banks could be empty or
+				 * have 4, 8, 16, 32, or 64MB.
+				 */
+				mb = milan_probe_bank(simm_base[bank][slot]);
+				if (mb > 0) {
+					boot_segs[seg].start =
+					    simm_base[bank][slot];
+					boot_segs[seg].end   =
+					    simm_base[bank][slot] + MB(mb);
+					ttphysize += MB(mb);
+					seg++;
+				}
+			}
+		}
+	}
+#else /* _MILANHW_ */
 	boot_segs[0].start       = 0;
 	boot_segs[0].end         = stphysize;
 	boot_segs[1].start       = ttphystart;
 	boot_segs[1].end         = ttphystart + ttphysize;
 	boot_segs[2].start = boot_segs[2].end = 0; /* End of segments! */
+#endif
 
 	/*
 	 * The following is a hack. We do not know how much ST memory we
@@ -484,10 +545,21 @@
 	usable_segs[0].start = 0;
 	usable_segs[0].end   = stphysize;
 	usable_segs[0].free_list = VM_FREELIST_STRAM;
+#if defined(_MILANHW_)
+	for (i = 1; i < seg; i++) {
+		usable_segs[i].start = boot_segs[i].start;
+		usable_segs[i].end   = boot_segs[i].end;
+		usable_segs[i].free_list = VM_FREELIST_TTRAM;
+	}
+	for (; i < NMEM_SEGS; i++) {
+		usable_segs[i].start = usable_segs[i].end = 0;
+	}
+#else
 	usable_segs[1].start = ttphystart;
 	usable_segs[1].end   = ttphystart + ttphysize;
 	usable_segs[1].free_list = VM_FREELIST_TTRAM;
 	usable_segs[2].start = usable_segs[2].end = 0; /* End of segments! */
+#endif
 
 	if (kbase) {
 		/*
@@ -506,7 +578,7 @@
 	 * available physical memory.
 	 */
 	usable_segs[0].first_page = 0;
-	for (i = 1; usable_segs[i].start; i++) {
+	for (i = 1; i < NMEM_SEGS && usable_segs[i].start; i++) {
 		usable_segs[i].first_page  = usable_segs[i-1].first_page;
 		usable_segs[i].first_page +=
 		    (usable_segs[i-1].end - usable_segs[i-1].start) / PAGE_SIZE;
@@ -609,7 +681,7 @@
 	/*
 	 * Allocate the physical RAM from the extent map
 	 */
-	for (i = 0; boot_segs[i].end != 0; i++) {
+	for (i = 0; i < NMEM_SEGS && boot_segs[i].end != 0; i++) {
 		if (extent_alloc_region(iomem_ex, boot_segs[i].start,
 		    boot_segs[i].end - boot_segs[i].start, EX_NOWAIT)) {
 			/* XXX: Ahum, should not happen ;-) */
@@ -623,6 +695,151 @@
 	 */
 	intr_init();
 }
+
+#if defined(_MILANHW_)
+/*
+ * Probe and return available memory size in MB at specfied address.
+ * The first slot SIMM have at least 16MB, so check if it has 32 or 64 MB.
+ *
+ * Note it seems Milan does not generate bus errors on accesses against
+ * address regions where memory doesn't exist, but it returns memory images
+ * of lower address of the bank.
+ */
+static u_int
+milan_probe_bank_1(paddr_t start_paddr)
+{
+	volatile uint8_t *base;
+	u_int mb;
+	uint8_t save_16, save_32, save_64;
+
+	/* Assume that this bank has at least 16MB */
+	mb = 16;
+
+	base = (uint8_t *)start_paddr;
+
+	/* save and write a MAGIC at the end of 16MB region */
+	save_16 = base[MB_END(16)];
+	base[MB_END(16)] = MAGIC_16M;
+
+	/* check bus error at the end of 32MB region */
+	if (badbaddr(__UNVOLATILE(base + MB_END(32)), sizeof(uint8_t))) {
+		/* bus error; assume no memory there */
+		goto out16;
+	}
+
+	/* check if the 32MB region is not image of the prior 16MB region */
+	save_32 = base[MB_END(32)];
+	base[MB_END(32)] = MAGIC_32M;
+	if (base[MB_END(32)] != MAGIC_32M || base[MB_END(16)] != MAGIC_16M) {
+		/* no memory or image at the 32MB region */
+		goto out16;
+	}
+	/* we have at least 32MB */
+	mb = 32;
+
+	/* check bus error at the end of 64MB region */
+	if (badbaddr(__UNVOLATILE(base + MB_END(64)), sizeof(uint8_t))) {
+		/* bus error; assume no memory there */
+		goto out32;
+	}
+
+	/* check if the 64MB region is not image of the prior 32MB region */
+	save_64 = base[MB_END(64)];
+	base[MB_END(64)] = MAGIC_64M;
+	if (base[MB_END(64)] != MAGIC_64M || base[MB_END(32)] != MAGIC_32M) {
+		/* no memory or image at the 64MB region */
+		goto out32;
+	}
+	/* we have 64MB */
+	mb = 64;
+	base[MB_END(64)] = save_64;
+ out32:
+	base[MB_END(32)] = save_32;
+ out16:
+	base[MB_END(16)] = save_16;
+
+	return mb;
+}
+
+/*
+ * Probe and return available memory size in MB at specfied address.
+ * The rest slot could be empty so check all possible size.
+ */
+static u_int
+milan_probe_bank(paddr_t start_paddr)
+{
+	volatile uint8_t *base;
+	u_int mb;
+	uint8_t save_4, save_8, save_16;
+
+	/* The rest banks might have no memory */
+	mb = 0;
+
+	base = (uint8_t *)start_paddr;
+
+	/* check bus error at the end of 4MB region */
+	if (badbaddr(__UNVOLATILE(base + MB_END(4)), sizeof(uint8_t))) {
+		/* bus error; assume no memory there */
+		goto out;
+	}
+
+	/* check if the 4MB region has memory */
+	save_4 = base[MB_END(4)];
+	base[MB_END(4)] = MAGIC_4M_INV;
+	if (base[MB_END(4)] != MAGIC_4M_INV) {
+		/* no memory */
+		goto out;
+	}
+	base[MB_END(4)] = MAGIC_4M;
+	if (base[MB_END(4)] != MAGIC_4M) {
+		/* no memory */
+		goto out;
+	}
+	/* we have at least 4MB */
+	mb = 4;
+
+	/* check bus error at the end of 8MB region */
+	if (badbaddr(__UNVOLATILE(base + MB_END(8)), sizeof(uint8_t))) {
+		/* bus error; assume no memory there */
+		goto out4;
+	}
+
+	/* check if the 8MB region is not image of the prior 4MB region */
+	save_8 = base[MB_END(8)];
+	base[MB_END(8)] = MAGIC_8M;
+	if (base[MB_END(8)] != MAGIC_8M || base[MB_END(4)] != MAGIC_4M) {
+		/* no memory or image at the 8MB region */
+		goto out4;
+	}
+	/* we have at least 8MB */
+	mb = 8;
+
+	/* check bus error at the end of 16MB region */
+	if (badbaddr(__UNVOLATILE(base + MB_END(16)), sizeof(uint8_t))) {
+		/* bus error; assume no memory there */
+		goto out8;
+	}
+
+	/* check if the 16MB region is not image of the prior 8MB region */
+	save_16 = base[MB_END(16)];
+	base[MB_END(16)] = MAGIC_16M;
+	if (base[MB_END(16)] != MAGIC_16M || base[MB_END(8)] != MAGIC_8M) {
+		/* no memory or image at the 32MB region */
+		goto out8;
+	}
+	/* we have at least 16MB, so check more region as the first bank */
+	mb = milan_probe_bank_1(start_paddr);
+
+	base[MB_END(16)] = save_16;
+ out8:
+	base[MB_END(8)] = save_8;
+ out4:
+	base[MB_END(4)] = save_4;
+ out:
+
+	return mb;
+}
+#endif	/* _MILANHW_ */
 
 /*
  * Try to figure out on what type of machine we are running

@@ -1,4 +1,4 @@
-/*	$NetBSD: bus.c,v 1.58 2014/10/18 08:33:24 snj Exp $	*/
+/*	$NetBSD: bus.c,v 1.58.12.1 2018/03/13 13:41:13 martin Exp $	*/
 
 /*-
  * Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
 #include "opt_m68k_arch.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.58 2014/10/18 08:33:24 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.58.12.1 2018/03/13 13:41:13 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -251,7 +251,7 @@
 		u_int	*ptep, npte;
 
 		pmap_enter(pmap_kernel(), (vaddr_t)va, pa,
-		    VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED);
+		    VM_PROT_READ|VM_PROT_WRITE, VM_PROT_READ|VM_PROT_WRITE);
 
 		ptep = kvtopte(va);
 		npte = *ptep & ~PG_CMASK;
@@ -548,46 +548,203 @@
  * by bus-specific DMA map synchronization functions.
  */
 void
-_bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t off,
+_bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
     bus_size_t len, int ops)
 {
 #if defined(M68040) || defined(M68060)
-	int	i, pa_off, inc, seglen;
-	u_long	pa, end_pa;
+	bus_addr_t p, e, ps, pe;
+	bus_size_t seglen;
+	bus_dma_segment_t *seg;
+	int i;
+#endif
 
-	pa_off = t->_displacement;
+#if defined(M68020) || defined(M68030)
+#if defined(M68040) || defined(M68060)
+	if (cputype == CPU_68020 || cputype == CPU_68030)
+#endif
+		/* assume no L2 physical cache */
+		return;
+#endif
 
-	/* Flush granularity */
-	inc = (len > 1024) ? PAGE_SIZE : 16;
+#if defined(M68040) || defined(M68060)
+	/* If the whole DMA map is uncached, do nothing. */
+	if ((map->_dm_flags & BUS_DMA_COHERENT) != 0)
+		return;
 
-	for (i = 0; i < map->dm_nsegs && len > 0; i++) {
-		if (map->dm_segs[i].ds_len <= off) {
+	/* Short-circuit for unsupported `ops' */
+	if ((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) == 0)
+		return;
+
+	/*
+	 * flush/purge the cache.
+	 */
+	for (i = 0; i < map->dm_nsegs && len != 0; i++) {
+		seg = &map->dm_segs[i];
+		if (seg->ds_len <= offset) {
 			/* Segment irrelevant - before requested offset */
-			off -= map->dm_segs[i].ds_len;
+			offset -= seg->ds_len;
 			continue;
 		}
-		seglen = map->dm_segs[i].ds_len - off;
+
+		/*
+		 * Now at the first segment to sync; nail
+		 * each segment until we have exhausted the
+		 * length.
+		 */
+		seglen = seg->ds_len - offset;
 		if (seglen > len)
 			seglen = len;
-		len -= seglen;
-		pa = map->dm_segs[i].ds_addr + off - pa_off;
-		end_pa = pa + seglen;
 
-		if (inc == 16) {
-			pa &= ~15;
-			while (pa < end_pa) {
-				DCFL(pa);
-				pa += 16;
+		ps = seg->ds_addr + offset;
+		pe = ps + seglen;
+
+		if (ops & BUS_DMASYNC_PREWRITE) {
+			p = ps & ~CACHELINE_MASK;
+			e = (pe + CACHELINE_MASK) & ~CACHELINE_MASK;
+
+			/* flush cacheline */
+			while ((p < e) && (p & (CACHELINE_SIZE * 8 - 1)) != 0) {
+				DCFL(p);
+				p += CACHELINE_SIZE;
 			}
-		} else {
-			pa &= ~PGOFSET;
-			while (pa < end_pa) {
-				DCFP(pa);
-				pa += PAGE_SIZE;
+
+			/* flush cachelines per 128bytes */
+			while ((p < e) && (p & PAGE_MASK) != 0) {
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
 			}
+
+			/* flush page */
+			while (p + PAGE_SIZE <= e) {
+				DCFP(p);
+				p += PAGE_SIZE;
+			}
+
+			/* flush cachelines per 128bytes */
+			while (p + CACHELINE_SIZE * 8 <= e) {
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+				DCFL(p);
+				p += CACHELINE_SIZE;
+			}
+
+			/* flush cacheline */
+			while (p < e) {
+				DCFL(p);
+				p += CACHELINE_SIZE;
+			}
 		}
+
+		/*
+		 * Normally, the `PREREAD' flag instructs us to purge the
+		 * cache for the specified offset and length. However, if
+		 * the offset/length is not aligned to a cacheline boundary,
+		 * we may end up purging some legitimate data from the
+		 * start/end of the cache. In such a case, *flush* the
+		 * cachelines at the start and end of the required region.
+		 */
+		else if (ops & BUS_DMASYNC_PREREAD) {
+			/* flush cacheline on start boundary */
+			if (ps & CACHELINE_MASK) {
+				DCFL(ps & ~CACHELINE_MASK);
+			}
+
+			p = (ps + CACHELINE_MASK) & ~CACHELINE_MASK;
+			e = pe & ~CACHELINE_MASK;
+
+			/* purge cacheline */
+			while ((p < e) && (p & (CACHELINE_SIZE * 8 - 1)) != 0) {
+				DCPL(p);
+				p += CACHELINE_SIZE;
+			}
+
+			/* purge cachelines per 128bytes */
+			while ((p < e) && (p & PAGE_MASK) != 0) {
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+			}
+
+			/* purge page */
+			while (p + PAGE_SIZE <= e) {
+				DCPP(p);
+				p += PAGE_SIZE;
+			}
+
+			/* purge cachelines per 128bytes */
+			while (p + CACHELINE_SIZE * 8 <= e) {
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+				DCPL(p);
+				p += CACHELINE_SIZE;
+			}
+
+			/* purge cacheline */
+			while (p < e) {
+				DCPL(p);
+				p += CACHELINE_SIZE;
+			}
+
+			/* flush cacheline on end boundary */
+			if (p < pe) {
+				DCFL(p);
+			}
+		}
+		offset = 0;
+		len -= seglen;
 	}
-#endif
+#endif	/* defined(M68040) || defined(M68060) */
 }
 
 /*
@@ -667,7 +824,7 @@
 				panic("_bus_dmamem_map: size botch");
 			pmap_enter(pmap_kernel(), va, addr - offset,
 			    VM_PROT_READ | VM_PROT_WRITE,
-			    VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
+			    VM_PROT_READ | VM_PROT_WRITE);
 		}
 	}
 	pmap_update(pmap_kernel());

@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.s,v 1.110 2011/12/22 15:33:28 tsutsui Exp $	*/
+/*	$NetBSD: locore.s,v 1.110.40.1 2018/03/13 13:41:13 martin Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -399,7 +399,7 @@
 	movel	%d1,%sp@-		| Call handler
 	jbsr	_C_LABEL(milan_isa_intr)
 	addql	#8,%sp
-	INTERRUPT_RESTOREREG
+	moveml  %sp@+,%d0-%d2/%a0-%a1
 	subql	#1,_C_LABEL(idepth)
 	jra	_ASM_LABEL(rei)
 
@@ -450,7 +450,6 @@
 	tstl	_ASM_LABEL(plx_nonmi)	| milan_conf_read shortcut
 	jne	1f			| .... get out immediately
 	INTERRUPT_SAVEREG
-	moveml	%d0-%d1/%a0-%a1,%sp@-
 	movl	_C_LABEL(stio_addr),%a0	| get KVA of ST-IO area
 	movw	%a0@(PLX_PCICR),_C_LABEL(plx_status)
 	movw	#0xf900,%a0@(PLX_PCICR)	| Clear error bits
@@ -464,7 +463,6 @@
 ENTRY_NOPROFILE(lev3intr)
 ENTRY_NOPROFILE(badtrap)
 	addql	#1,_C_LABEL(idepth)
-	moveml	#0xC0C0,%sp@-		|  save scratch regs
 	INTERRUPT_SAVEREG
 	movw	%sp@(22),%sp@-		|  push exception vector info
 	clrw	%sp@-

@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap_bootstrap.c,v 1.8 2016/12/22 14:47:54 cherry Exp $	*/
+/*	$NetBSD: pmap_bootstrap.c,v 1.8.8.1 2018/03/13 13:41:13 martin Exp $	*/
 /*-
  * Copyright (c) 1999 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -113,11 +113,11 @@
 	/*
 	 * Setup physical address ranges
 	 */
-	for (i = 0; usable_segs[i + 1].start; i++)
-		;
+	for (i = 0; i < NMEM_SEGS && usable_segs[i].start; i++)
+		continue;
 	/* XXX: allow for msgbuf */
-	usable_segs[i].end -= m68k_round_page(MSGBUFSIZE);
-	msgbufpa = usable_segs[i].end;
+	usable_segs[i - 1].end -= m68k_round_page(MSGBUFSIZE);
+	msgbufpa = usable_segs[i - 1].end;
 
 	/*
 	 * Count physical memory
@@ -132,7 +132,7 @@
 	/*
 	 * Announce available memory to the VM-system
 	 */
-	for (i = 0; usable_segs[i].start; i++)
+	for (i = 0; i < NMEM_SEGS && usable_segs[i].start; i++)
 		uvm_page_physload(atop(usable_segs[i].start),
 				 atop(usable_segs[i].end),
 				 atop(usable_segs[i].start),

@@ -1,5 +1,5 @@
 #
-#	$NetBSD: MILAN.in,v 1.27 2014/07/05 09:24:23 tsutsui Exp $
+#	$NetBSD: MILAN.in,v 1.27.20.1 2018/03/13 13:41:13 martin Exp $
 #
 # Milan
 #
@@ -77,20 +77,21 @@
 
 #if defined(MILAN_PCIIDE)
 pciide* 	at pci? dev ? function ? flags 0x0000	# GENERIC pciide driver
-acardide*	at pci? dev ? function ?	# Acard IDE controllers
-aceride* 	at pci? dev ? function ?	# Acer Lab IDE controllers
-artsata*	at pci? dev ? function ?	# Intel i31244 SATA controller
-cmdide* 	at pci? dev ? function ?	# CMD tech IDE controllers
-cypide* 	at pci? dev ? function ?	# Cypress IDE controllers
-hptide* 	at pci? dev ? function ?	# Triones/HighPoint IDE controllers
-optiide* 	at pci? dev ? function ?	# Opti IDE controllers
-pdcide* 	at pci? dev ? function ?	# Promise IDE controllers
-pdcsata* 	at pci? dev ? function ?	# Promise SATA150 controllers
-satalink*	at pci? dev ? function ?	# SiI SATALink controllers
-siside* 	at pci? dev ? function ?	# SiS IDE controllers
-slide*  	at pci? dev ? function ?	# Symphony Labs IDE controllers
-viaide* 	at pci? dev ? function ?	# VIA/AMD/Nvidia IDE controllers
-#endif /* MILAN_ISAIDE */
+#acardide*	at pci? dev ? function ?	# Acard IDE controllers
+#aceride* 	at pci? dev ? function ?	# Acer Lab IDE controllers
+#artsata*	at pci? dev ? function ?	# Intel i31244 SATA controller
+#cmdide* 	at pci? dev ? function ?	# CMD tech IDE controllers
+#cypide* 	at pci? dev ? function ?	# Cypress IDE controllers
+#hptide* 	at pci? dev ? function ?	# Triones/HighPoint IDE controllers
+#optiide* 	at pci? dev ? function ?	# Opti IDE controllers
+#pdcide* 	at pci? dev ? function ?	# Promise IDE controllers
+#pdcsata* 	at pci? dev ? function ?	# Promise SATA150 controllers
+piixide* 	at pci? dev ? function ?	# Intel IDE controllers
+#satalink*	at pci? dev ? function ?	# SiI SATALink controllers
+#siside* 	at pci? dev ? function ?	# SiS IDE controllers
+#slide*  	at pci? dev ? function ?	# Symphony Labs IDE controllers
+#viaide* 	at pci? dev ? function ?	# VIA/AMD/Nvidia IDE controllers
+#endif /* MILAN_PCIIDE */
 
 atabus*		at ata? channel ?
 

@@ -1,4 +1,4 @@
-/*	$NetBSD: nvram.c,v 1.20 2015/03/06 12:41:05 christos Exp $	*/
+/*	$NetBSD: nvram.c,v 1.20.10.1 2018/03/13 13:41:13 martin Exp $	*/
 
 /*
  * Copyright (c) 1995 Leo Weppelman.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvram.c,v 1.20 2015/03/06 12:41:05 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvram.c,v 1.20.10.1 2018/03/13 13:41:13 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/conf.h>
@@ -92,11 +92,15 @@
 	/*
 	 * Check the validity of the NVram contents
 	 */
-	if (!nvram_csum_valid(nvram_csum())) {
-		printf(": Invalid checksum - re-initialized");
-		for (nreg = MC_NVRAM_START; nreg < MC_NVRAM_CSUM; nreg++)
-			mc146818_write(RTC, nreg, 0);
-		nvram_set_csum(nvram_csum());
+	/* XXX: Milan's firmware seems to use different check method */
+	if ((machineid & ATARI_MILAN) == 0) {
+		if (!nvram_csum_valid(nvram_csum())) {
+			printf(": Invalid checksum - re-initialized");
+			for (nreg = MC_NVRAM_START; nreg < MC_NVRAM_CSUM;
+			    nreg++)
+				mc146818_write(RTC, nreg, 0);
+			nvram_set_csum(nvram_csum());
+		}
 	}
 	sc = device_private(self);
 	sc->sc_dev = self;

@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.31 2017/02/02 21:53:54 rin Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.31.6.1 2018/03/13 13:41:14 martin Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -104,8 +104,10 @@
 
 /*
  * Our bootloader currently passes up to 2 segments (ST and TT ram).
+ * On the other hand, Milan has four SIMM slots with 2 banks
+ * so it could have upto 8 segments.
  */
-#define VM_PHYSSEG_MAX		(2)
+#define VM_PHYSSEG_MAX		(8)
 #define VM_PHYSSEG_STRAT	VM_PSTRAT_RANDOM
 
 #define	VM_NFREELIST		2

@@ -1,4 +1,4 @@
-/*	$NetBSD: isa_machdep.c,v 1.40 2012/10/13 17:58:54 jdc Exp $	*/
+/*	$NetBSD: isa_machdep.c,v 1.40.30.1 2018/03/13 13:41:14 martin Exp $	*/
 
 /*
  * Copyright (c) 1997 Leo Weppelman.  All rights reserved.
@@ -32,7 +32,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.40 2012/10/13 17:58:54 jdc Exp $");
+__KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.40.30.1 2018/03/13 13:41:14 martin Exp $");
 
 #include <sys/types.h>
 #include <sys/param.h>
@@ -111,17 +111,14 @@
 void
 isabusattach(device_t parent, device_t self, void *aux)
 {
-	struct isabus_softc *sc = device_private(self);
+	struct isabus_softc *sc;
 	struct isabus_attach_args	iba;
 	extern struct atari_bus_dma_tag isa_bus_dma_tag;
 	extern void isa_bus_init(void);
 
-	sc->sc_dev = self;
-
 	iba.iba_dmat	= &isa_bus_dma_tag;
 	iba.iba_iot     = leb_alloc_bus_space_tag(&bs_storage[0]);
 	iba.iba_memt    = leb_alloc_bus_space_tag(&bs_storage[1]);
-	iba.iba_ic	= &sc->sc_chipset;
 	if ((iba.iba_iot == NULL) || (iba.iba_memt == NULL)) {
 		printf("leb_alloc_bus_space_tag failed!\n");
 		return;
@@ -138,6 +135,10 @@
 #endif
 		return;
 	}
+
+	sc = device_private(self);
+	sc->sc_dev = self;
+	iba.iba_ic = &sc->sc_chipset;
 
 	printf("\n");
 	config_found_ia(self, "isabus", &iba, atariisabusprint);

@@ -1,4 +1,4 @@
-/*	$NetBSD: isa_milan.c,v 1.14 2009/03/18 10:22:25 cegger Exp $	*/
+/*	$NetBSD: isa_milan.c,v 1.14.56.1 2018/03/13 13:41:14 martin Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: isa_milan.c,v 1.14 2009/03/18 10:22:25 cegger Exp $");
+__KERNEL_RCSID(0, "$NetBSD: isa_milan.c,v 1.14.56.1 2018/03/13 13:41:14 martin Exp $");
 
 #include <sys/types.h>
 #include <sys/param.h>
@@ -122,9 +122,11 @@
 
 	s = splx(iinfo_p->ipl);
 	(void) (iinfo_p->ifunc)(iinfo_p->iarg);
-	if (vector > 7)
+	if (vector > 7) {
 		WICU(AD_8259_SLAVE, 0x60 | (vector & 7));
-	else WICU(AD_8259_MASTER, 0x60 | (vector & 7));
+		vector = IRQ_SLAVE;
+	}
+	WICU(AD_8259_MASTER, 0x60 | (vector & 7));
 	splx(s);
 }
 
@@ -140,10 +142,6 @@
 		return;
 	}
 
-	/* Ack cascade 0x60 == Specific EOI		*/
-	if (vector > 7)
-		WICU(AD_8259_MASTER, 0x60|IRQ_SLAVE);
-
 	iinfo_p = &milan_isa_iinfo[vector];
 	if (iinfo_p->ifunc == NULL) {
 		printf("milan_isa_intr: Stray interrupt: %d (mask:%04x)\n",
@@ -159,9 +157,11 @@
 	else {
 		s = splx(iinfo_p->ipl);
 		(void) (iinfo_p->ifunc)(iinfo_p->iarg);
-		if (vector > 7)
+		if (vector > 7) {
 			WICU(AD_8259_SLAVE, 0x60 | (vector & 7));
-		else WICU(AD_8259_MASTER, 0x60 | (vector & 7));
+			vector = IRQ_SLAVE;
+		}
+		WICU(AD_8259_MASTER, 0x60 | (vector & 7));
 		splx(s);
 	}
 }
@@ -209,7 +209,7 @@
 
 	iinfo_p->slot  = 0;	/* Unused on Milan */
 	iinfo_p->ihand = NULL;	/* Unused on Milan */
-	iinfo_p->ipl   = level;
+	iinfo_p->ipl   = ipl2psl_table[level];
 	iinfo_p->ifunc = ih_fun;
 	iinfo_p->iarg  = ih_arg;
 

@@ -1,4 +1,4 @@
-/*	$NetBSD: pci_machdep.c,v 1.54 2014/03/29 19:28:26 christos Exp $	*/
+/*	$NetBSD: pci_machdep.c,v 1.54.22.1 2018/03/13 13:41:14 martin Exp $	*/
 
 /*
  * Copyright (c) 1996 Leo Weppelman.  All rights reserved.
@@ -32,7 +32,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.54 2014/03/29 19:28:26 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.54.22.1 2018/03/13 13:41:14 martin Exp $");
 
 #include "opt_mbtype.h"
 
@@ -49,6 +49,7 @@
 
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
+#include <dev/pci/pcidevs.h>
 
 #include <uvm/uvm_extern.h>
 
@@ -449,6 +450,24 @@
 	/*
 	 * On the Milan, we accept the BIOS's choice.
 	 */
+	/* ..except the secondary IDE interrupt that the BIOS doesn't setup. */
+#define PIIX_PCIB_MBIRQ0	0x70
+	if ((PCI_VENDOR(id) == PCI_VENDOR_INTEL) &&
+	    (PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_82371FB_ISA)) {
+		/*
+		 * Set Interrupt Routing for MBIRQ0 to IRQ15.
+		 * Note Milan's ROM bootloader v1.2 and v1.4 incorrectly
+		 * set MBIRQ0 to IRQ14 (not 15) and unused MBIRQ1 to IRQ 15,
+		 * so explicitly disable MBIRQ1.
+		 */
+		csr = pci_conf_read(pc, tag, PIIX_PCIB_MBIRQ0);
+		csr &= ~0x000ffff;
+		csr |=  0x000800f;	/* MBIRQ1: disable, MBIRQ0: IRQ15 */
+		pci_conf_write(pc, tag, PIIX_PCIB_MBIRQ0, csr);
+#ifdef DEBUG_PCI_MACHDEP
+		printf("\npcib0: enable and route MBIRQ0 to irq 15\n");
+#endif
+	}
 #endif
     }
 

@@ -1,4 +1,4 @@
-/*	$NetBSD: pci_milan.c,v 1.14 2015/10/02 05:22:50 msaitoh Exp $	*/
+/*	$NetBSD: pci_milan.c,v 1.14.10.1 2018/03/13 13:41:14 martin Exp $	*/
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_milan.c,v 1.14 2015/10/02 05:22:50 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_milan.c,v 1.14.10.1 2018/03/13 13:41:14 martin Exp $");
 
 #include <sys/types.h>
 #include <sys/param.h>
@@ -120,19 +120,41 @@
 
 /*
  * VGA related stuff...
- * XXX: Currently, you can only boot the Milan through loadbsd.ttp, hence the
- *      text mode ;-)
+ *  
  * It looks like the Milan BIOS is initializing the VGA card in a reasonably
  * standard text mode. However, the screen mode is 640*480 instead of 640*400.
  * Since wscons does not handle the right by default, the card is reprogrammed
  * to 640*400 using only 'standard' VGA registers (I hope!). So this ought to
  * work on cards other than the S3Trio card I have tested it on.
  */
-static u_char crt_tab[] = {
-	0x60, 0x53, 0x4f, 0x14, 0x56, 0x05, 0xc1, 0x1f,
-	0x00, 0x4f, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00,
-	0x98, 0x3d, 0x8f, 0x28, 0x0f, 0x8f, 0xc1, 0xc3,
-	0xff };
+static const uint8_t crt_tab[] = {
+	/* taken from vga_crtc[] in sys/dev/ic/vga_subr.c */
+	0x5f,	/* 00: horizontal total */
+	0x4f,	/* 01: horizontal display-enable end */
+	0x50,	/* 02: start horizontal blanking */
+	0x82,	/* 03: display skew control / end horizontal blanking */
+	0x55,	/* 04: start horizontal retrace pulse */
+	0x81,	/* 05: horizontal retrace delay / end horizontal retrace */
+	0xbf,	/* 06: vertical total */
+	0x1f,	/* 07: overflow register */
+	0x00,	/* 08: preset row scan */
+	0x4f,	/* 09: overflow / maximum scan line */
+	0x0d,	/* 0A: cursor off / cursor start */
+	0x0e,	/* 0B: cursor skew / cursor end */
+	0x00,	/* 0C: start regenerative buffer address high */
+	0x00,	/* 0D: start regenerative buffer address low */
+	0x00,	/* 0E: cursor location high */
+	0x00,	/* 0F: cursor location low */
+	0x9c,	/* 10: vertical retrace start */
+	0x8e,	/* 11: vertical interrupt / vertical retrace end */
+	0x8f,	/* 12: vertical display enable end */
+	0x28,	/* 13: logical line width */
+	0x00,	/* 14: underline location */
+	0x96,	/* 15: start vertical blanking */
+	0xb9,	/* 16: end vertical blanking */
+	0xa3,	/* 17: CRT mode control */
+	0xff	/* 18: line compare */
+};
 
 /*
  * XXX: Why are we repeating this everywhere! (Leo)

@@ -1,5 +1,6 @@
-# $NetBSD: Makefile,v 1.3 2003/06/28 09:09:53 he Exp $
+# $NetBSD: Makefile,v 1.3.188.1 2018/03/13 13:41:13 martin Exp $
 
 BTYPE=MILAN
+LINKS=	${BINDIR}/sdb00t.ahdi ${BINDIR}/wdb00t.ahdi
 
 .include <../Makefile.xxb>

@@ -1,5 +1,6 @@
-# $NetBSD: Makefile,v 1.3 2003/06/28 09:09:54 he Exp $
+# $NetBSD: Makefile,v 1.3.188.1 2018/03/13 13:41:13 martin Exp $
 
 BTYPE=MILAN
+LINKS=	${BINDIR}/sdboot ${BINDIR}/wdboot
 
 .include <../Makefile.sdboot>

@@ -1,4 +1,4 @@
-/*	$NetBSD: fd.c,v 1.110 2015/12/08 20:36:15 christos Exp $	*/
+/*	$NetBSD: fd.c,v 1.110.10.1 2018/03/13 13:41:13 martin Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2003, 2008 The NetBSD Foundation, Inc.
@@ -81,7 +81,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fd.c,v 1.110 2015/12/08 20:36:15 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fd.c,v 1.110.10.1 2018/03/13 13:41:13 martin Exp $");
 
 #include "opt_ddb.h"
 
@@ -460,14 +460,16 @@
 			 * Atari has a different ordening, defaults to 1.44
 			 */
 			fa.fa_deftype = &fd_types[2];
+			 /* Atari also configures ISA fdc(4) as "fdcisa" */
+			(void)config_found_ia(fdc->sc_dev, "fdcisa", (void *)&fa, fdprint);
 #else
 			/*
 			 * Default to 1.44MB on Alpha and BeBox.  How do we tell
 			 * on these platforms?
 			 */
 			fa.fa_deftype = &fd_types[0];
-#endif
 			(void)config_found_ia(fdc->sc_dev, "fdc", (void *)&fa, fdprint);
+#endif
 		}
 	}
 	fdc->sc_state = DEVIDLE;