 @@ -1,14 +1,14 @@
-/*	$NetBSD: isadma.c,v 1.66 2010/11/13 13:52:03 uebayasi Exp $	*/
+/*	$NetBSD: isadma.c,v 1.66.52.1 2018/06/07 19:39:54 martin Exp $	*/
 /*-
  * Copyright (c) 1997, 1998, 2000 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -25,53 +25,57 @@
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Device driver for the ISA on-board DMA controller.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: isadma.c,v 1.66 2010/11/13 13:52:03 uebayasi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: isadma.c,v 1.66.52.1 2018/06/07 19:39:54 martin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/proc.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/bus.h>
 #include <dev/isa/isareg.h>
 #include <dev/isa/isavar.h>
 #include <dev/isa/isadmavar.h>
 #include <dev/isa/isadmareg.h>
 struct isa_mem *isa_mem_head;
 /*
- * High byte of DMA address is stored in this DMAPG register for
+ * DMA Channel to Address Page Register offset mapping
  * the Nth DMA channel.
  * Offset from IO_DMAPG is stored in this 2D array -- first dimension is
  * the DMA controller, second dimension is the DMA channel.
+ *
  * e.g. dmapageport[0][1] gives us the offset for DMA ch 1 on DMA1
  */
-static int dmapageport[2][4] = {
+static const int dmapageport[2][4] = {
-	{0x7, 0x3, 0x1, 0x2},
+	{0x6, 0x2, 0x0, 0x1},
-	{0xf, 0xb, 0x9, 0xa}
+	{0xe, 0xa, 0x8, 0x9}
 };
-static u_int8_t dmamode[] = {
+static const u_int8_t dmamode[] = {
 	/* write to device/read from device */
 	DMA37MD_READ | DMA37MD_SINGLE,
 	DMA37MD_WRITE | DMA37MD_SINGLE,
 	/* write to device/read from device */
 	DMA37MD_READ | DMA37MD_DEMAND,
 	DMA37MD_WRITE | DMA37MD_DEMAND,
 	/* write to device/read from device - DMAMODE_LOOP */
 	DMA37MD_READ | DMA37MD_SINGLE | DMA37MD_LOOP,
 	DMA37MD_WRITE | DMA37MD_SINGLE | DMA37MD_LOOP,
 	/* write to device/read from device - DMAMODE_LOOPDEMAND */
 @@ -159,27 +163,27 @@ _isa_dmainit(struct isa_dma_state *ids,
 	} else {
 		ids->ids_bst = bst;
 		ids->ids_dmat = dmat;
 		/*
 		 * Map the registers used by the ISA DMA controller.
 		 */
 		if (bus_space_map(ids->ids_bst, IO_DMA1, DMA1_IOSIZE, 0,
 		    &ids->ids_dma1h))
 			panic("_isa_dmainit: unable to map DMA controller #1");
 		if (bus_space_map(ids->ids_bst, IO_DMA2, DMA2_IOSIZE, 0,
 		    &ids->ids_dma2h))
 			panic("_isa_dmainit: unable to map DMA controller #2");
-		if (bus_space_map(ids->ids_bst, IO_DMAPG, 0xf, 0,
+		if (bus_space_map(ids->ids_bst, IO_DMAPG, DMAPG_IOSIZE, 0,
 		    &ids->ids_dmapgh))
 			panic("_isa_dmainit: unable to map DMA page registers");
 		/*
 		 * All 8 DMA channels start out "masked".
 		 */
 		ids->ids_masked = 0xff;
 		/*
 		 * Initialize the max transfer size for each channel, if
 		 * it is not initialized already (i.e. by a bus-dependent
 		 * front-end).
 		 */
 @@ -201,27 +205,27 @@ _isa_dmainit(struct isa_dma_state *ids,
+}
 void
 _isa_dmadestroy(struct isa_dma_state *ids)
+{
 	if (!ids->ids_initialized)
 		return;
 	_isa_dmacascade_stop(ids, 4);
 	/*
 	 * Unmap the registers used by the ISA DMA controller.
 	 */
-	bus_space_unmap(ids->ids_bst, ids->ids_dmapgh, 0xf);
+	bus_space_unmap(ids->ids_bst, ids->ids_dmapgh, DMAPG_IOSIZE);
 	bus_space_unmap(ids->ids_bst, ids->ids_dma2h, DMA2_IOSIZE);
 	bus_space_unmap(ids->ids_bst, ids->ids_dma1h, DMA1_IOSIZE);
 	ids->ids_initialized = 0;
+}
 /*
  * _isa_dmacascade(): program 8237 DMA controller channel to accept
  * external dma control by a board.
  */
 int
 _isa_dmacascade(struct isa_dma_state *ids, int chan)
+{

 @@ -1,14 +1,14 @@
-/*	$NetBSD: isadmareg.h,v 1.8 2008/04/28 20:23:52 martin Exp $	*/
+/*	$NetBSD: isadmareg.h,v 1.8.80.1 2018/06/07 19:39:54 martin Exp $	*/
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -37,26 +37,29 @@
 /*
  * By default, ISA DMA controllers can do 64k or 128k transfers, depending
  * on the width of the channel being used.  However, this may be modified
  * by our parent based on bus constraints, etc.  Clients of ISA DMA should
  * query the ISA DMA to determine the maximum transfer size allowed.
  */
 #define	ISA_DMA_MAXSIZE_8BIT	(64 * 1024)
 #define	ISA_DMA_MAXSIZE_16BIT	(ISA_DMA_MAXSIZE_8BIT * 2)
 #define	ISA_DMA_MAXSIZE_DEFAULT(chan)					\
 	(((chan) & 4) ? ISA_DMA_MAXSIZE_16BIT : ISA_DMA_MAXSIZE_8BIT)
 /* DMA Page Address Registers size */
 #define	DMAPG_IOSIZE	(1*15)
 /*
  * Register definitions for DMA controller 1 (channels 0..3):
  */
 #define	DMA1_CHN(c)	(1*(2*(c)))		/* addr reg for channel c */
 #define	DMA1_SR		(1*8)			/* status register */
 #define	DMA1_SMSK	(1*10)			/* single mask register */
 #define	DMA1_MODE	(1*11)			/* mode register */
 #define	DMA1_FFC	(1*12)			/* clear first/last FF */
 #define	DMA1_MASK	(1*15)			/* mask register */
 #define	DMA1_IOSIZE	(1*16)
 /*

 @@ -1,14 +1,14 @@
-/*	$NetBSD: isareg.h,v 1.9 2005/12/11 12:22:02 christos Exp $	*/
+/*	$NetBSD: isareg.h,v 1.9.156.1 2018/06/07 19:39:54 martin Exp $	*/
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * William Jolitz.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -45,27 +45,27 @@
 #ifndef IO_ISABEGIN
 #define	IO_ISABEGIN	0x000		/* 0x000 - Beginning of I/O Registers */
 		/* CPU Board */
 #define	IO_DMA1		0x000		/* 8237A DMA Controller #1 */
 #define	IO_ICU1		0x020		/* 8259A Interrupt Controller #1 */
 #define	IO_PMP1		0x026		/* 82347 Power Management Peripheral */
 #define	IO_TIMER1	0x040		/* 8253 Timer #1 */
 #define	IO_TIMER2	0x048		/* 8253 Timer #2 (EISA only) */
 #define	IO_KBD		0x060		/* 8042 Keyboard */
 #define	IO_PPI		0x061		/* Programmable Peripheral Interface */
 #define	IO_RTC		0x070		/* RTC */
 #define	IO_NMI		IO_RTC		/* NMI Control */
-#define	IO_DMAPG	0x080		/* DMA Page Registers */
+#define	IO_DMAPG	0x081		/* DMA Page Registers */
 #define	IO_ICU2		0x0A0		/* 8259A Interrupt Controller #2 */
 #define	IO_DMA2		0x0C0		/* 8237A DMA Controller #2 */
 #define	IO_NPX		0x0F0		/* Numeric Coprocessor */
 		/* Cards */
 					/* 0x100 - 0x16F Open */
 #define	IO_WD2		0x170		/* Secondary Fixed Disk Controller */
 #define	IO_PMP2		0x178		/* 82347 Power Management Peripheral */
 					/* 0x17A - 0x1EF Open */
 #define	IO_WD1		0x1f0		/* Primary Fixed Disk Controller */