 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpufunc.S,v 1.33 2018/07/21 06:09:13 maxv Exp $	*/
+/*	$NetBSD: cpufunc.S,v 1.34 2018/12/22 21:27:22 cherry Exp $	*/
 /*
  * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -53,81 +53,116 @@ ENTRY(x86_lfence)
 	ret
 END(x86_lfence)
 ENTRY(x86_sfence)
 	sfence
 	ret
 END(x86_sfence)
 ENTRY(x86_mfence)
 	mfence
 	ret
 END(x86_mfence)
 /*
  * These functions below should always be accessed via the corresponding wrapper
  * function names defined in x86/include/cpufunc.h and exported as WEAK_ALIAS()
+ *
  * We use this rather roundabout method so that a runtime wrapper function may
  * be made available for PVHVM, which could override both native and PV aliases
  * and decide which to invoke at run time.
  */
 WEAK_ALIAS(invlpg, amd64_invlpg)
 WEAK_ALIAS(lidt, amd64_lidt)
 WEAK_ALIAS(lldt, amd64_lldt)
 WEAK_ALIAS(ltr, amd64_ltr)
 WEAK_ALIAS(lcr0, amd64_lcr0)
 WEAK_ALIAS(rcr0, amd64_rcr0)
 WEAK_ALIAS(rcr2, amd64_rcr2)
 WEAK_ALIAS(lcr2, amd64_lcr2)
 WEAK_ALIAS(rcr3, amd64_rcr3)
 WEAK_ALIAS(lcr3, amd64_lcr3)
 WEAK_ALIAS(tlbflush, amd64_tlbflush)
 WEAK_ALIAS(tlbflushg, amd64_tlbflushg)
 WEAK_ALIAS(rdr0, amd64_rdr0)
 WEAK_ALIAS(ldr0, amd64_ldr0)
 WEAK_ALIAS(rdr1, amd64_rdr1)
 WEAK_ALIAS(ldr1, amd64_ldr1)
 WEAK_ALIAS(rdr2, amd64_rdr2)
 WEAK_ALIAS(ldr2, amd64_ldr2)
 WEAK_ALIAS(rdr3, amd64_rdr3)
 WEAK_ALIAS(ldr3, amd64_ldr3)
 WEAK_ALIAS(rdr6, amd64_rdr6)
 WEAK_ALIAS(ldr6, amd64_ldr6)
 WEAK_ALIAS(rdr7, amd64_rdr7)
 WEAK_ALIAS(ldr7, amd64_ldr7)
 WEAK_ALIAS(wbinvd, amd64_wbinvd)
 #ifndef XEN
-ENTRY(invlpg)
+ENTRY(amd64_invlpg)
 	invlpg	(%rdi)
 	ret
-END(invlpg)
+END(amd64_invlpg)
-ENTRY(lidt)
+ENTRY(amd64_lidt)
 	lidt	(%rdi)
 	ret
-END(lidt)
+END(amd64_lidt)
-ENTRY(lldt)
+ENTRY(amd64_lldt)
 	cmpl	%edi, CPUVAR(CURLDT)
 	jne	1f
 	ret
 :
 	movl	%edi, CPUVAR(CURLDT)
 	lldt	%di
 	ret
-END(lldt)
+END(amd64_lldt)
-ENTRY(ltr)
+ENTRY(amd64_ltr)
 	ltr	%di
 	ret
-END(ltr)
+END(amd64_ltr)
-ENTRY(lcr0)
+ENTRY(amd64_lcr0)
 	movq	%rdi, %cr0
 	ret
-END(lcr0)
+END(amd64_lcr0)
-ENTRY(rcr0)
+ENTRY(amd64_rcr0)
 	movq	%cr0, %rax
 	ret
-END(rcr0)
+END(amd64_rcr0)
-ENTRY(lcr2)
+ENTRY(amd64_lcr2)
 	movq	%rdi, %cr2
 	ret
-END(lcr2)
+END(amd64_lcr2)
-ENTRY(rcr2)
+ENTRY(amd64_rcr2)
 	movq	%cr2, %rax
 	ret
-END(rcr2)
+END(amd64_rcr2)
-ENTRY(lcr3)
+ENTRY(amd64_lcr3)
 	movq	%rdi, %cr3
 	ret
-END(lcr3)
+END(amd64_lcr3)
-ENTRY(rcr3)
+ENTRY(amd64_rcr3)
 	movq	%cr3, %rax
 	ret
-END(rcr3)
+END(amd64_rcr3)
 #endif
 ENTRY(lcr4)
 	movq	%rdi, %cr4
 	ret
 END(lcr4)
 ENTRY(rcr4)
 	movq	%cr4, %rax
 	ret
 END(rcr4)
 ENTRY(lcr8)
 @@ -149,103 +184,103 @@ END(rcr8)
  *	System Programming, section 9.10, "Invalidating the
  * Translation Lookaside Buffers (TLBS)":
  * "The following operations invalidate all TLB entries, irrespective
  * of the setting of the G flag:
  * ...
  * "(P6 family processors only): Writing to control register CR4 to
  * modify the PSE, PGE, or PAE flag."
+ *
  * (the alternatives not quoted above are not an option here.)
+ *
  * If PGE is not in use, we reload CR3.
  */
 #ifndef XEN
-ENTRY(tlbflushg)
+ENTRY(amd64_tlbflushg)
 	movq	%cr4, %rax
 	testq	$CR4_PGE, %rax
 	jz	1f
 	movq	%rax, %rdx
 	andq	$~CR4_PGE, %rdx
 	movq	%rdx, %cr4
 	movq	%rax, %cr4
 	ret
-END(tlbflushg)
+END(amd64_tlbflushg)
-ENTRY(tlbflush)
+ENTRY(amd64_tlbflush)
 :
 	movq	%cr3, %rax
 	movq	%rax, %cr3
 	ret
-END(tlbflush)
+END(amd64_tlbflush)
-ENTRY(ldr0)
+ENTRY(amd64_ldr0)
 	movq	%rdi, %dr0
 	ret
-END(ldr0)
+END(amd64_ldr0)
-ENTRY(rdr0)
+ENTRY(amd64_rdr0)
 	movq	%dr0, %rax
 	ret
-END(rdr0)
+END(amd64_rdr0)
-ENTRY(ldr1)
+ENTRY(amd64_ldr1)
 	movq	%rdi, %dr1
 	ret
-END(ldr1)
+END(amd64_ldr1)
-ENTRY(rdr1)
+ENTRY(amd64_rdr1)
 	movq	%dr1, %rax
 	ret
-END(rdr1)
+END(amd64_rdr1)
-ENTRY(ldr2)
+ENTRY(amd64_ldr2)
 	movq	%rdi, %dr2
 	ret
-END(ldr2)
+END(amd64_ldr2)
-ENTRY(rdr2)
+ENTRY(amd64_rdr2)
 	movq	%dr2, %rax
 	ret
-END(rdr2)
+END(amd64_rdr2)
-ENTRY(ldr3)
+ENTRY(amd64_ldr3)
 	movq	%rdi, %dr3
 	ret
-END(ldr3)
+END(amd64_ldr3)
-ENTRY(rdr3)
+ENTRY(amd64_rdr3)
 	movq	%dr3, %rax
 	ret
-END(rdr3)
+END(amd64_rdr3)
-ENTRY(ldr6)
+ENTRY(amd64_ldr6)
 	movq	%rdi, %dr6
 	ret
-END(ldr6)
+END(amd64_ldr6)
-ENTRY(rdr6)
+ENTRY(amd64_rdr6)
 	movq	%dr6, %rax
 	ret
-END(rdr6)
+END(amd64_rdr6)
-ENTRY(ldr7)
+ENTRY(amd64_ldr7)
 	movq	%rdi, %dr7
 	ret
-END(ldr7)
+END(amd64_ldr7)
-ENTRY(rdr7)
+ENTRY(amd64_rdr7)
 	movq	%dr7, %rax
 	ret
-END(rdr7)
+END(amd64_rdr7)
 ENTRY(x86_disable_intr)
 	cli
 	ret
 END(x86_disable_intr)
 ENTRY(x86_enable_intr)
 	sti
 	ret
 END(x86_enable_intr)
 ENTRY(x86_read_flags)
 	pushfq

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpufunc.S,v 1.25 2018/10/18 04:11:14 cherry Exp $	*/
+/*	$NetBSD: cpufunc.S,v 1.26 2018/12/22 21:27:22 cherry Exp $	*/
 /*-
  * Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -28,65 +28,77 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Functions to provide access to i386-specific instructions.
+ *
  * These are shared with NetBSD/xen.
  */
 #include <sys/errno.h>
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.S,v 1.25 2018/10/18 04:11:14 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.S,v 1.26 2018/12/22 21:27:22 cherry Exp $");
 #include "opt_xen.h"
 #include <machine/specialreg.h>
 #include <machine/segments.h>
 #include "assym.h"
 /*
  * These functions below should always be accessed via the corresponding wrapper
  * function names defined in x86/include/cpufunc.h and exported as WEAK_ALIAS()
+ *
  * We use this rather roundabout method so that a runtime wrapper function may
  * be made available for PVHVM, which could override both native and PV aliases
  * and decide which to invoke at run time.
  */
 WEAK_ALIAS(lidt, i386_lidt)
 WEAK_ALIAS(rcr3, i386_rcr3)
 ENTRY(x86_lfence)
 	lock
 	addl	$0, -4(%esp)
 	ret
 END(x86_lfence)
 ENTRY(x86_sfence)
 	lock
 	addl	$0, -4(%esp)
 	ret
 END(x86_sfence)
 ENTRY(x86_mfence)
 	lock
 	addl	$0, -4(%esp)
 	ret
 END(x86_mfence)
 #ifndef XEN
-ENTRY(lidt)
+ENTRY(i386_lidt)
 	movl	4(%esp), %eax
 	lidt	(%eax)
 	ret
-END(lidt)
+END(i386_lidt)
 #endif /* XEN */
-ENTRY(rcr3)
+ENTRY(i386_rcr3)
 	movl	%cr3, %eax
 	ret
-END(rcr3)
+END(i386_rcr3)
 ENTRY(lcr4)
 	movl	4(%esp), %eax
 	movl	%eax, %cr4
 	ret
 END(lcr4)
 ENTRY(rcr4)
 	movl	%cr4, %eax
 	ret
 END(rcr4)
 ENTRY(x86_read_flags)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: i386func.S,v 1.18 2016/11/27 14:49:21 kamil Exp $	*/
+/*	$NetBSD: i386func.S,v 1.19 2018/12/22 21:27:22 cherry Exp $	*/
 /*-
  * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -26,194 +26,227 @@
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Functions to provide access to i386-specific instructions.
+ *
  * These are _not_ shared with NetBSD/xen.
  */
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: i386func.S,v 1.18 2016/11/27 14:49:21 kamil Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i386func.S,v 1.19 2018/12/22 21:27:22 cherry Exp $");
 #include <machine/specialreg.h>
 #include <machine/segments.h>
 #include "assym.h"
-ENTRY(invlpg)
+/*
  * These functions below should always be accessed via the corresponding wrapper
  * function names defined in x86/include/cpufunc.h and exported as WEAK_ALIAS()
+ *
  * We use this rather roundabout method so that a runtime wrapper function may
  * be made available for PVHVM, which could override both native and PV aliases
  * and decide which to invoke at run time.
  */
 WEAK_ALIAS(invlpg, i386_invlpg)
 WEAK_ALIAS(lldt, i386_lldt)
 WEAK_ALIAS(ltr, i386_ltr)
 WEAK_ALIAS(lcr0, i386_lcr0)
 WEAK_ALIAS(rcr0, i386_rcr0)
 WEAK_ALIAS(lcr3, i386_lcr3)
 WEAK_ALIAS(tlbflush, i386_tlbflush)
 WEAK_ALIAS(tlbflushg, i386_tlbflushg)
 WEAK_ALIAS(rdr0, i386_rdr0)
 WEAK_ALIAS(ldr0, i386_ldr0)
 WEAK_ALIAS(rdr1, i386_rdr1)
 WEAK_ALIAS(ldr1, i386_ldr1)
 WEAK_ALIAS(rdr2, i386_rdr2)
 WEAK_ALIAS(ldr2, i386_ldr2)
 WEAK_ALIAS(rdr3, i386_rdr3)
 WEAK_ALIAS(ldr3, i386_ldr3)
 WEAK_ALIAS(rdr6, i386_rdr6)
 WEAK_ALIAS(ldr6, i386_ldr6)
 WEAK_ALIAS(rdr7, i386_rdr7)
 WEAK_ALIAS(ldr7, i386_ldr7)
 WEAK_ALIAS(rcr2, i386_rcr2)
 WEAK_ALIAS(lcr2, i386_lcr2)
 WEAK_ALIAS(wbinvd, i386_wbinvd)
 ENTRY(i386_invlpg)
 	movl	4(%esp), %eax
 	invlpg	(%eax)
 	ret
-END(invlpg)
+END(i386_invlpg)
-ENTRY(lldt)
+ENTRY(i386_lldt)
 	movl	4(%esp), %eax
 	cmpl	%eax, CPUVAR(CURLDT)
 	jne	1f
 	ret
 :
 	movl	%eax, CPUVAR(CURLDT)
 	lldt	%ax
 	ret
-END(lldt)
+END(i386_lldt)
-ENTRY(ltr)
+ENTRY(i386_ltr)
 	movl	4(%esp), %eax
 	ltr	%ax
 	ret
-END(ltr)
+END(i386_ltr)
-ENTRY(lcr0)
+ENTRY(i386_lcr0)
 	movl	4(%esp), %eax
 	movl	%eax, %cr0
 	ret
-END(lcr0)
+END(i386_lcr0)
-ENTRY(rcr0)
+ENTRY(i386_rcr0)
 	movl	%cr0, %eax
 	ret
-END(rcr0)
+END(i386_rcr0)
-ENTRY(lcr3)
+ENTRY(i386_lcr3)
 	movl	4(%esp), %eax
 	movl	%eax, %cr3
 	ret
-END(lcr3)
+END(i386_lcr3)
 /*
  * Big hammer: flush all TLB entries, including ones from PTE's
  * with the G bit set.  This should only be necessary if TLB
  * shootdown falls far behind.
+ *
  * Intel Architecture Software Developer's Manual, Volume 3,
  *	System Programming, section 9.10, "Invalidating the
  * Translation Lookaside Buffers (TLBS)":
  * "The following operations invalidate all TLB entries, irrespective
  * of the setting of the G flag:
  * ...
  * "(P6 family processors only): Writing to control register CR4 to
  * modify the PSE, PGE, or PAE flag."
+ *
  * (the alternatives not quoted above are not an option here.)
+ *
  * If PGE is not in use, we reload CR3.  Check for the PGE feature
  * first since i486 does not have CR4.  Note: the feature flag may
  * be present while the actual PGE functionality not yet enabled.
  */
-ENTRY(tlbflushg)
+ENTRY(i386_tlbflushg)
 	testl	$CPUID_PGE, _C_LABEL(cpu_feature)
 	jz	1f
 	movl	%cr4, %eax
 	testl	$CR4_PGE, %eax
 	jz	1f
 	movl	%eax, %edx
 	andl	$~CR4_PGE, %edx
 	movl	%edx, %cr4
 	movl	%eax, %cr4
 	ret
-END(tlbflushg)
+END(i386_tlbflushg)
-ENTRY(tlbflush)
+ENTRY(i386_tlbflush)
 :
 	movl	%cr3, %eax
 	movl	%eax, %cr3
 	ret
-END(tlbflush)
+END(i386_tlbflush)
-ENTRY(ldr0)
+ENTRY(i386_ldr0)
 	movl	4(%esp), %eax
 	movl	%eax, %dr0
 	ret
-END(ldr0)
+END(i386_ldr0)
-ENTRY(rdr0)
+ENTRY(i386_rdr0)
 	movl	%dr0, %eax
 	ret
-END(rdr0)
+END(i386_rdr0)
-ENTRY(ldr1)
+ENTRY(i386_ldr1)
 	movl	4(%esp), %eax
 	movl	%eax, %dr1
 	ret
-END(ldr1)
+END(i386_ldr1)
-ENTRY(rdr1)
+ENTRY(i386_rdr1)
 	movl	%dr1, %eax
 	ret
-END(rdr1)
+END(i386_rdr1)
-ENTRY(ldr2)
+ENTRY(i386_ldr2)
 	movl	4(%esp), %eax
 	movl	%eax, %dr2
 	ret
-END(ldr2)
+END(i386_ldr2)
-ENTRY(rdr2)
+ENTRY(i386_rdr2)
 	movl	%dr2, %eax
 	ret
-END(rdr2)
+END(i386_rdr2)
-ENTRY(ldr3)
+ENTRY(i386_ldr3)
 	movl	4(%esp), %eax
 	movl	%eax, %dr3
 	ret
-END(ldr3)
+END(i386_ldr3)
-ENTRY(rdr3)
+ENTRY(i386_rdr3)
 	movl	%dr3, %eax
 	ret
-END(rdr3)
+END(i386_rdr3)
-ENTRY(ldr6)
+ENTRY(i386_ldr6)
 	movl	4(%esp), %eax
 	movl	%eax, %dr6
 	ret
-END(ldr6)
+END(i386_ldr6)
-ENTRY(rdr6)
+ENTRY(i386_rdr6)
 	movl	%dr6, %eax
 	ret
-END(rdr6)
+END(i386_rdr6)
-ENTRY(ldr7)
+ENTRY(i386_ldr7)
 	movl	4(%esp), %eax
 	movl	%eax, %dr7
 	ret
-END(ldr7)
+END(i386_ldr7)
-ENTRY(rdr7)
+ENTRY(i386_rdr7)
 	movl	%dr7, %eax
 	ret
-END(rdr7)
+END(i386_rdr7)
-ENTRY(rcr2)
+ENTRY(i386_rcr2)
 	movl	%cr2, %eax
 	ret
-END(rcr2)
+END(i386_rcr2)
-ENTRY(lcr2)
+ENTRY(i386_lcr2)
 	movl	4(%esp), %eax
 	movl	%eax, %cr2
 	ret
-END(lcr2)
+END(i386_lcr2)
-ENTRY(wbinvd)
+ENTRY(i386_wbinvd)
 	wbinvd
 	ret
-END(wbinvd)
+END(i386_wbinvd)
 ENTRY(x86_disable_intr)
 	cli
 	ret
 END(x86_disable_intr)
 ENTRY(x86_enable_intr)
 	sti
 	ret
 END(x86_enable_intr)
 /*
  * void lgdt(struct region_descriptor *rdp);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: xenfunc.c,v 1.22 2018/10/18 04:17:18 cherry Exp $	*/
+/*	$NetBSD: xenfunc.c,v 1.23 2018/12/22 21:27:22 cherry Exp $	*/
 /*
  * Copyright (c) 2004 Christian Limpach.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -16,55 +16,121 @@
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: xenfunc.c,v 1.22 2018/10/18 04:17:18 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: xenfunc.c,v 1.23 2018/12/22 21:27:22 cherry Exp $");
 #include <sys/param.h>
 #include <uvm/uvm_extern.h>
 #include <machine/intr.h>
 #include <machine/vmparam.h>
 #include <machine/pmap.h>
 #include <xen/xen.h>
 #include <xen/hypervisor.h>
 //#include <xen/evtchn.h>
 #include <xen/xenpmap.h>
 #include <machine/pte.h>
 #define MAX_XEN_IDT 128
 void xen_set_ldt(vaddr_t, uint32_t);
 /*
  * We don't need to export these declarations, since they are used via
  * linker aliasing. They should always be accessed via the
  * corresponding wrapper function names defined in
  * x86/include/cpufunc.h and exported as __weak_alias()
+ *
  * We use this rather roundabout method so that a runtime wrapper
  * function may be made available for PVHVM, which could override both
  * native and PV aliases and decide which to invoke at run time.
  */
 void xen_invlpg(vaddr_t);
 void xen_lidt(struct region_descriptor *);
 void xen_lldt(u_short);
 void xen_ltr(u_short);
 void xen_lcr0(u_long);
 u_long xen_rcr0(void);
 void xen_tlbflush(void);
 void xen_tlbflushg(void);
 register_t xen_rdr0(void);
 void xen_ldr0(register_t);
 register_t xen_rdr1(void);
 void xen_ldr1(register_t);
 register_t xen_rdr2(void);
 void xen_ldr2(register_t);
 register_t xen_rdr3(void);
 void xen_ldr3(register_t);
 register_t xen_rdr6(void);
 void xen_ldr6(register_t);
 register_t xen_rdr7(void);
 void xen_ldr7(register_t);
 void xen_wbinvd(void);
 vaddr_t xen_rcr2(void);
 __weak_alias(invlpg, xen_invlpg);
 __weak_alias(lidt, xen_lidt);
 __weak_alias(lldt, xen_lldt);
 __weak_alias(ltr, xen_ltr);
 __weak_alias(lcr0, xen_lcr0);
 __weak_alias(rcr0, xen_rcr0);
 __weak_alias(tlbflush, xen_tlbflush);
 __weak_alias(tlbflushg, xen_tlbflushg);
 __weak_alias(rdr0, xen_rdr0);
 __weak_alias(ldr0, xen_ldr0);
 __weak_alias(rdr1, xen_rdr1);
 __weak_alias(ldr1, xen_ldr1);
 __weak_alias(rdr2, xen_rdr2);
 __weak_alias(ldr2, xen_ldr2);
 __weak_alias(rdr3, xen_rdr3);
 __weak_alias(ldr3, xen_ldr3);
 __weak_alias(rdr6, xen_rdr6);
 __weak_alias(ldr6, xen_ldr6);
 __weak_alias(rdr7, xen_rdr7);
 __weak_alias(ldr7, xen_ldr7);
 __weak_alias(wbinvd, xen_wbinvd);
 __weak_alias(rcr2, xen_rcr2);
 #ifdef __x86_64__
 void xen_setusergs(int);
 __weak_alias(setusergs, xen_setusergs);
 #else
 void xen_lcr3(vaddr_t);
 __weak_alias(lcr3, xen_lcr3);
 #endif
 void
-invlpg(vaddr_t addr)
+xen_invlpg(vaddr_t addr)
+{
 	int s = splvm(); /* XXXSMP */
 	xpq_queue_invlpg(addr);
 	splx(s);
+}
 void
-lidt(struct region_descriptor *rd)
+xen_lidt(struct region_descriptor *rd)
+{
 	/*
 	 * We need to do this because we can't assume kmem_alloc(9)
 	 * will be available at the boot stage when this is called.
 	 */
 	static char xen_idt_page[PAGE_SIZE] __attribute__((__aligned__ (PAGE_SIZE)));
 	memset(xen_idt_page, 0, PAGE_SIZE);
 	struct trap_info *xen_idt = (void * )xen_idt_page;
 	int xen_idt_idx = 0;
 	struct trap_info * idd = (void *) rd->rd_base;
 	const int nidt = rd->rd_limit / (sizeof *idd);
 @@ -89,177 +155,177 @@ lidt(struct region_descriptor *rd)
 #endif /* __x86_64 */
 	/* Hook it up in the hypervisor */
 	if (HYPERVISOR_set_trap_table(xen_idt))
 		panic("HYPERVISOR_set_trap_table() failed");
 #if defined(__x86_64__)
 	/* reset */
 	pmap_changeprot_local((vaddr_t) xen_idt, VM_PROT_READ|VM_PROT_WRITE);
 #endif /* __x86_64 */
+}
 void
-lldt(u_short sel)
+xen_lldt(u_short sel)
+{
 #ifndef __x86_64__
 	struct cpu_info *ci;
 	ci = curcpu();
 	if (ci->ci_curldt == sel)
 		return;
 	if (sel == GSEL(GLDT_SEL, SEL_KPL))
 		xen_set_ldt((vaddr_t)ldtstore, NLDT);
 	else
 		xen_set_ldt(ci->ci_gdt[IDXSELN(sel)].ld.ld_base,
 		    ci->ci_gdt[IDXSELN(sel)].ld.ld_entries);
 	ci->ci_curldt = sel;
 #endif
+}
 void
-ltr(u_short sel)
+xen_ltr(u_short sel)
+{
 	panic("XXX ltr not supported\n");
+}
 void
-lcr0(u_long val)
+xen_lcr0(u_long val)
+{
 	panic("XXX lcr0 not supported\n");
+}
 u_long
-rcr0(void)
+xen_rcr0(void)
+{
 	/* XXX: handle X86_CR0_TS ? */
 	return 0;
+}
 #ifndef __x86_64__
 void
-lcr3(vaddr_t val)
+xen_lcr3(vaddr_t val)
+{
 	int s = splvm(); /* XXXSMP */
 	xpq_queue_pt_switch(xpmap_ptom_masked(val));
 	splx(s);
+}
 #endif
 void
-tlbflush(void)
+xen_tlbflush(void)
+{
 	int s = splvm(); /* XXXSMP */
 	xpq_queue_tlb_flush();
 	splx(s);
+}
 void
-tlbflushg(void)
+xen_tlbflushg(void)
+{
 	tlbflush();
+}
 register_t
-rdr0(void)
+xen_rdr0(void)
+{
 	return HYPERVISOR_get_debugreg(0);
+}
 void
-ldr0(register_t val)
+xen_ldr0(register_t val)
+{
 	HYPERVISOR_set_debugreg(0, val);
+}
 register_t
-rdr1(void)
+xen_rdr1(void)
+{
 	return HYPERVISOR_get_debugreg(1);
+}
 void
-ldr1(register_t val)
+xen_ldr1(register_t val)
+{
 	HYPERVISOR_set_debugreg(1, val);
+}
 register_t
-rdr2(void)
+xen_rdr2(void)
+{
 	return HYPERVISOR_get_debugreg(2);
+}
 void
-ldr2(register_t val)
+xen_ldr2(register_t val)
+{
 	HYPERVISOR_set_debugreg(2, val);
+}
 register_t
-rdr3(void)
+xen_rdr3(void)
+{
 	return HYPERVISOR_get_debugreg(3);
+}
 void
-ldr3(register_t val)
+xen_ldr3(register_t val)
+{
 	HYPERVISOR_set_debugreg(3, val);
+}
 register_t
-rdr6(void)
+xen_rdr6(void)
+{
 	return HYPERVISOR_get_debugreg(6);
+}
 void
-ldr6(register_t val)
+xen_ldr6(register_t val)
+{
 	HYPERVISOR_set_debugreg(6, val);
+}
 register_t
-rdr7(void)
+xen_rdr7(void)
+{
 	return HYPERVISOR_get_debugreg(7);
+}
 void
-ldr7(register_t val)
+xen_ldr7(register_t val)
+{
 	HYPERVISOR_set_debugreg(7, val);
+}
 void
-wbinvd(void)
+xen_wbinvd(void)
+{
 	xpq_flush_cache();
+}
 vaddr_t
-rcr2(void)
+xen_rcr2(void)
+{
 	return curcpu()->ci_vcpu->arch.cr2;
+}
 #ifdef __x86_64__
 void
-setusergs(int gssel)
+xen_setusergs(int gssel)
+{
 	HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, gssel);
+}
 #endif