 @@ -1,14 +1,14 @@
-/* $NetBSD: sunxi_mc_smp.c,v 1.2 2019/01/03 12:52:40 jmcneill Exp $ */
+/* $NetBSD: sunxi_mc_smp.c,v 1.3 2019/01/03 14:44:21 jmcneill Exp $ */
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -18,186 +18,246 @@
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_mc_smp.c,v 1.2 2019/01/03 12:52:40 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_mc_smp.c,v 1.3 2019/01/03 14:44:21 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <uvm/uvm_extern.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/armreg.h>
 #include <arm/cpu.h>
 #include <arm/cpufunc.h>
 #include <arm/locore.h>
 #include <arm/sunxi/sunxi_mc_smp.h>
-#define	A83T_SMP_ENABLE_METHOD	"allwinner,sun8i-a83t-smp"
+#define	A80_PRCM_BASE		0x08001400
 #define	A80_PRCM_SIZE		0x200
-#define	PRCM_BASE		0x01f01400
+#define	A83T_PRCM_BASE		0x01f01400
-#define	PRCM_SIZE		0x800
+#define	A83T_PRCM_SIZE		0x800
 #define	 PRCM_CL_RST_CTRL(cluster)	(0x4 + (cluster) * 0x4)
 #define	 PRCM_CL_PWROFF(cluster)	(0x100 + (cluster) * 0x4)
 #define	 PRCM_CL_PWR_CLAMP(cluster, cpu) (0x140 + (cluster) * 0x10 + (cpu) * 0x4)
 #define	 PRCM_CPU_SOFT_ENTRY		0x164
 #define	CPUCFG_BASE	0x01f01c00
 #define	CPUCFG_SIZE	0x400
 #define	 CPUCFG_CL_RST(cluster)		(0x30 + (cluster) * 0x4)
 #define	 CPUCFG_P_REG0			0x1a4
 #define	CPUXCFG_BASE	0x01700000
 #define	CPUXCFG_SIZE	0x400
 #define	 CPUXCFG_CL_RST(cluster)	(0x80 + (cluster) * 0x4)
 #define	  CPUXCFG_CL_RST_SOC_DBG_RST	__BIT(24)
 #define	  CPUXCFG_CL_RST_ETM_RST(cpu)	__BIT(20 + (cpu))
 #define	  CPUXCFG_CL_RST_DBG_RST(cpu)	__BIT(16 + (cpu))
 #define	  CPUXCFG_CL_RST_H_RST		__BIT(12)
 #define	  CPUXCFG_CL_RST_L2_RST		__BIT(8)
 #define	  CPUXCFG_CL_RST_CX_RST(cpu)	__BIT(4 + (cpu))
 #define	 CPUXCFG_CL_CTRL0(cluster)	(0x0 + (cluster) * 0x10)
 #define	 CPUXCFG_CL_CTRL1(cluster)	(0x4 + (cluster) * 0x10)
 #define	  CPUXCFG_CL_CTRL1_ACINACTM	__BIT(0)
-#define	CCI_BASE		0x01790000
+#define	A80_CCI_BASE		0x01c90000
-#define	CCI_SLAVEIF3_BASE	(CCI_BASE + 0x4000)
+#define	A83T_CCI_BASE		0x01790000
 #define	CCI_SLAVEIF4_BASE	(CCI_BASE + 0x5000)
 #define	CCI_SLAVEIF3_OFFSET	0x4000
 #define	CCI_SLAVEIF4_OFFSET	0x5000
 extern struct bus_space arm_generic_bs_tag;
-uint32_t sunxi_mc_cci_port[MAXCPUS] = {
+enum sunxi_mc_soc {
-	CCI_SLAVEIF3_BASE,
+	MC_SOC_A80,
-	CCI_SLAVEIF3_BASE,
+	MC_SOC_A83T
-	CCI_SLAVEIF3_BASE,
+};
 	CCI_SLAVEIF3_BASE,
-	CCI_SLAVEIF4_BASE,
+enum sunxi_mc_cpu {
-	CCI_SLAVEIF4_BASE,
+	MC_CORE_CA7,
-	CCI_SLAVEIF4_BASE,
+	MC_CORE_CA15
 	CCI_SLAVEIF4_BASE,
 };
 uint32_t sunxi_mc_cci_port[MAXCPUS];
 static uint32_t
 sunxi_mc_smp_pa(void)
+{
 	extern void sunxi_mc_mpstart(void);
 	bool ok __diagused;
 	paddr_t pa;
 	ok = pmap_extract(pmap_kernel(), (vaddr_t)sunxi_mc_mpstart, &pa);
 	KASSERT(ok);
 	return pa;
+}
 static int
 sunxi_mc_smp_start(bus_space_tag_t bst, bus_space_handle_t prcm, bus_space_handle_t cpucfg,
-    bus_space_handle_t cpuxcfg, u_int cluster, u_int cpu)
+    bus_space_handle_t cpuxcfg, u_int cluster, u_int cpu, enum sunxi_mc_soc soc,
     enum sunxi_mc_cpu core)
+{
 	uint32_t val;
 	int i;
 	/* Set start vector */
 	bus_space_write_4(bst, cpucfg, CPUCFG_P_REG0, sunxi_mc_smp_pa());
 	/* Assert core reset */
 	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster));
 	val &= ~__BIT(cpu);
 	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster), val);
-	/* Assert power-on reset */
+	if (soc == MC_SOC_A83T) {
-	val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
+		/* Assert power-on reset */
-	val &= ~__BIT(cpu);
+		val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
-	bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
+		val &= ~__BIT(cpu);
 		bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
+	}
-	/* Disable automatic L1 cache invalidate at reset */
+	if (core == MC_CORE_CA7) {
-	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster));
+		/* Disable automatic L1 cache invalidate at reset */
-	val &= ~__BIT(cpu);
+		val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster));
-	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster), val);
+		val &= ~__BIT(cpu);
 		bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster), val);
+	}
 	/* Release power clamp */
 	for (i = 0; i <= 8; i++) {
 		bus_space_write_4(bst, prcm, PRCM_CL_PWR_CLAMP(cluster, cpu), 0xff >> i);
 		delay(10);
+	}
 	for (i = 100000; i > 0; i--) {
 		if (bus_space_read_4(bst, prcm, PRCM_CL_PWR_CLAMP(cluster, cpu)) == 0)
 			break;
+	}
 	if (i == 0) {
 		printf("CPU %#llx failed to start\n", __SHIFTIN(cluster, MPIDR_AFF1) | __SHIFTIN(cpu, MPIDR_AFF0));
 		return ETIMEDOUT;
+	}
 	/* Clear power-off gating */
 	val = bus_space_read_4(bst, prcm, PRCM_CL_PWROFF(cluster));
-	if (cpu == 0)
+	if (soc == MC_SOC_A83T) {
-		val &= ~__BIT(4);
+		if (cpu == 0)
-	val &= ~__BIT(cpu);
+			val &= ~__BIT(4);
 		val &= ~__BIT(0);	/* cluster power gate */
 	} else {
 		val &= ~__BIT(cpu);
 		val &= ~__BIT(4);	/* cluster power gate */
+	}
 	bus_space_write_4(bst, prcm, PRCM_CL_PWROFF(cluster), val);
 	/* De-assert power-on reset */
 	val = bus_space_read_4(bst, prcm, PRCM_CL_RST_CTRL(cluster));
 	val |= __BIT(cpu);
 	bus_space_write_4(bst, prcm, PRCM_CL_RST_CTRL(cluster), val);
-	val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
+	if (soc == MC_SOC_A83T) {
-	val |= __BIT(cpu);
+		val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
-	bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
+		val |= __BIT(cpu);
-	delay(10);
+		bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
 		delay(10);
+	}
 	/* De-assert core reset */
 	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster));
 	val |= __BIT(cpu);
 	val |= CPUXCFG_CL_RST_SOC_DBG_RST;
-	val |= CPUXCFG_CL_RST_ETM_RST(cpu);
+	if (core == MC_CORE_CA7)
 		val |= CPUXCFG_CL_RST_ETM_RST(cpu);
 	else
 		val |= CPUXCFG_CL_RST_CX_RST(cpu);
 	val |= CPUXCFG_CL_RST_DBG_RST(cpu);
 	val |= CPUXCFG_CL_RST_L2_RST;
 	val |= CPUXCFG_CL_RST_H_RST;
 	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster), val);
 	/* De-assert ACINACTM */
 	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_CTRL1(cluster));
 	val &= ~CPUXCFG_CL_CTRL1_ACINACTM;
 	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_CTRL1(cluster), val);
 	return 0;
+}
 int
-sunxi_mc_smp_enable(u_int mpidr)
+sun8i_a83t_smp_enable(u_int mpidr)
+{
 	bus_space_tag_t bst = &arm_generic_bs_tag;
 	bus_space_handle_t prcm, cpucfg, cpuxcfg;
 	int error;
 	const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);
 	const u_int cpu = __SHIFTOUT(mpidr, MPIDR_AFF0);
-	if (bus_space_map(bst, PRCM_BASE, PRCM_SIZE, 0, &prcm) != 0 ||
+	if (bus_space_map(bst, A83T_PRCM_BASE, A83T_PRCM_SIZE, 0, &prcm) != 0 ||
 	    bus_space_map(bst, CPUCFG_BASE, CPUCFG_SIZE, 0, &cpucfg) != 0 ||
 	    bus_space_map(bst, CPUXCFG_BASE, CPUXCFG_SIZE, 0, &cpuxcfg) != 0)
 		return ENOMEM;
-	error = sunxi_mc_smp_start(bst, prcm, cpucfg, cpuxcfg, cluster, cpu);
+	for (int i = 0; i < 4; i++)
 		sunxi_mc_cci_port[i] = A83T_CCI_BASE + CCI_SLAVEIF3_OFFSET;
 	for (int i = 4; i < 8; i++)
 		sunxi_mc_cci_port[i] = A83T_CCI_BASE + CCI_SLAVEIF4_OFFSET;
 	/* Set start vector */
 	bus_space_write_4(bst, cpucfg, CPUCFG_P_REG0, sunxi_mc_smp_pa());
 	cpu_idcache_wbinv_all();
 	error = sunxi_mc_smp_start(bst, prcm, cpucfg, cpuxcfg, cluster, cpu,
 	    MC_SOC_A83T, MC_CORE_CA7);
 	bus_space_unmap(bst, cpuxcfg, CPUXCFG_SIZE);
 	bus_space_unmap(bst, cpucfg, CPUCFG_SIZE);
-	bus_space_unmap(bst, prcm, PRCM_SIZE);
+	bus_space_unmap(bst, prcm, A83T_PRCM_SIZE);
 	return error;
+}
 int
 sun9i_a80_smp_enable(u_int mpidr)
+{
 	bus_space_tag_t bst = &arm_generic_bs_tag;
 	bus_space_handle_t prcm, cpuxcfg;
 	int error;
 	const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);
 	const u_int cpu = __SHIFTOUT(mpidr, MPIDR_AFF0);
 	if (bus_space_map(bst, A80_PRCM_BASE, A80_PRCM_SIZE, 0, &prcm) != 0 ||
 	    bus_space_map(bst, CPUXCFG_BASE, CPUXCFG_SIZE, 0, &cpuxcfg) != 0)
 		return ENOMEM;
 	for (int i = 0; i < 4; i++)
 		sunxi_mc_cci_port[i] = A80_CCI_BASE + CCI_SLAVEIF3_OFFSET;
 	for (int i = 4; i < 8; i++)
 		sunxi_mc_cci_port[i] = A80_CCI_BASE + CCI_SLAVEIF4_OFFSET;
 	/* Set start vector */
 	bus_space_write_4(bst, prcm, PRCM_CPU_SOFT_ENTRY, sunxi_mc_smp_pa());
 	cpu_idcache_wbinv_all();
 	error = sunxi_mc_smp_start(bst, prcm, 0, cpuxcfg, cluster, cpu,
 	    MC_SOC_A80, cluster == 0 ? MC_CORE_CA7 : MC_CORE_CA15);
 	bus_space_unmap(bst, cpuxcfg, CPUXCFG_SIZE);
 	bus_space_unmap(bst, prcm, A80_PRCM_SIZE);
 	return error;
+}

 @@ -1,14 +1,14 @@
-/* $NetBSD: sunxi_platform.c,v 1.33 2019/01/03 12:52:40 jmcneill Exp $ */
+/* $NetBSD: sunxi_platform.c,v 1.34 2019/01/03 14:44:21 jmcneill Exp $ */
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -21,27 +21,27 @@
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_soc.h"
 #include "opt_multiprocessor.h"
 #include "opt_console.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.33 2019/01/03 12:52:40 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.34 2019/01/03 14:44:21 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/termios.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/fdt/arm_fdtvar.h>
 #include <uvm/uvm_extern.h>
 #include <machine/bootconfig.h>
 @@ -117,46 +117,70 @@ extern struct bus_space arm_generic_a4x_
 static const struct pmap_devmap *
 sunxi_platform_devmap(void)
+{
 	static const struct pmap_devmap devmap[] = {
 		DEVMAP_ENTRY(SUNXI_CORE_VBASE,
 			     SUNXI_CORE_PBASE,
 			     SUNXI_CORE_SIZE),
 		DEVMAP_ENTRY_END
 	};
 	return devmap;
+}
-#define	SUN8I_A83T_CPU_VBASE	(SUNXI_CORE_VBASE + SUNXI_CORE_SIZE)
+#define	SUNXI_MC_CPU_VBASE	(SUNXI_CORE_VBASE + SUNXI_CORE_SIZE)
-#define	SUN8I_A83T_CPU_PBASE	0x01700000
+#define	SUNXI_MC_CPU_PBASE	0x01700000
-#define	SUN8I_A83T_CPU_SIZE	0x00100000
+#define	SUNXI_MC_CPU_SIZE	0x00100000
 static const struct pmap_devmap *
 sun8i_a83t_platform_devmap(void)
+{
 	static const struct pmap_devmap devmap[] = {
 		DEVMAP_ENTRY(SUNXI_CORE_VBASE,
 			     SUNXI_CORE_PBASE,
 			     SUNXI_CORE_SIZE),
-		DEVMAP_ENTRY(SUN8I_A83T_CPU_VBASE,
+		DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE,
-			     SUN8I_A83T_CPU_PBASE,
+			     SUNXI_MC_CPU_PBASE,
-			     SUN8I_A83T_CPU_SIZE),
+			     SUNXI_MC_CPU_SIZE),
 		DEVMAP_ENTRY_END
 	};
 	return devmap;
+}
 #define	SUN9I_A80_PRCM_VBASE	(SUNXI_MC_CPU_VBASE + SUNXI_MC_CPU_PBASE)
 #define	SUN9I_A80_PRCM_PBASE	0x08000000
 #define	SUN9I_A80_PRCM_SIZE	0x00100000
 static const struct pmap_devmap *
 sun9i_a80_platform_devmap(void)
+{
 	static const struct pmap_devmap devmap[] = {
 		DEVMAP_ENTRY(SUNXI_CORE_VBASE,
 			     SUNXI_CORE_PBASE,
 			     SUNXI_CORE_SIZE),
 		DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE,
 			     SUNXI_MC_CPU_PBASE,
 			     SUNXI_MC_CPU_SIZE),
 		DEVMAP_ENTRY(SUN9I_A80_PRCM_VBASE,
 			     SUN9I_A80_PRCM_PBASE,
 			     SUN9I_A80_PRCM_SIZE),
 		DEVMAP_ENTRY_END
 	};
 	return devmap;
+}
 static void
 sunxi_platform_init_attach_args(struct fdt_attach_args *faa)
+{
 	faa->faa_bst = &sunxi_bs_tag;
 	faa->faa_a4x_bst = &sunxi_a4x_bs_tag;
 	faa->faa_dmat = &sunxi_dma_tag;
+}
 void sunxi_platform_early_putchar(char);
 void
 sunxi_platform_early_putchar(char c)
+{
 @@ -227,35 +251,46 @@ sunxi_platform_bootstrap(void)
 			if (status == NULL || strncmp(status, "ok", 2) == 0) {
 				fdt_setprop_string(fdt_data, chosen_off,
 				    "stdout-path", "/chosen/framebuffer");
+			}
+		}
 	} else if (match_bootconf_option(boot_args, "console", "serial")) {
 		fdt_setprop_string(fdt_data, chosen_off,
 		    "stdout-path", "serial0:115200n8");
+	}
+}
 #if defined(SOC_SUNXI_MC)
 static int
-cpu_enable_sunxi_mc(int phandle)
+cpu_enable_sun8i_a83t(int phandle)
+{
 	uint64_t mpidr;
 	fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
-	return sunxi_mc_smp_enable(mpidr);
+	return sun8i_a83t_smp_enable(mpidr);
+}
-ARM_CPU_METHOD(sun8i_a83t, "allwinner,sun8i-a83t-smp", cpu_enable_sunxi_mc);
+ARM_CPU_METHOD(sun8i_a83t, "allwinner,sun8i-a83t-smp", cpu_enable_sun8i_a83t);
 static int
 cpu_enable_sun9i_a80(int phandle)
+{
 	uint64_t mpidr;
 	fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
 	return sun9i_a80_smp_enable(mpidr);
+}
 ARM_CPU_METHOD(sun9i_a80, "allwinner,sun9i-a80-smp", cpu_enable_sun9i_a80);
 #endif
 static void
 sun4i_platform_reset(void)
+{
 	bus_space_tag_t bst = &sunxi_bs_tag;
 	bus_space_handle_t bsh;
 	bus_space_map(bst, SUN4I_WDT_BASE, SUN4I_WDT_SIZE, 0, &bsh);
 	bus_space_write_4(bst, bsh, SUN4I_WDT_CTRL,
 	    SUN4I_WDT_CTRL_KEY | SUN4I_WDT_CTRL_RESTART);
 	for (;;) {
 @@ -401,27 +436,27 @@ static const struct arm_platform sun8i_a
 	.ap_devmap = sun8i_a83t_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun6i_platform_reset,
 	.ap_delay = gtmr_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 ARM_PLATFORM(sun8i_a83t, "allwinner,sun8i-a83t", &sun8i_a83t_platform);
 static const struct arm_platform sun9i_platform = {
-	.ap_devmap = sunxi_platform_devmap,
+	.ap_devmap = sun9i_a80_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun9i_platform_reset,
 	.ap_delay = gtmr_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 ARM_PLATFORM(sun9i_a80, "allwinner,sun9i-a80", &sun9i_platform);
 static const struct arm_platform sun50i_platform = {
 	.ap_devmap = sunxi_platform_devmap,

 @@ -1,14 +1,14 @@
-#	$NetBSD: files.sunxi,v 1.58 2019/01/03 11:01:59 jmcneill Exp $
+#	$NetBSD: files.sunxi,v 1.59 2019/01/03 14:44:21 jmcneill Exp $
+#
 # Configuration info for Allwinner sunxi family SoCs
+#
+#
 file	arch/arm/sunxi/sunxi_platform.c		soc_sunxi
 file	arch/arm/sunxi/sunxi_mc_smp.c		soc_sunxi_mc
 file	arch/arm/sunxi/sunxi_mc_mpstart.S	soc_sunxi_mc
 # CCU
 define	sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu.c		sunxi_ccu
 @@ -302,18 +302,18 @@ defflag	opt_soc.h			SOC_SUNXI
 defflag	opt_soc.h			SOC_SUNXI_MC
 defflag	opt_soc.h			SOC_SUN4I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN4I_A10: SOC_SUN4I
 defflag	opt_soc.h			SOC_SUN5I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN5I_A13: SOC_SUN5I
 defflag	opt_soc.h			SOC_SUN6I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN6I_A31: SOC_SUN6I
 defflag	opt_soc.h			SOC_SUN7I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN7I_A20: SOC_SUN7I
 defflag	opt_soc.h			SOC_SUN8I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN8I_A83T: SOC_SUN8I, SOC_SUNXI_MC
 defflag	opt_soc.h			SOC_SUN8I_H3: SOC_SUN8I
 defflag	opt_soc.h			SOC_SUN9I: SOC_SUNXI
-defflag	opt_soc.h			SOC_SUN9I_A80: SOC_SUN9I
+defflag	opt_soc.h			SOC_SUN9I_A80: SOC_SUN9I, SOC_SUNXI_MC
 defflag	opt_soc.h			SOC_SUN50I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN50I_A64: SOC_SUN50I
 defflag	opt_soc.h			SOC_SUN50I_H5: SOC_SUN50I, SOC_SUN8I_H3
 defflag	opt_soc.h			SOC_SUN50I_H6: SOC_SUN50I