Thu Aug 29 05:55:19 2019 UTC ()
 Add missing NUL to prevent buffer overrun.


(msaitoh)
diff -r1.29 -r1.30 src/sys/arch/sparc/include/ctlreg.h
diff -r1.2 -r1.3 src/sys/dev/pci/if_xgereg.h
cvs diff -r1.29 -r1.30 src/sys/arch/sparc/include/ctlreg.h (expand / switch to unified diff)

--- src/sys/arch/sparc/include/ctlreg.h 2013/12/04 18:44:14 1.29
+++ src/sys/arch/sparc/include/ctlreg.h 2019/08/29 05:55:18 1.30
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: ctlreg.h,v 1.29 2013/12/04 18:44:14 jdc Exp $ */ 1/* $NetBSD: ctlreg.h,v 1.30 2019/08/29 05:55:18 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1996 4 * Copyright (c) 1996
5 * The President and Fellows of Harvard College. All rights reserved. 5 * The President and Fellows of Harvard College. All rights reserved.
6 * Copyright (c) 1992, 1993 6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved. 7 * The Regents of the University of California. All rights reserved.
8 * 8 *
9 * This software was developed by the Computer Systems Engineering group 9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley. 11 * contributed to Berkeley.
12 * 12 *
13 * All advertising materials mentioning features or use of this software 13 * All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement: 14 * must display the following acknowledgement:
@@ -366,27 +366,27 @@ @@ -366,27 +366,27 @@
366#define SFSR_P 0x00004000 /* SS: Parity error */ 366#define SFSR_P 0x00004000 /* SS: Parity error */
367#define SFSR_UC 0x00001000 /* Uncorrectable error */ 367#define SFSR_UC 0x00001000 /* Uncorrectable error */
368#define SFSR_TO 0x00000800 /* S-Bus timeout */ 368#define SFSR_TO 0x00000800 /* S-Bus timeout */
369#define SFSR_BE 0x00000400 /* S-Bus bus error */ 369#define SFSR_BE 0x00000400 /* S-Bus bus error */
370#define SFSR_LVL 0x00000300 /* Pagetable level causing the fault */ 370#define SFSR_LVL 0x00000300 /* Pagetable level causing the fault */
371#define SFSR_AT 0x000000e0 /* Access type */ 371#define SFSR_AT 0x000000e0 /* Access type */
372#define SFSR_FT 0x0000001c /* Fault type */ 372#define SFSR_FT 0x0000001c /* Fault type */
373#define SFSR_FAV 0x00000002 /* Fault Address is valid */ 373#define SFSR_FAV 0x00000002 /* Fault Address is valid */
374#define SFSR_OW 0x00000001 /* Overwritten with new fault */ 374#define SFSR_OW 0x00000001 /* Overwritten with new fault */
375 375
376#define SFSR_BITS "\177\020" \ 376#define SFSR_BITS "\177\020" \
377 "b\21EM\0b\20CS\0b\17SB\0f\15\2PERR\0" \ 377 "b\21EM\0b\20CS\0b\17SB\0f\15\2PERR\0" \
378 "b\14UC\0b\13TO\0b\12BE\0f\10\2LVL\0" \ 378 "b\14UC\0b\13TO\0b\12BE\0f\10\2LVL\0" \
379 "f\05\3AT\0f\02\3FT\0b\01FAV\0b\01OW" 379 "f\05\3AT\0f\02\3FT\0b\01FAV\0b\01OW\0"
380 380
381/* [4m] Synchronous Fault Types */ 381/* [4m] Synchronous Fault Types */
382#define SFSR_FT_NONE (0 << 2) /* no fault */ 382#define SFSR_FT_NONE (0 << 2) /* no fault */
383#define SFSR_FT_INVADDR (1 << 2) /* invalid address fault */ 383#define SFSR_FT_INVADDR (1 << 2) /* invalid address fault */
384#define SFSR_FT_PROTERR (2 << 2) /* protection fault */ 384#define SFSR_FT_PROTERR (2 << 2) /* protection fault */
385#define SFSR_FT_PRIVERR (3 << 2) /* privelege violation */ 385#define SFSR_FT_PRIVERR (3 << 2) /* privelege violation */
386#define SFSR_FT_TRANSERR (4 << 2) /* translation fault */ 386#define SFSR_FT_TRANSERR (4 << 2) /* translation fault */
387#define SFSR_FT_BUSERR (5 << 2) /* access bus error */ 387#define SFSR_FT_BUSERR (5 << 2) /* access bus error */
388#define SFSR_FT_INTERR (6 << 2) /* internal error */ 388#define SFSR_FT_INTERR (6 << 2) /* internal error */
389#define SFSR_FT_RESERVED (7 << 2) /* reserved */ 389#define SFSR_FT_RESERVED (7 << 2) /* reserved */
390 390
391/* [4m] Synchronous Fault Access Types */ 391/* [4m] Synchronous Fault Access Types */
392#define SFSR_AT_LDUDATA (0 << 5) /* Load user data */ 392#define SFSR_AT_LDUDATA (0 << 5) /* Load user data */
cvs diff -r1.2 -r1.3 src/sys/dev/pci/if_xgereg.h (expand / switch to unified diff)

--- src/sys/dev/pci/if_xgereg.h 2005/12/11 12:22:50 1.2
+++ src/sys/dev/pci/if_xgereg.h 2019/08/29 05:55:19 1.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: if_xgereg.h,v 1.2 2005/12/11 12:22:50 christos Exp $ */ 1/* $NetBSD: if_xgereg.h,v 1.3 2019/08/29 05:55:19 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -75,27 +75,27 @@ @@ -75,27 +75,27 @@
75#define ADAPTER_EN (1ULL<<56) 75#define ADAPTER_EN (1ULL<<56)
76#define EOI_TX_ON (1ULL<<48) 76#define EOI_TX_ON (1ULL<<48)
77#define LED_ON (1ULL<<40) 77#define LED_ON (1ULL<<40)
78#define WAIT_INT_EN (1ULL<<15) 78#define WAIT_INT_EN (1ULL<<15)
79#define ECC_ENABLE_N (1ULL<<8) 79#define ECC_ENABLE_N (1ULL<<8)
80 80
81/* for debug of ADAPTER_STATUS */ 81/* for debug of ADAPTER_STATUS */
82#define QUIESCENT (TDMA_READY|RDMA_READY|PFC_READY|TMAC_BUF_EMPTY|\ 82#define QUIESCENT (TDMA_READY|RDMA_READY|PFC_READY|TMAC_BUF_EMPTY|\
83 PIC_QUIESCENT|MC_DRAM_READY|MC_QUEUES_READY|M_PLL_LOCK|P_PLL_LOCK) 83 PIC_QUIESCENT|MC_DRAM_READY|MC_QUEUES_READY|M_PLL_LOCK|P_PLL_LOCK)
84#define QUIESCENT_BMSK \ 84#define QUIESCENT_BMSK \
85 "\177\20b\x3fTDMA_READY\0b\x3eRDMA_READY\0b\x3dPFC_READY\0" \ 85 "\177\20b\x3fTDMA_READY\0b\x3eRDMA_READY\0b\x3dPFC_READY\0" \
86 "b\x3cTMAC_BUF_EMPTY\0b\x3aPIC_QUIESCENT\0\x39RMAC_REMOTE_FAULT\0" \ 86 "b\x3cTMAC_BUF_EMPTY\0b\x3aPIC_QUIESCENT\0\x39RMAC_REMOTE_FAULT\0" \
87 "b\x38RMAC_LOCAL_FAULT\0b\x27MC_DRAM_READY\0b\x26MC_QUEUES_READY\0" \ 87 "b\x38RMAC_LOCAL_FAULT\0b\x27MC_DRAM_READY\0b\x26MC_QUEUES_READY\0" \
88 "b\x21M_PLL_LOCK\0b\x20P_PLL_LOCK" 88 "b\x21M_PLL_LOCK\0b\x20P_PLL_LOCK\0"
89 89
90/* 90/*
91 * PCI-X registers 91 * PCI-X registers
92 */ 92 */
93/* Interrupt control registers */ 93/* Interrupt control registers */
94#define PIC_INT_STATUS PCIXB(0) 94#define PIC_INT_STATUS PCIXB(0)
95#define PIC_INT_MASK PCIXB(0x008) 95#define PIC_INT_MASK PCIXB(0x008)
96#define TXPIC_INT_MASK PCIXB(0x018) 96#define TXPIC_INT_MASK PCIXB(0x018)
97#define RXPIC_INT_MASK PCIXB(0x030) 97#define RXPIC_INT_MASK PCIXB(0x030)
98#define FLASH_INT_MASK PCIXB(0x048) 98#define FLASH_INT_MASK PCIXB(0x048)
99#define MDIO_INT_MASK PCIXB(0x060) 99#define MDIO_INT_MASK PCIXB(0x060)
100#define IIC_INT_MASK PCIXB(0x078) 100#define IIC_INT_MASK PCIXB(0x078)
101#define GPIO_INT_MASK PCIXB(0x098) 101#define GPIO_INT_MASK PCIXB(0x098)