 @@ -1,14 +1,14 @@
-/*	$NetBSD: rtl8169.c,v 1.159 2019/05/30 02:32:18 msaitoh Exp $	*/
+/*	$NetBSD: rtl8169.c,v 1.159.2.1 2020/01/28 11:12:30 martin Exp $	*/
 /*
  * Copyright (c) 1997, 1998-2003
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -23,27 +23,27 @@
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.159 2019/05/30 02:32:18 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.159.2.1 2020/01/28 11:12:30 martin Exp $");
 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
 /*
  * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver
+ *
  * Written by Bill Paul <wpaul@windriver.com>
  * Senior Networking Software Engineer
  * Wind River Systems
  */
 /*
  * This driver is designed to support RealTek's next generation of
  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
 @@ -597,56 +597,80 @@ re_attach(struct rtk_softc *sc)
 			 * These (8168/8111) controllers support jumbo frame
 			 * but it seems that enabling it requires touching
 			 * additional magic registers. Depending on MAC
 			 * revisions some controllers need to disable
 			 * checksum offload. So disable jumbo frame until
 			 * I have better idea what it really requires to
 			 * make it support.
 			 * RTL8168C/CP : supports up to 6KB jumbo frame.
 			 * RTL8111C/CP : supports up to 9KB jumbo frame.
 			 */
 			sc->sc_quirk |= RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8168E:
 		case RTK_HWREV_8168H:
 		case RTK_HWREV_8168H_SPIN1:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM |
 			    RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8168H:
 		case RTK_HWREV_8168FP:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM |
 			    RTKQ_NOJUMBO | RTKQ_RXDV_GATED | RTKQ_TXRXEN_LATER;
 			break;
 		case RTK_HWREV_8168E_VL:
 		case RTK_HWREV_8168F:
 		case RTK_HWREV_8411:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8168EP:
 		case RTK_HWREV_8168G:
 		case RTK_HWREV_8168G_SPIN1:
 		case RTK_HWREV_8168G_SPIN2:
 		case RTK_HWREV_8168G_SPIN4:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO |
 			    RTKQ_RXDV_GATED;
 			break;
 		case RTK_HWREV_8100E:
 		case RTK_HWREV_8100E_SPIN2:
 		case RTK_HWREV_8101E:
 			sc->sc_quirk |= RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8102E:
 		case RTK_HWREV_8102EL:
-		case RTK_HWREV_8103E:
+		case RTK_HWREV_8102EL_SPIN1:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8103E:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP;
 			break;
 		case RTK_HWREV_8401E:
 		case RTK_HWREV_8105E:
 		case RTK_HWREV_8105E_SPIN1:
 		case RTK_HWREV_8106E:
 			sc->sc_quirk |= RTKQ_PHYWAKE_PM |
 			    RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT |
 			    RTKQ_CMDSTOP;
 			break;
 		case RTK_HWREV_8402:
 			sc->sc_quirk |= RTKQ_PHYWAKE_PM |
 			    RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT |
 			    RTKQ_CMDSTOP; /* CMDSTOP_WAIT_TXQ */
 			break;
 		default:
 			aprint_normal_dev(sc->sc_dev,
 			    "Unknown revision (0x%08x)\n", hwrev);
 			/* assume the latest features */
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD;
 			sc->sc_quirk |= RTKQ_NOJUMBO;
+		}
 		/* Set RX length mask */
 		sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
 		sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169;
 	} else {
 		sc->sc_quirk |= RTKQ_NOJUMBO;
 @@ -1863,27 +1887,28 @@ re_init(struct ifnet *ifp)
 	CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI,
 	    RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
 	CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO,
 	    RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
 	if (sc->sc_quirk & RTKQ_RXDV_GATED) {
 		CSR_WRITE_4(sc, RTK_MISC,
 		    CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN);
+	}
 	/*
 	 * Enable transmit and receive.
 	 */
-	CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
+	if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) == 0)
 		CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
 	/*
 	 * Set the initial TX and RX configuration.
 	 */
 	if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) {
 		/* test mode is needed only for old 8169 */
 		CSR_WRITE_4(sc, RTK_TXCFG,
 		    RE_TXCFG_CONFIG | RTK_LOOPTEST_ON);
 	} else
 		CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG);
 	CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16);
 @@ -1905,26 +1930,32 @@ re_init(struct ifnet *ifp)
 	 */
 	if (ifp->if_flags & IFF_BROADCAST)
 		rxcfg |= RTK_RXCFG_RX_BROAD;
 	else
 		rxcfg &= ~RTK_RXCFG_RX_BROAD;
 	CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
 	/*
 	 * Program the multicast filter, if necessary.
 	 */
 	rtk_setmulti(sc);
 	/*
 	 * some chips require to enable TX/RX *AFTER* TX/RX configuration
 	 */
 	if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) != 0)
 		CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
 	/*
 	 * Enable interrupts.
 	 */
 	if (sc->re_testmode)
 		CSR_WRITE_2(sc, RTK_IMR, 0);
 	else if ((sc->sc_quirk & RTKQ_IM_HW) != 0)
 		CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW);
 	else
 		CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
 	/* Start RX/TX process. */
 	CSR_WRITE_4(sc, RTK_MISSEDPKT, 0);
 #ifdef notdef
 	/* Enable receiver and transmitter. */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: rtl81x9.c,v 1.106 2019/05/28 07:41:48 msaitoh Exp $	*/
+/*	$NetBSD: rtl81x9.c,v 1.106.2.1 2020/01/28 11:12:30 martin Exp $	*/
 /*
  * Copyright (c) 1997, 1998
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -76,27 +76,27 @@
  * On the bright side, the 8139 does have a built-in PHY, although
  * rather than using an MDIO serial interface like most other NICs, the
  * PHY registers are directly accessible through the 8139's register
  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
  * filter.
+ *
  * The 8129 chip is an older version of the 8139 that uses an external PHY
  * chip. The 8129 has a serial MDIO interface for accessing the MII where
  * the 8139 lets you directly access the on-board PHY registers. We need
  * to select which interface to use depending on the chip type.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.106 2019/05/28 07:41:48 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.106.2.1 2020/01/28 11:12:30 martin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/device.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <net/if.h>
 @@ -551,29 +551,29 @@ rtk_setmulti(struct rtk_softc *sc)
 	/* now program new ones */
 	ETHER_LOCK(ec);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	mcnt = 0;
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
 		    ETHER_ADDR_LEN) != 0) {
 			ETHER_UNLOCK(ec);
 			goto allmulti;
+		}
 		h = rtk_calchash(enm->enm_addrlo);
 		if (h < 32)
-			hashes[0] |= (1 << h);
+			hashes[0] |= __BIT(h);
 		else
-			hashes[1] |= (1 << (h - 32));
+			hashes[1] |= __BIT(h - 32);
 		mcnt++;
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ETHER_UNLOCK(ec);
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	if (mcnt)
 		rxfilt |= RTK_RXCFG_RX_MULTI;
 	else
 		rxfilt &= ~RTK_RXCFG_RX_MULTI;
 	CSR_WRITE_4(sc, RTK_RXCFG, rxfilt);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: rtl81x9reg.h,v 1.50 2019/04/05 23:46:04 uwe Exp $	*/
+/*	$NetBSD: rtl81x9reg.h,v 1.50.4.1 2020/01/28 11:12:30 martin Exp $	*/
 /*
  * Copyright (c) 1997, 1998
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -139,70 +139,79 @@
 #define RTK_MISC		0x00F0
 /*
  * TX config register bits
  */
 #define RTK_TXCFG_CLRABRT	0x00000001	/* retransmit aborted pkt */
 #define RTK_TXCFG_MAXDMA	0x00000700	/* max DMA burst size */
 #define RTK_TXCFG_CRCAPPEND	0x00010000	/* CRC append (0 = yes) */
 #define RTK_TXCFG_LOOPBKTST	0x00060000	/* loopback test */
 #define RTK_TXCFG_IFG2		0x00080000	/* 8169 only */
 #define RTK_TXCFG_IFG		0x03000000	/* interframe gap */
 #define RTK_TXCFG_HWREV		0x7CC00000
-#define RTK_LOOPTEST_OFF		0x00000000
+#define RTK_LOOPTEST_OFF	0x00000000
 #define RTK_LOOPTEST_ON		0x00020000
 #define RTK_LOOPTEST_ON_CPLUS	0x00060000
 /* Known revision codes. */
 #define RTK_HWREV_8169		0x00000000
 #define RTK_HWREV_8110S		0x00800000
 #define RTK_HWREV_8169S		0x04000000
 #define RTK_HWREV_8169_8110SB	0x10000000
 #define RTK_HWREV_8169_8110SC	0x18000000
 #define RTK_HWREV_8401E		0x24000000
 #define RTK_HWREV_8102EL	0x24800000
-#define RTK_HWREV_8103E		0x24C00000
+#define RTK_HWREV_8102EL_SPIN1	0x24C00000
 #define RTK_HWREV_8168D		0x28000000
 #define RTK_HWREV_8168DP	0x28800000
 #define RTK_HWREV_8168E		0x2C000000
 #define RTK_HWREV_8168E_VL	0x2C800000
 #define RTK_HWREV_8168_SPIN1	0x30000000
 #define RTK_HWREV_8168G		0x4c000000
 #define RTK_HWREV_8168G_SPIN1	0x4c100000
 #define RTK_HWREV_8168G_SPIN2	0x50900000
 #define RTK_HWREV_8168G_SPIN4	0x5c800000
 #define RTK_HWREV_8168GU	0x50800000
 #define RTK_HWREV_8100E		0x30800000
 #define RTK_HWREV_8101E		0x34000000
 #define RTK_HWREV_8102E		0x34800000
 #define RTK_HWREV_8103E		0x34c00000
 #define RTK_HWREV_8168_SPIN2	0x38000000
 #define RTK_HWREV_8168_SPIN3	0x38400000
 #define RTK_HWREV_8100E_SPIN2	0x38800000
 #define RTK_HWREV_8168C		0x3C000000
 #define RTK_HWREV_8168C_SPIN2	0x3C400000
 #define RTK_HWREV_8168CP	0x3C800000
 #define RTK_HWREV_8105E		0x40800000
 #define RTK_HWREV_8105E_SPIN1	0x40C00000
 #define RTK_HWREV_8402		0x44000000
 #define RTK_HWREV_8106E		0x44800000
 #define RTK_HWREV_8168F		0x48000000
 #define RTK_HWREV_8411		0x48800000
 #define RTK_HWREV_8168G		0x4c000000
 #define RTK_HWREV_8168G_SPIN1	0x4c100000
 #define RTK_HWREV_8168EP	0x50000000
 #define RTK_HWREV_8168GU	0x50800000
 #define RTK_HWREV_8168G_SPIN2	0x50900000
 #define RTK_HWREV_8168H		0x54000000
 #define RTK_HWREV_8168H_SPIN1	0x54100000
 #define RTK_HWREV_8168FP	0x54800000
 #define RTK_HWREV_8168G_SPIN4	0x5c800000
 #define RTK_HWREV_8139		0x60000000
 #define RTK_HWREV_8139A		0x70000000
 #define RTK_HWREV_8139AG	0x70800000
 #define RTK_HWREV_8139B		0x78000000
 #define RTK_HWREV_8130		0x7C000000
 #define RTK_HWREV_8139C		0x74000000
 #define RTK_HWREV_8139D		0x74400000
 #define RTK_HWREV_8139CPLUS	0x74800000
 #define RTK_HWREV_8101		0x74c00000
 #define RTK_HWREV_8139B		0x78000000
 #define RTK_HWREV_8100		0x78800000
 #define RTK_HWREV_8130		0x7C000000
 #define RTK_HWREV_8169_8110SBL	0x7cc00000
 #define RTK_TXDMA_16BYTES	0x00000000
 #define RTK_TXDMA_32BYTES	0x00000100
 #define RTK_TXDMA_64BYTES	0x00000200
 #define RTK_TXDMA_128BYTES	0x00000300
 #define RTK_TXDMA_256BYTES	0x00000400
 #define RTK_TXDMA_512BYTES	0x00000500
 #define RTK_TXDMA_1024BYTES	0x00000600
 #define RTK_TXDMA_2048BYTES	0x00000700
 /*
  * Transmit descriptor status register bits.

 @@ -1,14 +1,14 @@
-/*	$NetBSD: rtl81x9var.h,v 1.56 2017/04/19 00:20:02 jmcneill Exp $	*/
+/*	$NetBSD: rtl81x9var.h,v 1.56.18.1 2020/01/28 11:12:30 martin Exp $	*/
 /*
  * Copyright (c) 1997, 1998
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -184,26 +184,27 @@ struct rtk_softc {
 #define RTKQ_8129		0x00000001	/* 8129 */
 #define RTKQ_8139CPLUS		0x00000002	/* 8139C+ */
 #define RTKQ_8169NONS		0x00000004	/* old non-single 8169 */
 #define RTKQ_PCIE		0x00000008	/* PCIe variants */
 #define RTKQ_MACLDPS		0x00000010	/* has LDPS register */
 #define RTKQ_DESCV2		0x00000020	/* has V2 TX/RX descriptor */
 #define RTKQ_NOJUMBO		0x00000040	/* no jumbo MTU support */
 #define RTKQ_NOEECMD		0x00000080	/* unusable EEPROM command */
 #define RTKQ_MACSTAT		0x00000100	/* set MACSTAT_DIS on init */
 #define RTKQ_CMDSTOP		0x00000200	/* set STOPREQ on stop */
 #define RTKQ_PHYWAKE_PM		0x00000400	/* wake PHY from power down */
 #define RTKQ_RXDV_GATED		0x00000800
 #define RTKQ_IM_HW		0x00001000	/* HW interrupt mitigation */
 #define RTKQ_TXRXEN_LATER	0x00002000	/* TX/RX enable timing */
 	bus_dma_tag_t		sc_dmat;
 	bus_dma_segment_t	sc_dmaseg;	/* for rtk(4) */
 	int			sc_dmanseg;	/* for rtk(4) */
 	bus_dmamap_t		recv_dmamap;	/* for rtk(4) */
 	uint8_t			*rtk_rx_buf;
 	struct rtk_tx_desc	rtk_tx_descs[RTK_TX_LIST_CNT];
 	SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_free;
 	SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_dirty;