 @@ -1,14 +1,14 @@
-/*	$NetBSD: specialreg.h,v 1.150.2.5 2019/11/19 13:15:57 martin Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.150.2.6 2020/04/14 17:15:02 martin Exp $	*/
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -465,42 +465,46 @@
 	"b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0"	\
 	"b\4OSPKE\0"	"b\5WAITPKG\0"	"b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
 	"b\10GFNI\0"	"b\11VAES\0"	"b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
 	"b\14AVX512_BITALG\0"		"b\16AVX512_VPOPCNTDQ\0"	\
 	"f\21\5MAWAU\0"							\
 					"b\26RDPID\0"			\
 			"b\31CLDEMOTE\0"		"b\33MOVDIRI\0"	\
 	"b\34MOVDIR64B\0"		"b\36SGXLC\0"
 /* %edx */
 #define CPUID_SEF_AVX512_4VNNIW	__BIT(2)
 #define CPUID_SEF_AVX512_4FMAPS	__BIT(3)
 #define CPUID_SEF_FSREP_MOV	__BIT(4)  /* Fast Short REP MOV */
 #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8)
 #define CPUID_SEF_MD_CLEAR	__BIT(10)
 #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
 #define CPUID_SEF_SERIALIZE	__BIT(14)
 #define CPUID_SEF_HYBRID	__BIT(15) /* Hybrid part */
 #define CPUID_SEF_TSXLDTRK	__BIT(16) /* TSX suspend load addr tracking */
 #define CPUID_SEF_CET_IBT	__BIT(20) /* CET Indirect Branch Tracking */
 #define CPUID_SEF_IBRS		__BIT(26) /* IBRS / IBPB Speculation Control */
 #define CPUID_SEF_STIBP		__BIT(27) /* STIBP Speculation Control */
 #define CPUID_SEF_L1D_FLUSH	__BIT(28) /* IA32_FLUSH_CMD MSR */
 #define CPUID_SEF_ARCH_CAP	__BIT(29) /* IA32_ARCH_CAPABILITIES */
 #define CPUID_SEF_CORE_CAP	__BIT(30) /* IA32_CORE_CAPABILITIES */
 #define CPUID_SEF_SSBD		__BIT(31) /* Speculative Store Bypass Disable */
 #define CPUID_SEF_FLAGS2	"\20" \
 				"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
 	"\5" "FSREP_MOV"						\
-				"\13" "MD_CLEAR"			\
+	"\11" "VP2INTERSECT"	"\13" "MD_CLEAR"			\
-			"\16" "TSX_FORCE_ABORT"		"\20" "HYBRID"	\
+			"\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID"	\
 	"\21" "TSXLDTRK"						\
 	"\25" "CET_IBT"							\
 	"\33" "IBRS"	"\34" "STIBP"					\
 	"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP"	"\40" "SSBD"
 /*
  * Intel CPUID Architectural Performance Monitoring Fn0000000a
+ *
  * See also src/usr.sbin/tprof/arch/tprof_x86.c
  */
 /* %eax */
 #define CPUID_PERF_VERSION	__BITS(7, 0)   /* Version ID */
 #define CPUID_PERF_NGPPC	__BITS(15, 8)  /* Num of G.P. perf counter */
 @@ -683,49 +687,51 @@
 #define CPUID_AMD_FLAGS4	"\20" \
 	"\1" "LAHF"	"\2" "CMPLEGACY" "\3" "SVM"	"\4" "EAPIC" \
 	"\5" "ALTMOVCR0" "\6" "LZCNT"	"\7" "SSE4A"	"\10" "MISALIGNSSE" \
 	"\11" "3DNOWPREFETCH" \
 			"\12" "OSVW"	"\13" "IBS"	"\14" "XOP" \
 	"\15" "SKINIT"	"\16" "WDT"	"\17" "B14"	"\20" "LWP" \
 	"\21" "FMA4"	"\22" "TCE"	"\23" "B18"	"\24" "NodeID" \
 	"\25" "B20"	"\26" "TBM"	"\27" "TopoExt"	"\30" "PCExtC" \
 	"\31" "PCExtNB"	"\32" "StrmPM"	"\33" "DBExt"	"\34" "PerfTsc" \
 	"\35" "L2IPERFC" "\36" "MWAITX"	"\37" "B30"	"\40" "B31"
 /*
- * AMD Advanced Power Management
+ * Advanced Power Management
  * CPUID Fn8000_0007 %edx
+ *
  * Only ITSC is for both Intel and AMD. Others are only for AMD.
  */
 #define CPUID_APM_TS	0x00000001	/* Temperature Sensor */
 #define CPUID_APM_FID	0x00000002	/* Frequency ID control */
 #define CPUID_APM_VID	0x00000004	/* Voltage ID control */
 #define CPUID_APM_TTP	0x00000008	/* THERMTRIP (PCI F3xE4 register) */
 #define CPUID_APM_HTC	0x00000010	/* Hardware thermal control (HTC) */
 #define CPUID_APM_STC	0x00000020	/* Software thermal control (STC) */
 #define CPUID_APM_100	0x00000040	/* 100MHz multiplier control */
 #define CPUID_APM_HWP	0x00000080	/* HW P-State control */
-#define CPUID_APM_TSC	0x00000100	/* TSC invariant */
+#define CPUID_APM_ITSC	0x00000100	/* invariant TSC */
 #define CPUID_APM_CPB	0x00000200	/* Core performance boost */
 #define CPUID_APM_EFF	0x00000400	/* Effective Frequency (read-only) */
 #define CPUID_APM_PROCFI 0x00000800	/* Proc Feedback Interface */
 #define CPUID_APM_PROCPR 0x00001000	/* Proc Power Reporting  */
 #define CPUID_APM_CONNSTBY 0x00002000	/* Connected Standby */
 #define CPUID_APM_RAPL	0x00004000	/* Running Average Power Limit */
 #define CPUID_APM_FLAGS		"\20"					      \
 	"\1" "TS"	"\2" "FID"	"\3" "VID"	"\4" "TTP"	      \
 	"\5" "HTC"	"\6" "STC"	"\7" "100"	"\10" "HWP"	      \
-	"\11" "TSC"	"\12" "CPB"	"\13" "EffFreq"	"\14" "PROCFI"	      \
+	"\11" "ITSC"	"\12" "CPB"	"\13" "EffFreq"	"\14" "PROCFI"	      \
 	"\15" "PROCPR"	"\16" "CONNSTBY" "\17" "RAPL"
 /*
  * AMD Processor Capacity Parameters and Extended Features
  * CPUID Fn8000_0008
  * %eax: Long Mode Size Identifiers
  * %ebx: Extended Feature Identifiers
  * %ecx: Size Identifiers
  */
 /* %ebx */
 #define CPUID_CAPEX_CLZERO	__BIT(0)	/* CLZERO instruction */
 #define CPUID_CAPEX_IRPERF	__BIT(1)	/* InstRetCntMsr */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: procfs_machdep.c,v 1.33.2.1 2019/10/17 18:56:25 martin Exp $ */
+/*	$NetBSD: procfs_machdep.c,v 1.33.2.2 2020/04/14 17:15:02 martin Exp $ */
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Frank van der Linden and Jason R. Thorpe for
  * Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -32,27 +32,27 @@
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * NOTE: We simply use the primary CPU's cpuid_level and tsc_freq
  * here.  Might want to change this later.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.1 2019/10/17 18:56:25 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.2 2020/04/14 17:15:02 martin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/mount.h>
 #include <sys/stat.h>
 #include <sys/vnode.h>
 #include <miscfs/procfs/procfs.h>
 #include <machine/cpu.h>
 #include <machine/reg.h>
 #include <machine/specialreg.h>
 #include <x86/cputypes.h>
 @@ -178,28 +178,28 @@ static const char * const x86_features[]
 	"ospke", "waitpkg", "avx512_vbmi2", NULL,
 	"gfni", "vaes", "vpclmulqdq", "avx512_vnni",
 	"avx512_bitalg", "tme", "avx512_vpopcntdq", NULL,
 	"la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL,
 	NULL, "cldemote", NULL, "movdiri", "movdir64b", NULL, NULL, NULL},
 	{ /* (17) 0x80000007 ebx */
 	"overflow_recov", "succor", NULL, "smca", NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (18) Intel 0x00000007 edx */
-	NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", NULL, NULL, NULL, NULL,
+	NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", "fsrm", NULL, NULL, NULL,
-	NULL, NULL, "md_clear", NULL, NULL, NULL, NULL, NULL,
+	"vp2intersect", NULL, "md_clear", NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, "pconfig", NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL,
 	"flush_l1d", "arch_capabilities", NULL, "ssbd"},
 };
 static int	procfs_getonecpu(int, struct cpu_info *, char *, size_t *);
 /*
  * Linux-style /proc/cpuinfo.
  * Only used when procfs is mounted with -o linux.
+ *
  * In the multiprocessor case, this should be a loop over all CPUs.
  */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: tsc.c,v 1.37 2017/10/02 19:23:16 maxv Exp $	*/
+/*	$NetBSD: tsc.c,v 1.37.8.1 2020/04/14 17:15:02 martin Exp $	*/
 /*-
  * Copyright (c) 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.37 2017/10/02 19:23:16 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.37.8.1 2020/04/14 17:15:02 martin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/time.h>
 #include <sys/timetc.h>
 #include <sys/lwp.h>
 #include <sys/atomic.h>
 #include <sys/kernel.h>
 #include <sys/cpu.h>
 #include <sys/xcall.h>
 #include <machine/cpu_counter.h>
 #include <machine/cpuvar.h>
 @@ -125,27 +125,27 @@ tsc_is_invariant(void)
 		 */
+	}
 	/*
 	 * The best way to check whether the TSC counter is invariant or not
 	 * is to check CPUID 80000007.
 	 */
 	family = CPUID_TO_BASEFAMILY(ci->ci_signature);
 	if (((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
 	    && ((family == 0x06) || (family == 0x0f))) {
 		x86_cpuid(0x80000000, descs);
 		if (descs[0] >= 0x80000007) {
 			x86_cpuid(0x80000007, descs);
-			invariant = (descs[3] & CPUID_APM_TSC) != 0;
+			invariant = (descs[3] & CPUID_APM_ITSC) != 0;
+		}
+	}
 	return invariant;
+}
 void
 tsc_tc_init(void)
+{
 	struct cpu_info *ci;
 	bool invariant;
 	if (!cpu_hascounter())

 @@ -1,14 +1,14 @@
-/*	$NetBSD: i386.c,v 1.104.2.4 2019/11/19 13:15:57 martin Exp $	*/
+/*	$NetBSD: i386.c,v 1.104.2.5 2020/04/14 17:15:02 martin Exp $	*/
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Frank van der Linden,  and by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -47,27 +47,27 @@
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.104.2.4 2019/11/19 13:15:57 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.104.2.5 2020/04/14 17:15:02 martin Exp $");
 #endif /* not lint */
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/bitops.h>
 #include <sys/sysctl.h>
 #include <sys/ioctl.h>
 #include <sys/cpuio.h>
 #include <errno.h>
 #include <string.h>
 #include <stdio.h>
 #include <stdlib.h>
 @@ -109,27 +109,26 @@ struct cpu_info {
 					  *     [7] structure ext. feat. %edx
 					  *	[8] XCR0 bits (d:0 %eax)
 					  *	[9] xsave flags (d:1 %eax)
 					  */
 	uint32_t	ci_cpu_class;	 /* CPU class */
 	uint32_t	ci_brand_id;	 /* Intel brand id */
 	uint32_t	ci_vendor[4];	 /* vendor string */
 	uint32_t	ci_cpu_serial[3]; /* PIII serial number */
 	uint64_t	ci_tsc_freq;	 /* cpu cycles/second */
 	uint8_t		ci_packageid;
 	uint8_t		ci_coreid;
 	uint8_t		ci_smtid;
 	uint32_t	ci_initapicid;
 	uint32_t	ci_max_ext_cpuid;
 	uint32_t	ci_cur_xsave;
 	uint32_t	ci_max_xsave;
 	struct x86_cache_info ci_cinfo[CAI_COUNT];
 	void		(*ci_info)(struct cpu_info *);
 };
 struct cpu_nocpuid_nameclass {
 	int cpu_vendor;
 	const char *cpu_vendorname;
 	const char *cpu_name;
 	int cpu_class;
 @@ -1934,27 +1933,27 @@ identifycpu_cpuids_amd(struct cpu_info *
 	int n, cpu_family, apic_id, smt_bits, core_bits = 0;
 	uint32_t descs[4];
 	apic_id = ci->ci_initapicid;
 	cpu_family = CPUID_TO_FAMILY(ci->ci_signature);
 	if (cpu_family < 0xf)
 		return;
 	if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) {
 		x86_cpuid(1, descs);
 		lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
-		if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) {
+		if (cpu_family >= 0x10 && ci->ci_cpuid_extlevel >= 0x8000008) {
 			x86_cpuid(0x8000008, descs);
 			core_max = (descs[2] & 0xff) + 1;
 			n = (descs[2] >> 12) & 0x0f;
 			if (n != 0)
 				core_bits = n;
+		}
 	} else {
 		lp_max = 1;
+	}
 	core_max = lp_max;
 	smt_bits = ilog2((lp_max / core_max) - 1) + 1;
 	if (core_bits == 0)
 @@ -2277,52 +2276,48 @@ identifycpu(int fd, const char *cpuname)
 		|| (cpu_vendor == CPUVENDOR_AMD))) {
 		x86_cpuid(6, descs);
 		print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]);
 		print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]);
+	}
 	if ((ci->ci_cpuid_level >= 7)
 	    && ((cpu_vendor == CPUVENDOR_INTEL)
 		|| (cpu_vendor == CPUVENDOR_AMD))) {
 		x86_cpuid(7, descs);
 		aprint_verbose("%s: SEF highest subleaf %08x\n",
 		    cpuname, descs[0]);
+	}
-	if (cpu_vendor == CPUVENDOR_AMD) {
+	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
-		x86_cpuid(0x80000000, descs);
+		if (ci->ci_cpuid_extlevel >= 0x80000007)
 		if (descs[0] >= 0x80000000)
 			ci->ci_max_ext_cpuid = descs[0];
 		else
 			ci->ci_max_ext_cpuid = 0;
 		if (ci->ci_max_ext_cpuid >= 0x80000007)
 			powernow_probe(ci);
-		if (ci->ci_max_ext_cpuid >= 0x80000008) {
+	if (cpu_vendor == CPUVENDOR_AMD) {
 		if (ci->ci_cpuid_extlevel >= 0x80000008) {
 			x86_cpuid(0x80000008, descs);
 			print_bits(cpuname, "AMD Extended features",
 			    CPUID_CAPEX_FLAGS, descs[1]);
+		}
-		if ((ci->ci_max_ext_cpuid >= 0x8000000a)
+		if ((ci->ci_cpuid_extlevel >= 0x8000000a)
 		    && (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
 			x86_cpuid(0x8000000a, descs);
 			aprint_verbose("%s: SVM Rev. %d\n", cpuname,
 			    descs[0] & 0xf);
 			aprint_verbose("%s: SVM NASID %d\n", cpuname,
 			    descs[1]);
 			print_bits(cpuname, "SVM features",
 			    CPUID_AMD_SVM_FLAGS, descs[3]);
+		}
-		if (ci->ci_max_ext_cpuid >= 0x8000001f) {
+		if (ci->ci_cpuid_extlevel >= 0x8000001f) {
 			x86_cpuid(0x8000001f, descs);
 			print_bits(cpuname, "Encrypted Memory features",
 			    CPUID_AMD_ENCMEM_FLAGS, descs[0]);
+		}
 	} else if (cpu_vendor == CPUVENDOR_INTEL) {
 		int32_t bi_index;
 		for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) {
 			x86_cpuid(bi_index, descs);
 			switch (bi_index) {
 			case 0x0a:
 				print_bits(cpuname, "Perfmon-eax",
 				    CPUID_PERF_FLAGS0, descs[0]);
 @@ -2562,28 +2557,27 @@ x86_print_cache_and_tlb_info(struct cpu_
 			aprint_verbose("\n");
+	}
+}
 static void
 powernow_probe(struct cpu_info *ci)
+{
 	uint32_t regs[4];
 	char buf[256];
 	x86_cpuid(0x80000007, regs);
 	snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]);
-	aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n",
+	aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf);
 	    buf);
+}
 bool
 identifycpu_bind(void)
+{
 	return true;
+}
 int
 ucodeupdate_check(int fd, struct cpu_ucode *uc)
+{
 	struct cpu_info ci;