Tue Apr 14 18:11:35 2020 UTC ()
Regen for ticket #1529


(martin)
diff -r1.128.6.8 -r1.128.6.9 src/sys/dev/mii/miidevs.h
diff -r1.116.6.8 -r1.116.6.9 src/sys/dev/mii/miidevs_data.h
cvs diff -r1.128.6.8 -r1.128.6.9 src/sys/dev/mii/miidevs.h (expand / switch to unified diff)

--- src/sys/dev/mii/miidevs.h 2019/11/25 15:57:49 1.128.6.8
+++ src/sys/dev/mii/miidevs.h 2020/04/14 18:11:35 1.128.6.9
@@ -1,20 +1,20 @@ @@ -1,20 +1,20 @@
1/* $NetBSD: miidevs.h,v 1.128.6.8 2019/11/25 15:57:49 martin Exp $ */ 1/* $NetBSD: miidevs.h,v 1.128.6.9 2020/04/14 18:11:35 martin Exp $ */
2 2
3/* 3/*
4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
5 * 5 *
6 * generated from: 6 * generated from:
7 * NetBSD: miidevs,v 1.125.6.8 2019/11/25 15:57:23 martin Exp 7 * NetBSD: miidevs,v 1.125.6.9 2020/04/14 17:57:17 martin Exp
8 */ 8 */
9 9
10/*- 10/*-
11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
12 * All rights reserved. 12 * All rights reserved.
13 * 13 *
14 * This code is derived from software contributed to The NetBSD Foundation 14 * This code is derived from software contributed to The NetBSD Foundation
15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
16 * NASA Ames Research Center. 16 * NASA Ames Research Center.
17 * 17 *
18 * Redistribution and use in source and binary forms, with or without 18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions 19 * modification, are permitted provided that the following conditions
20 * are met: 20 * are met:
@@ -50,101 +50,104 @@ @@ -50,101 +50,104 @@
50 * The MII_OUI() macro in "miivar.h" reflects this. 50 * The MII_OUI() macro in "miivar.h" reflects this.
51 * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here 51 * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here
52 * which is mangled accordingly to compensate. 52 * which is mangled accordingly to compensate.
53 */ 53 */
54 54
55/* 55/*
56 * Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h 56 * Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h
57 */ 57 */
58 58
59#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */ 59#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
60#define MII_OUI_TRIDIUM 0x0001f0 /* Tridium */ 60#define MII_OUI_TRIDIUM 0x0001f0 /* Tridium */
61#define MII_OUI_DATATRACK 0x0002c6 /* Data Track Technology */ 61#define MII_OUI_DATATRACK 0x0002c6 /* Data Track Technology */
62#define MII_OUI_AGERE 0x00053d /* Agere */ 62#define MII_OUI_AGERE 0x00053d /* Agere */
 63#define MII_OUI_QUAKE 0x000897 /* Quake Technologies */
63#define MII_OUI_BANKSPEED 0x0006b8 /* Bankspeed Pty */ 64#define MII_OUI_BANKSPEED 0x0006b8 /* Bankspeed Pty */
64#define MII_OUI_NETEXCELL 0x0008bb /* NetExcell */ 65#define MII_OUI_NETEXCELL 0x0008bb /* NetExcell */
65#define MII_OUI_NETAS 0x0009c3 /* Netas */ 66#define MII_OUI_NETAS 0x0009c3 /* Netas */
66#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */ 67#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */
 68#define MII_OUI_AELUROS 0x000b25 /* Aeluros */
67#define MII_OUI_RALINK 0x000c43 /* Ralink Technology */ 69#define MII_OUI_RALINK 0x000c43 /* Ralink Technology */
68#define MII_OUI_ASIX 0x000ec6 /* ASIX */ 70#define MII_OUI_ASIX 0x000ec6 /* ASIX */
69#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */ 71#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
70#define MII_OUI_MICREL 0x0010a1 /* Micrel */ 72#define MII_OUI_MICREL 0x0010a1 /* Micrel */
71#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */ 73#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
72#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */ 74#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */
73#define MII_OUI_SUNPLUS 0x001105 /* Sunplus Technology */ 75#define MII_OUI_SUNPLUS 0x001105 /* Sunplus Technology */
74#define MII_OUI_ATHEROS 0x001374 /* Atheros */ 
75#define MII_OUI_TERANETICS 0x0014a6 /* Teranetics */ 76#define MII_OUI_TERANETICS 0x0014a6 /* Teranetics */
76#define MII_OUI_RALINK2 0x0017a5 /* Ralink Technology */ 77#define MII_OUI_RALINK2 0x0017a5 /* Ralink Technology */
77#define MII_OUI_AQUANTIA 0x0017b6 /* Aquantia Corporation */ 78#define MII_OUI_AQUANTIA 0x0017b6 /* Aquantia Corporation */
78#define MII_OUI_BROADCOM3 0x001be9 /* Broadcom Corporation */ 79#define MII_OUI_BROADCOM3 0x001be9 /* Broadcom Corporation */
79#define MII_OUI_LEVEL1 0x00207b /* Level 1 */ 80#define MII_OUI_LEVEL1 0x00207b /* Level 1 */
80#define MII_OUI_VIA 0x004063 /* VIA Technologies */ 
81#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */ 81#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
82#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */ 82#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
83#define MII_OUI_AMLOGIC 0x006051 /* Amlogic */ 83#define MII_OUI_AMLOGIC 0x006051 /* Amlogic */
84#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */ 84#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
85#define MII_OUI_SMSC 0x00800f /* SMSC */ 85#define MII_OUI_SMSC 0x00800f /* SMSC */
86#define MII_OUI_SEEQ 0x00a07d /* Seeq */ 86#define MII_OUI_SEEQ 0x00a07d /* Seeq */
87#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ 87#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */
88#define MII_OUI_INTEL 0x00aa00 /* Intel */ 88#define MII_OUI_INTEL 0x00aa00 /* Intel */
89#define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */ 89#define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */
90#define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */ 90#define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */
91#define MII_OUI_ATTANSIC 0x00c82e /* Attansic Technology */ 91#define MII_OUI_ATTANSIC 0x00c82e /* Attansic Technology */
92#define MII_OUI_RDC 0x00d02d /* RDC Semiconductor */ 
93#define MII_OUI_JMICRON 0x00d831 /* JMicron */ 92#define MII_OUI_JMICRON 0x00d831 /* JMicron */
94#define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */ 93#define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */
95#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ 94#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
96#define MII_OUI_REALTEK 0x00e04c /* RealTek */ 95#define MII_OUI_REALTEK 0x00e04c /* RealTek */
97#define MII_OUI_ADMTEK 0x00e092 /* ADMtek */ 96#define MII_OUI_ADMTEK 0x00e092 /* ADMtek */
98#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */ 97#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
99#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */ 98#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
100#define MII_OUI_TI 0x080028 /* Texas Instruments */ 99#define MII_OUI_TI 0x080028 /* Texas Instruments */
101#define MII_OUI_BROADCOM4 0x18c086 /* Broadcom Corporation */ 100#define MII_OUI_BROADCOM4 0x18c086 /* Broadcom Corporation */
102#define MII_OUI_RENESAS 0x749050 /* Renesas */ 101#define MII_OUI_RENESAS 0x749050 /* Renesas */
103 102
104/* Unregistered or wrong OUI */ 103/* Unregistered or wrong OUI */
105#define MII_OUI_yyREALTEK 0x000004 /* Realtek */ 104#define MII_OUI_yyREALTEK 0x000004 /* Realtek */
106#define MII_OUI_yyAMD 0x000058 /* Advanced Micro Devices */ 105#define MII_OUI_yyAMD 0x000058 /* Advanced Micro Devices */
 106#define MII_OUI_xxVIA 0x0002c6 /* VIA Technologies */
107#define MII_OUI_xxMYSON 0x00032d /* Myson Technology */ 107#define MII_OUI_xxMYSON 0x00032d /* Myson Technology */
108#define MII_OUI_xxTSC 0x00039c /* TDK Semiconductor */ 108#define MII_OUI_xxTSC 0x00039c /* TDK Semiconductor */
109#define MII_OUI_xxASIX 0x000674 /* Asix Semiconductor */ 109#define MII_OUI_xxASIX 0x000674 /* Asix Semiconductor */
110#define MII_OUI_xxDAVICOM 0x000676 /* Davicom Semiconductor */ 110#define MII_OUI_xxDAVICOM 0x000676 /* Davicom Semiconductor */
111#define MII_OUI_xxAMLOGIC 0x00068a /* Amlogic */ 111#define MII_OUI_xxAMLOGIC 0x00068a /* Amlogic */
112#define MII_OUI_xxQUALSEMI 0x00068a /* Quality Semiconductor */ 112#define MII_OUI_xxQUALSEMI 0x00068a /* Quality Semiconductor */
113#define MII_OUI_xxREALTEK 0x000732 /* Realtek */ 113#define MII_OUI_xxREALTEK 0x000732 /* Realtek */
114#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */ 114#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */
115#define MII_OUI_xxPMCSIERRA 0x0009c0 /* PMC-Sierra */ 115#define MII_OUI_xxPMCSIERRA 0x0009c0 /* PMC-Sierra */
116#define MII_OUI_xxICPLUS 0x0009c3 /* IC Plus Corp. */ 116#define MII_OUI_xxICPLUS 0x0009c3 /* IC Plus Corp. */
117#define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */ 117#define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */
118#define MII_OUI_xxINTEL 0x001f00 /* Intel */ 118#define MII_OUI_xxINTEL 0x001f00 /* Intel */
119#define MII_OUI_xxBROADCOM_ALT1 0x0050ef /* Broadcom Corporation */ 119#define MII_OUI_xxBROADCOM_ALT1 0x0050ef /* Broadcom Corporation */
120#define MII_OUI_yyINTEL 0x005500 /* Intel */ 120#define MII_OUI_yyINTEL 0x005500 /* Intel */
121#define MII_OUI_yyASIX 0x007063 /* Asix Semiconductor */ 121#define MII_OUI_yyASIX 0x007063 /* Asix Semiconductor */
122#define MII_OUI_xxVITESSE 0x008083 /* Vitesse Semiconductor */ 122#define MII_OUI_xxVITESSE 0x008083 /* Vitesse Semiconductor */
123#define MII_OUI_xxPMCSIERRA2 0x009057 /* PMC-Sierra */ 123#define MII_OUI_xxPMCSIERRA2 0x009057 /* PMC-Sierra */
124#define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */ 124#define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */
 125#define MII_OUI_xxRDC 0x00d02d /* RDC Semiconductor */
125#define MII_OUI_xxNATSEMI 0x1000e8 /* National Semiconductor */ 126#define MII_OUI_xxNATSEMI 0x1000e8 /* National Semiconductor */
126#define MII_OUI_xxLEVEL1 0x782000 /* Level 1 */ 127#define MII_OUI_xxLEVEL1 0x782000 /* Level 1 */
127#define MII_OUI_xxXAQTI 0xace000 /* XaQti Corp. */ 128#define MII_OUI_xxXAQTI 0xace000 /* XaQti Corp. */
128 129
129/* 130/*
130 * List of known models. Grouped by oui. 131 * List of known models. Grouped by oui.
131 */ 132 */
132 133
133/* 134/*
134 * Agere PHYs 135 * Agere PHYs
135 */ 136 */
136#define MII_MODEL_AGERE_ET1011 0x0004 137#define MII_MODEL_AGERE_ET1011 0x0001
137#define MII_STR_AGERE_ET1011 "Agere ET1011 10/100/1000baseT PHY" 138#define MII_STR_AGERE_ET1011 "ET1011 10/100/1000baseT PHY"
 139#define MII_MODEL_AGERE_ET1011C 0x0004
 140#define MII_STR_AGERE_ET1011C "ET1011C 10/100/1000baseT PHY"
138 141
139/* Asix semiconductor PHYs */ 142/* Asix semiconductor PHYs */
140#define MII_MODEL_xxASIX_AX88X9X 0x0031 143#define MII_MODEL_xxASIX_AX88X9X 0x0031
141#define MII_STR_xxASIX_AX88X9X "Ax88x9x internal PHY" 144#define MII_STR_xxASIX_AX88X9X "Ax88x9x internal PHY"
142#define MII_MODEL_yyASIX_AX88772 0x0001 145#define MII_MODEL_yyASIX_AX88772 0x0001
143#define MII_STR_yyASIX_AX88772 "AX88772 internal PHY" 146#define MII_STR_yyASIX_AX88772 "AX88772 internal PHY"
144#define MII_MODEL_yyASIX_AX88772A 0x0006 147#define MII_MODEL_yyASIX_AX88772A 0x0006
145#define MII_STR_yyASIX_AX88772A "AX88772A internal PHY" 148#define MII_STR_yyASIX_AX88772A "AX88772A internal PHY"
146#define MII_MODEL_yyASIX_AX88772B 0x0008 149#define MII_MODEL_yyASIX_AX88772B 0x0008
147#define MII_STR_yyASIX_AX88772B "AX88772B internal PHY" 150#define MII_STR_yyASIX_AX88772B "AX88772B internal PHY"
148 151
149/* Altima Communications PHYs */ 152/* Altima Communications PHYs */
150/* Don't know the model for ACXXX */ 153/* Don't know the model for ACXXX */
@@ -156,33 +159,27 @@ @@ -156,33 +159,27 @@
156#define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface" 159#define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface"
157/* AMD Am79C87[45] have ALTIMA OUI */ 160/* AMD Am79C87[45] have ALTIMA OUI */
158#define MII_MODEL_ALTIMA_Am79C875 0x0014 161#define MII_MODEL_ALTIMA_Am79C875 0x0014
159#define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface" 162#define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface"
160#define MII_MODEL_ALTIMA_Am79C874 0x0021 163#define MII_MODEL_ALTIMA_Am79C874 0x0021
161#define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface" 164#define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface"
162 165
163/* Amlogic PHYs */ 166/* Amlogic PHYs */
164#define MII_MODEL_AMLOGIC_GXL 0x0000 167#define MII_MODEL_AMLOGIC_GXL 0x0000
165#define MII_STR_AMLOGIC_GXL "Meson GXL internal PHY" 168#define MII_STR_AMLOGIC_GXL "Meson GXL internal PHY"
166#define MII_MODEL_xxAMLOGIC_GXL 0x0000 169#define MII_MODEL_xxAMLOGIC_GXL 0x0000
167#define MII_STR_xxAMLOGIC_GXL "Meson GXL internal PHY" 170#define MII_STR_xxAMLOGIC_GXL "Meson GXL internal PHY"
168 171
169/* Atheros PHYs */ 172/* Attansic/Atheros PHYs */
170#define MII_MODEL_ATHEROS_F1 0x0001 
171#define MII_STR_ATHEROS_F1 "F1 10/100/1000 PHY" 
172#define MII_MODEL_ATHEROS_F2 0x0002 
173#define MII_STR_ATHEROS_F2 "F2 10/100 PHY" 
174 
175/* Attansic PHYs */ 
176#define MII_MODEL_ATTANSIC_L1 0x0001 173#define MII_MODEL_ATTANSIC_L1 0x0001
177#define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY" 174#define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY"
178#define MII_MODEL_ATTANSIC_L2 0x0002 175#define MII_MODEL_ATTANSIC_L2 0x0002
179#define MII_STR_ATTANSIC_L2 "L2 10/100 PHY" 176#define MII_STR_ATTANSIC_L2 "L2 10/100 PHY"
180#define MII_MODEL_ATTANSIC_AR8021 0x0004 177#define MII_MODEL_ATTANSIC_AR8021 0x0004
181#define MII_STR_ATTANSIC_AR8021 "Atheros AR8021 10/100/1000 PHY" 178#define MII_STR_ATTANSIC_AR8021 "Atheros AR8021 10/100/1000 PHY"
182#define MII_MODEL_ATTANSIC_AR8035 0x0007 179#define MII_MODEL_ATTANSIC_AR8035 0x0007
183#define MII_STR_ATTANSIC_AR8035 "Atheros AR8035 10/100/1000 PHY" 180#define MII_STR_ATTANSIC_AR8035 "Atheros AR8035 10/100/1000 PHY"
184 181
185/* Advanced Micro Devices PHYs */ 182/* Advanced Micro Devices PHYs */
186/* see Davicom DM9101 for Am79C873 */ 183/* see Davicom DM9101 for Am79C873 */
187#define MII_MODEL_yyAMD_79C972_10T 0x0001 184#define MII_MODEL_yyAMD_79C972_10T 0x0001
188#define MII_STR_yyAMD_79C972_10T "Am79C972 internal 10BASE-T interface" 185#define MII_STR_yyAMD_79C972_10T "Am79C972 internal 10BASE-T interface"
@@ -290,26 +287,28 @@ @@ -290,26 +287,28 @@
290#define MII_STR_BROADCOM2_BCM5709S "BCM5709S 1000/2500baseSX PHY" 287#define MII_STR_BROADCOM2_BCM5709S "BCM5709S 1000/2500baseSX PHY"
291#define MII_MODEL_BROADCOM3_BCM57780 0x0019 288#define MII_MODEL_BROADCOM3_BCM57780 0x0019
292#define MII_STR_BROADCOM3_BCM57780 "BCM57780 1000BASE-T media interface" 289#define MII_STR_BROADCOM3_BCM57780 "BCM57780 1000BASE-T media interface"
293#define MII_MODEL_BROADCOM3_BCM5717C 0x0020 290#define MII_MODEL_BROADCOM3_BCM5717C 0x0020
294#define MII_STR_BROADCOM3_BCM5717C "BCM5717C 1000BASE-T media interface" 291#define MII_STR_BROADCOM3_BCM5717C "BCM5717C 1000BASE-T media interface"
295#define MII_MODEL_BROADCOM3_BCM5719C 0x0022 292#define MII_MODEL_BROADCOM3_BCM5719C 0x0022
296#define MII_STR_BROADCOM3_BCM5719C "BCM5719C 1000BASE-T media interface" 293#define MII_STR_BROADCOM3_BCM5719C "BCM5719C 1000BASE-T media interface"
297#define MII_MODEL_BROADCOM3_BCM57765 0x0024 294#define MII_MODEL_BROADCOM3_BCM57765 0x0024
298#define MII_STR_BROADCOM3_BCM57765 "BCM57765 1000BASE-T media interface" 295#define MII_STR_BROADCOM3_BCM57765 "BCM57765 1000BASE-T media interface"
299#define MII_MODEL_BROADCOM3_BCM53125 0x0032 296#define MII_MODEL_BROADCOM3_BCM53125 0x0032
300#define MII_STR_BROADCOM3_BCM53125 "BCM53125 1000BASE-T switch" 297#define MII_STR_BROADCOM3_BCM53125 "BCM53125 1000BASE-T switch"
301#define MII_MODEL_BROADCOM3_BCM5720C 0x0036 298#define MII_MODEL_BROADCOM3_BCM5720C 0x0036
302#define MII_STR_BROADCOM3_BCM5720C "BCM5720C 1000BASE-T media interface" 299#define MII_STR_BROADCOM3_BCM5720C "BCM5720C 1000BASE-T media interface"
 300#define MII_MODEL_BROADCOM4_BCM54213PE 0x000a
 301#define MII_STR_BROADCOM4_BCM54213PE "BCM54213PE 1000BASE-T media interface"
303#define MII_MODEL_BROADCOM4_BCM5725C 0x0038 302#define MII_MODEL_BROADCOM4_BCM5725C 0x0038
304#define MII_STR_BROADCOM4_BCM5725C "BCM5725C 1000BASE-T media interface" 303#define MII_STR_BROADCOM4_BCM5725C "BCM5725C 1000BASE-T media interface"
305#define MII_MODEL_xxBROADCOM_ALT1_BCM5906 0x0004 304#define MII_MODEL_xxBROADCOM_ALT1_BCM5906 0x0004
306#define MII_STR_xxBROADCOM_ALT1_BCM5906 "BCM5906 10/100baseTX media interface" 305#define MII_STR_xxBROADCOM_ALT1_BCM5906 "BCM5906 10/100baseTX media interface"
307 306
308/* Cicada Semiconductor PHYs (-> Vitesse -> Microsemi) */ 307/* Cicada Semiconductor PHYs (-> Vitesse -> Microsemi) */
309 308
310#define MII_MODEL_xxCICADA_CIS8201 0x0001 309#define MII_MODEL_xxCICADA_CIS8201 0x0001
311#define MII_STR_xxCICADA_CIS8201 "Cicada CIS8201 10/100/1000TX PHY" 310#define MII_STR_xxCICADA_CIS8201 "Cicada CIS8201 10/100/1000TX PHY"
312#define MII_MODEL_xxCICADA_CIS8204 0x0004 311#define MII_MODEL_xxCICADA_CIS8204 0x0004
313#define MII_STR_xxCICADA_CIS8204 "Cicada CIS8204 10/100/1000TX PHY" 312#define MII_STR_xxCICADA_CIS8204 "Cicada CIS8204 10/100/1000TX PHY"
314#define MII_MODEL_xxCICADA_VSC8211 0x000b 313#define MII_MODEL_xxCICADA_VSC8211 0x000b
315#define MII_STR_xxCICADA_VSC8211 "Cicada VSC8211 10/100/1000TX PHY" 314#define MII_STR_xxCICADA_VSC8211 "Cicada VSC8211 10/100/1000TX PHY"
@@ -529,28 +528,32 @@ @@ -529,28 +528,32 @@
529#define MII_STR_xxPMCSIERRA_PM8351 "PM8351 OctalPHY Gigabit interface" 528#define MII_STR_xxPMCSIERRA_PM8351 "PM8351 OctalPHY Gigabit interface"
530#define MII_MODEL_xxPMCSIERRA2_PM8352 0x0002 529#define MII_MODEL_xxPMCSIERRA2_PM8352 0x0002
531#define MII_STR_xxPMCSIERRA2_PM8352 "PM8352 OctalPHY Gigabit interface" 530#define MII_STR_xxPMCSIERRA2_PM8352 "PM8352 OctalPHY Gigabit interface"
532#define MII_MODEL_xxPMCSIERRA2_PM8353 0x0003 531#define MII_MODEL_xxPMCSIERRA2_PM8353 0x0003
533#define MII_STR_xxPMCSIERRA2_PM8353 "PM8353 QuadPHY Gigabit interface" 532#define MII_STR_xxPMCSIERRA2_PM8353 "PM8353 QuadPHY Gigabit interface"
534#define MII_MODEL_PMCSIERRA_PM8354 0x0004 533#define MII_MODEL_PMCSIERRA_PM8354 0x0004
535#define MII_STR_PMCSIERRA_PM8354 "PM8354 QuadPHY Gigabit interface" 534#define MII_STR_PMCSIERRA_PM8354 "PM8354 QuadPHY Gigabit interface"
536 535
537/* Quality Semiconductor PHYs */ 536/* Quality Semiconductor PHYs */
538#define MII_MODEL_xxQUALSEMI_QS6612 0x0000 537#define MII_MODEL_xxQUALSEMI_QS6612 0x0000
539#define MII_STR_xxQUALSEMI_QS6612 "QS6612 10/100 media interface" 538#define MII_STR_xxQUALSEMI_QS6612 "QS6612 10/100 media interface"
540 539
541/* RDC Semiconductor PHYs */ 540/* RDC Semiconductor PHYs */
542#define MII_MODEL_RDC_R6040 0x0003 541#define MII_MODEL_xxRDC_R6040 0x0003
543#define MII_STR_RDC_R6040 "R6040 10/100 media interface" 542#define MII_STR_xxRDC_R6040 "R6040 10/100 media interface"
 543#define MII_MODEL_xxRDC_R6040_2 0x0005
 544#define MII_STR_xxRDC_R6040_2 "R6040 10/100 media interface"
 545#define MII_MODEL_xxRDC_R6040_3 0x0006
 546#define MII_STR_xxRDC_R6040_3 "R6040 10/100 media interface"
544 547
545/* RealTek PHYs */ 548/* RealTek PHYs */
546#define MII_MODEL_xxREALTEK_RTL8169S 0x0011 549#define MII_MODEL_xxREALTEK_RTL8169S 0x0011
547#define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" 550#define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface"
548#define MII_MODEL_yyREALTEK_RTL8201L 0x0020 551#define MII_MODEL_yyREALTEK_RTL8201L 0x0020
549#define MII_STR_yyREALTEK_RTL8201L "RTL8201L 10/100 media interface" 552#define MII_STR_yyREALTEK_RTL8201L "RTL8201L 10/100 media interface"
550#define MII_MODEL_REALTEK_RTL8251 0x0000 553#define MII_MODEL_REALTEK_RTL8251 0x0000
551#define MII_STR_REALTEK_RTL8251 "RTL8251 1000BASE-T media interface" 554#define MII_STR_REALTEK_RTL8251 "RTL8251 1000BASE-T media interface"
552#define MII_MODEL_REALTEK_RTL8201E 0x0008 555#define MII_MODEL_REALTEK_RTL8201E 0x0008
553#define MII_STR_REALTEK_RTL8201E "RTL8201E 10/100 media interface" 556#define MII_STR_REALTEK_RTL8201E "RTL8201E 10/100 media interface"
554#define MII_MODEL_REALTEK_RTL8169S 0x0011 557#define MII_MODEL_REALTEK_RTL8169S 0x0011
555#define MII_STR_REALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" 558#define MII_STR_REALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface"
556 559
@@ -574,44 +577,48 @@ @@ -574,44 +577,48 @@
574#define MII_MODEL_SMSC_LAN911X 0x000d 577#define MII_MODEL_SMSC_LAN911X 0x000d
575#define MII_STR_SMSC_LAN911X "SMSC LAN911X internal 10/100 PHY" 578#define MII_STR_SMSC_LAN911X "SMSC LAN911X internal 10/100 PHY"
576#define MII_MODEL_SMSC_LAN75XX 0x000e 579#define MII_MODEL_SMSC_LAN75XX 0x000e
577#define MII_STR_SMSC_LAN75XX "SMSC LAN75XX internal 10/100 PHY" 580#define MII_STR_SMSC_LAN75XX "SMSC LAN75XX internal 10/100 PHY"
578#define MII_MODEL_SMSC_LAN8710_LAN8720 0x000f 581#define MII_MODEL_SMSC_LAN8710_LAN8720 0x000f
579#define MII_STR_SMSC_LAN8710_LAN8720 "SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver" 582#define MII_STR_SMSC_LAN8710_LAN8720 "SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver"
580#define MII_MODEL_SMSC_LAN8740 0x0011 583#define MII_MODEL_SMSC_LAN8740 0x0011
581#define MII_STR_SMSC_LAN8740 "SMSC LAN8740 10/100 media interface" 584#define MII_STR_SMSC_LAN8740 "SMSC LAN8740 10/100 media interface"
582#define MII_MODEL_SMSC_LAN8741A 0x0012 585#define MII_MODEL_SMSC_LAN8741A 0x0012
583#define MII_STR_SMSC_LAN8741A "SMSC LAN8741A 10/100 media interface" 586#define MII_STR_SMSC_LAN8741A "SMSC LAN8741A 10/100 media interface"
584#define MII_MODEL_SMSC_LAN8742 0x0013 587#define MII_MODEL_SMSC_LAN8742 0x0013
585#define MII_STR_SMSC_LAN8742 "SMSC LAN8742 10/100 media interface" 588#define MII_STR_SMSC_LAN8742 "SMSC LAN8742 10/100 media interface"
586 589
 590/* Teranetics PHY */
 591#define MII_MODEL_TERANETICS_TN1010 0x0001
 592#define MII_STR_TERANETICS_TN1010 "Teranetics TN1010 10GBase-T PHY"
 593
587/* Texas Instruments PHYs */ 594/* Texas Instruments PHYs */
588#define MII_MODEL_TI_TLAN10T 0x0001 595#define MII_MODEL_TI_TLAN10T 0x0001
589#define MII_STR_TI_TLAN10T "ThunderLAN 10BASE-T media interface" 596#define MII_STR_TI_TLAN10T "ThunderLAN 10BASE-T media interface"
590#define MII_MODEL_TI_100VGPMI 0x0002 597#define MII_MODEL_TI_100VGPMI 0x0002
591#define MII_STR_TI_100VGPMI "ThunderLAN 100VG-AnyLan media interface" 598#define MII_STR_TI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
592#define MII_MODEL_TI_TNETE2101 0x0003 599#define MII_MODEL_TI_TNETE2101 0x0003
593#define MII_STR_TI_TNETE2101 "TNETE2101 media interface" 600#define MII_STR_TI_TNETE2101 "TNETE2101 media interface"
594 601
595/* TDK Semiconductor PHYs */ 602/* TDK Semiconductor PHYs */
596#define MII_MODEL_xxTSC_78Q2120 0x0014 603#define MII_MODEL_xxTSC_78Q2120 0x0014
597#define MII_STR_xxTSC_78Q2120 "78Q2120 10/100 media interface" 604#define MII_STR_xxTSC_78Q2120 "78Q2120 10/100 media interface"
598#define MII_MODEL_xxTSC_78Q2121 0x0015 605#define MII_MODEL_xxTSC_78Q2121 0x0015
599#define MII_STR_xxTSC_78Q2121 "78Q2121 100BASE-TX media interface" 606#define MII_STR_xxTSC_78Q2121 "78Q2121 100BASE-TX media interface"
600 607
601/* VIA Technologies PHYs */ 608/* VIA Technologies PHYs */
602#define MII_MODEL_VIA_VT6103 0x0032 609#define MII_MODEL_xxVIA_VT6103 0x0032
603#define MII_STR_VIA_VT6103 "VT6103 10/100 PHY" 610#define MII_STR_xxVIA_VT6103 "VT6103 10/100 PHY"
604#define MII_MODEL_VIA_VT6103_2 0x0034 611#define MII_MODEL_xxVIA_VT6103_2 0x0034
605#define MII_STR_VIA_VT6103_2 "VT6103 10/100 PHY" 612#define MII_STR_xxVIA_VT6103_2 "VT6103 10/100 PHY"
606 613
607/* Vitesse PHYs (Now Microsemi) */ 614/* Vitesse PHYs (Now Microsemi) */
608#define MII_MODEL_xxVITESSE_VSC8601 0x0002 615#define MII_MODEL_xxVITESSE_VSC8601 0x0002
609#define MII_STR_xxVITESSE_VSC8601 "VSC8601 10/100/1000 PHY" 616#define MII_STR_xxVITESSE_VSC8601 "VSC8601 10/100/1000 PHY"
610#define MII_MODEL_xxVITESSE_VSC8641 0x0003 617#define MII_MODEL_xxVITESSE_VSC8641 0x0003
611#define MII_STR_xxVITESSE_VSC8641 "Vitesse VSC8641 10/100/1000TX PHY" 618#define MII_STR_xxVITESSE_VSC8641 "Vitesse VSC8641 10/100/1000TX PHY"
612#define MII_MODEL_xxVITESSE_VSC8501 0x0013 619#define MII_MODEL_xxVITESSE_VSC8501 0x0013
613#define MII_STR_xxVITESSE_VSC8501 "Vitesse VSC8501 10/100/1000TX PHY" 620#define MII_STR_xxVITESSE_VSC8501 "Vitesse VSC8501 10/100/1000TX PHY"
614 621
615/* XaQti Corp. PHYs */ 622/* XaQti Corp. PHYs */
616#define MII_MODEL_xxXAQTI_XMACII 0x0000 623#define MII_MODEL_xxXAQTI_XMACII 0x0000
617#define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface" 624#define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
cvs diff -r1.116.6.8 -r1.116.6.9 src/sys/dev/mii/miidevs_data.h (expand / switch to unified diff)

--- src/sys/dev/mii/miidevs_data.h 2019/11/25 15:57:49 1.116.6.8
+++ src/sys/dev/mii/miidevs_data.h 2020/04/14 18:11:35 1.116.6.9
@@ -1,20 +1,20 @@ @@ -1,20 +1,20 @@
1/* $NetBSD: miidevs_data.h,v 1.116.6.8 2019/11/25 15:57:49 martin Exp $ */ 1/* $NetBSD: miidevs_data.h,v 1.116.6.9 2020/04/14 18:11:35 martin Exp $ */
2 2
3/* 3/*
4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
5 * 5 *
6 * generated from: 6 * generated from:
7 * NetBSD: miidevs,v 1.125.6.8 2019/11/25 15:57:23 martin Exp 7 * NetBSD: miidevs,v 1.125.6.9 2020/04/14 17:57:17 martin Exp
8 */ 8 */
9 9
10/*- 10/*-
11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
12 * All rights reserved. 12 * All rights reserved.
13 * 13 *
14 * This code is derived from software contributed to The NetBSD Foundation 14 * This code is derived from software contributed to The NetBSD Foundation
15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
16 * NASA Ames Research Center. 16 * NASA Ames Research Center.
17 * 17 *
18 * Redistribution and use in source and binary forms, with or without 18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions 19 * modification, are permitted provided that the following conditions
20 * are met: 20 * are met:
@@ -28,39 +28,38 @@ @@ -28,39 +28,38 @@
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE. 37 * POSSIBILITY OF SUCH DAMAGE.
38 */ 38 */
39struct mii_knowndev mii_knowndevs[] = { 39struct mii_knowndev mii_knowndevs[] = {
40 { MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, MII_STR_AGERE_ET1011 }, 40 { MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, MII_STR_AGERE_ET1011 },
 41 { MII_OUI_AGERE, MII_MODEL_AGERE_ET1011C, MII_STR_AGERE_ET1011C },
41 { MII_OUI_xxASIX, MII_MODEL_xxASIX_AX88X9X, MII_STR_xxASIX_AX88X9X }, 42 { MII_OUI_xxASIX, MII_MODEL_xxASIX_AX88X9X, MII_STR_xxASIX_AX88X9X },
42 { MII_OUI_yyASIX, MII_MODEL_yyASIX_AX88772, MII_STR_yyASIX_AX88772 }, 43 { MII_OUI_yyASIX, MII_MODEL_yyASIX_AX88772, MII_STR_yyASIX_AX88772 },
43 { MII_OUI_yyASIX, MII_MODEL_yyASIX_AX88772A, MII_STR_yyASIX_AX88772A }, 44 { MII_OUI_yyASIX, MII_MODEL_yyASIX_AX88772A, MII_STR_yyASIX_AX88772A },
44 { MII_OUI_yyASIX, MII_MODEL_yyASIX_AX88772B, MII_STR_yyASIX_AX88772B }, 45 { MII_OUI_yyASIX, MII_MODEL_yyASIX_AX88772B, MII_STR_yyASIX_AX88772B },
45 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_ACXXX, MII_STR_ALTIMA_ACXXX }, 46 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_ACXXX, MII_STR_ALTIMA_ACXXX },
46 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101L, MII_STR_ALTIMA_AC101L }, 47 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101L, MII_STR_ALTIMA_AC101L },
47 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 }, 48 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 },
48 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C875, MII_STR_ALTIMA_Am79C875 }, 49 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C875, MII_STR_ALTIMA_Am79C875 },
49 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C874, MII_STR_ALTIMA_Am79C874 }, 50 { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C874, MII_STR_ALTIMA_Am79C874 },
50 { MII_OUI_AMLOGIC, MII_MODEL_AMLOGIC_GXL, MII_STR_AMLOGIC_GXL }, 51 { MII_OUI_AMLOGIC, MII_MODEL_AMLOGIC_GXL, MII_STR_AMLOGIC_GXL },
51 { MII_OUI_xxAMLOGIC, MII_MODEL_xxAMLOGIC_GXL, MII_STR_xxAMLOGIC_GXL }, 52 { MII_OUI_xxAMLOGIC, MII_MODEL_xxAMLOGIC_GXL, MII_STR_xxAMLOGIC_GXL },
52 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, MII_STR_ATHEROS_F1 }, 
53 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2, MII_STR_ATHEROS_F2 }, 
54 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, MII_STR_ATTANSIC_L1 }, 53 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, MII_STR_ATTANSIC_L1 },
55 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, MII_STR_ATTANSIC_L2 }, 54 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, MII_STR_ATTANSIC_L2 },
56 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, MII_STR_ATTANSIC_AR8021 }, 55 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, MII_STR_ATTANSIC_AR8021 },
57 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8035, MII_STR_ATTANSIC_AR8035 }, 56 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8035, MII_STR_ATTANSIC_AR8035 },
58 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79C972_10T, MII_STR_yyAMD_79C972_10T }, 57 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79C972_10T, MII_STR_yyAMD_79C972_10T },
59 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c973phy, MII_STR_yyAMD_79c973phy }, 58 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c973phy, MII_STR_yyAMD_79c973phy },
60 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901, MII_STR_yyAMD_79c901 }, 59 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901, MII_STR_yyAMD_79c901 },
61 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901home, MII_STR_yyAMD_79c901home }, 60 { MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901home, MII_STR_yyAMD_79c901home },
62 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905B, MII_STR_xxBROADCOM_3C905B }, 61 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905B, MII_STR_xxBROADCOM_3C905B },
63 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905C, MII_STR_xxBROADCOM_3C905C }, 62 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905C, MII_STR_xxBROADCOM_3C905C },
64 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5221, MII_STR_xxBROADCOM_BCM5221 }, 63 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5221, MII_STR_xxBROADCOM_BCM5221 },
65 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5201, MII_STR_xxBROADCOM_BCM5201 }, 64 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5201, MII_STR_xxBROADCOM_BCM5201 },
66 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5214, MII_STR_xxBROADCOM_BCM5214 }, 65 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5214, MII_STR_xxBROADCOM_BCM5214 },
@@ -102,26 +101,27 @@ struct mii_knowndev mii_knowndevs[] = { @@ -102,26 +101,27 @@ struct mii_knowndev mii_knowndevs[] = {
102 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, MII_STR_BROADCOM2_BCM5785 }, 101 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, MII_STR_BROADCOM2_BCM5785 },
103 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, MII_STR_BROADCOM2_BCM5709CAX }, 102 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, MII_STR_BROADCOM2_BCM5709CAX },
104 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, MII_STR_BROADCOM2_BCM5722 }, 103 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, MII_STR_BROADCOM2_BCM5722 },
105 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, MII_STR_BROADCOM2_BCM5784 }, 104 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, MII_STR_BROADCOM2_BCM5784 },
106 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, MII_STR_BROADCOM2_BCM5709C }, 105 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, MII_STR_BROADCOM2_BCM5709C },
107 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, MII_STR_BROADCOM2_BCM5761 }, 106 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, MII_STR_BROADCOM2_BCM5761 },
108 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, MII_STR_BROADCOM2_BCM5709S }, 107 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, MII_STR_BROADCOM2_BCM5709S },
109 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, MII_STR_BROADCOM3_BCM57780 }, 108 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, MII_STR_BROADCOM3_BCM57780 },
110 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, MII_STR_BROADCOM3_BCM5717C }, 109 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, MII_STR_BROADCOM3_BCM5717C },
111 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, MII_STR_BROADCOM3_BCM5719C }, 110 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, MII_STR_BROADCOM3_BCM5719C },
112 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, MII_STR_BROADCOM3_BCM57765 }, 111 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, MII_STR_BROADCOM3_BCM57765 },
113 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM53125, MII_STR_BROADCOM3_BCM53125 }, 112 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM53125, MII_STR_BROADCOM3_BCM53125 },
114 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, MII_STR_BROADCOM3_BCM5720C }, 113 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, MII_STR_BROADCOM3_BCM5720C },
 114 { MII_OUI_BROADCOM4, MII_MODEL_BROADCOM4_BCM54213PE, MII_STR_BROADCOM4_BCM54213PE },
115 { MII_OUI_BROADCOM4, MII_MODEL_BROADCOM4_BCM5725C, MII_STR_BROADCOM4_BCM5725C }, 115 { MII_OUI_BROADCOM4, MII_MODEL_BROADCOM4_BCM5725C, MII_STR_BROADCOM4_BCM5725C },
116 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, MII_STR_xxBROADCOM_ALT1_BCM5906 }, 116 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, MII_STR_xxBROADCOM_ALT1_BCM5906 },
117 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CIS8201, MII_STR_xxCICADA_CIS8201 }, 117 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CIS8201, MII_STR_xxCICADA_CIS8201 },
118 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CIS8204, MII_STR_xxCICADA_CIS8204 }, 118 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CIS8204, MII_STR_xxCICADA_CIS8204 },
119 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8211, MII_STR_xxCICADA_VSC8211 }, 119 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8211, MII_STR_xxCICADA_VSC8211 },
120 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8221, MII_STR_xxCICADA_VSC8221 }, 120 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8221, MII_STR_xxCICADA_VSC8221 },
121 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8224, MII_STR_xxCICADA_VSC8224 }, 121 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8224, MII_STR_xxCICADA_VSC8224 },
122 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CIS8201A, MII_STR_xxCICADA_CIS8201A }, 122 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CIS8201A, MII_STR_xxCICADA_CIS8201A },
123 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CIS8201B, MII_STR_xxCICADA_CIS8201B }, 123 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CIS8201B, MII_STR_xxCICADA_CIS8201B },
124 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8234, MII_STR_xxCICADA_VSC8234 }, 124 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8234, MII_STR_xxCICADA_VSC8234 },
125 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8244, MII_STR_xxCICADA_VSC8244 }, 125 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8244, MII_STR_xxCICADA_VSC8244 },
126 { MII_OUI_DAVICOM, MII_MODEL_DAVICOM_DM9101, MII_STR_DAVICOM_DM9101 }, 126 { MII_OUI_DAVICOM, MII_MODEL_DAVICOM_DM9101, MII_STR_DAVICOM_DM9101 },
127 { MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9101, MII_STR_xxDAVICOM_DM9101 }, 127 { MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9101, MII_STR_xxDAVICOM_DM9101 },
@@ -206,44 +206,47 @@ struct mii_knowndev mii_knowndevs[] = { @@ -206,44 +206,47 @@ struct mii_knowndev mii_knowndevs[] = {
206 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 }, 206 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 },
207 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83843, MII_STR_xxNATSEMI_DP83843 }, 207 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83843, MII_STR_xxNATSEMI_DP83843 },
208 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83815, MII_STR_xxNATSEMI_DP83815 }, 208 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83815, MII_STR_xxNATSEMI_DP83815 },
209 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83847, MII_STR_xxNATSEMI_DP83847 }, 209 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83847, MII_STR_xxNATSEMI_DP83847 },
210 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83891, MII_STR_xxNATSEMI_DP83891 }, 210 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83891, MII_STR_xxNATSEMI_DP83891 },
211 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83861, MII_STR_xxNATSEMI_DP83861 }, 211 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83861, MII_STR_xxNATSEMI_DP83861 },
212 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83865, MII_STR_xxNATSEMI_DP83865 }, 212 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83865, MII_STR_xxNATSEMI_DP83865 },
213 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83849, MII_STR_xxNATSEMI_DP83849 }, 213 { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83849, MII_STR_xxNATSEMI_DP83849 },
214 { MII_OUI_xxPMCSIERRA, MII_MODEL_xxPMCSIERRA_PM8351, MII_STR_xxPMCSIERRA_PM8351 }, 214 { MII_OUI_xxPMCSIERRA, MII_MODEL_xxPMCSIERRA_PM8351, MII_STR_xxPMCSIERRA_PM8351 },
215 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8352, MII_STR_xxPMCSIERRA2_PM8352 }, 215 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8352, MII_STR_xxPMCSIERRA2_PM8352 },
216 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8353, MII_STR_xxPMCSIERRA2_PM8353 }, 216 { MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8353, MII_STR_xxPMCSIERRA2_PM8353 },
217 { MII_OUI_PMCSIERRA, MII_MODEL_PMCSIERRA_PM8354, MII_STR_PMCSIERRA_PM8354 }, 217 { MII_OUI_PMCSIERRA, MII_MODEL_PMCSIERRA_PM8354, MII_STR_PMCSIERRA_PM8354 },
218 { MII_OUI_xxQUALSEMI, MII_MODEL_xxQUALSEMI_QS6612, MII_STR_xxQUALSEMI_QS6612 }, 218 { MII_OUI_xxQUALSEMI, MII_MODEL_xxQUALSEMI_QS6612, MII_STR_xxQUALSEMI_QS6612 },
219 { MII_OUI_RDC, MII_MODEL_RDC_R6040, MII_STR_RDC_R6040 }, 219 { MII_OUI_xxRDC, MII_MODEL_xxRDC_R6040, MII_STR_xxRDC_R6040 },
 220 { MII_OUI_xxRDC, MII_MODEL_xxRDC_R6040_2, MII_STR_xxRDC_R6040_2 },
 221 { MII_OUI_xxRDC, MII_MODEL_xxRDC_R6040_3, MII_STR_xxRDC_R6040_3 },
220 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, MII_STR_xxREALTEK_RTL8169S }, 222 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, MII_STR_xxREALTEK_RTL8169S },
221 { MII_OUI_yyREALTEK, MII_MODEL_yyREALTEK_RTL8201L, MII_STR_yyREALTEK_RTL8201L }, 223 { MII_OUI_yyREALTEK, MII_MODEL_yyREALTEK_RTL8201L, MII_STR_yyREALTEK_RTL8201L },
222 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8251, MII_STR_REALTEK_RTL8251 }, 224 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8251, MII_STR_REALTEK_RTL8251 },
223 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8201E, MII_STR_REALTEK_RTL8201E }, 225 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8201E, MII_STR_REALTEK_RTL8201E },
224 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, MII_STR_REALTEK_RTL8169S }, 226 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, MII_STR_REALTEK_RTL8169S },
225 { MII_OUI_SEEQ, MII_MODEL_SEEQ_80220, MII_STR_SEEQ_80220 }, 227 { MII_OUI_SEEQ, MII_MODEL_SEEQ_80220, MII_STR_SEEQ_80220 },
226 { MII_OUI_SEEQ, MII_MODEL_SEEQ_84220, MII_STR_SEEQ_84220 }, 228 { MII_OUI_SEEQ, MII_MODEL_SEEQ_84220, MII_STR_SEEQ_84220 },
227 { MII_OUI_SEEQ, MII_MODEL_SEEQ_80225, MII_STR_SEEQ_80225 }, 229 { MII_OUI_SEEQ, MII_MODEL_SEEQ_80225, MII_STR_SEEQ_80225 },
228 { MII_OUI_SIS, MII_MODEL_SIS_900, MII_STR_SIS_900 }, 230 { MII_OUI_SIS, MII_MODEL_SIS_900, MII_STR_SIS_900 },
229 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN83C185, MII_STR_SMSC_LAN83C185 }, 231 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN83C185, MII_STR_SMSC_LAN83C185 },
230 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8700, MII_STR_SMSC_LAN8700 }, 232 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8700, MII_STR_SMSC_LAN8700 },
231 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN911X, MII_STR_SMSC_LAN911X }, 233 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN911X, MII_STR_SMSC_LAN911X },
232 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN75XX, MII_STR_SMSC_LAN75XX }, 234 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN75XX, MII_STR_SMSC_LAN75XX },
233 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8710_LAN8720, MII_STR_SMSC_LAN8710_LAN8720 }, 235 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8710_LAN8720, MII_STR_SMSC_LAN8710_LAN8720 },
234 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8740, MII_STR_SMSC_LAN8740 }, 236 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8740, MII_STR_SMSC_LAN8740 },
235 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8741A, MII_STR_SMSC_LAN8741A }, 237 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8741A, MII_STR_SMSC_LAN8741A },
236 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8742, MII_STR_SMSC_LAN8742 }, 238 { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8742, MII_STR_SMSC_LAN8742 },
 239 { MII_OUI_TERANETICS, MII_MODEL_TERANETICS_TN1010, MII_STR_TERANETICS_TN1010 },
237 { MII_OUI_TI, MII_MODEL_TI_TLAN10T, MII_STR_TI_TLAN10T }, 240 { MII_OUI_TI, MII_MODEL_TI_TLAN10T, MII_STR_TI_TLAN10T },
238 { MII_OUI_TI, MII_MODEL_TI_100VGPMI, MII_STR_TI_100VGPMI }, 241 { MII_OUI_TI, MII_MODEL_TI_100VGPMI, MII_STR_TI_100VGPMI },
239 { MII_OUI_TI, MII_MODEL_TI_TNETE2101, MII_STR_TI_TNETE2101 }, 242 { MII_OUI_TI, MII_MODEL_TI_TNETE2101, MII_STR_TI_TNETE2101 },
240 { MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2120, MII_STR_xxTSC_78Q2120 }, 243 { MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2120, MII_STR_xxTSC_78Q2120 },
241 { MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2121, MII_STR_xxTSC_78Q2121 }, 244 { MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2121, MII_STR_xxTSC_78Q2121 },
242 { MII_OUI_VIA, MII_MODEL_VIA_VT6103, MII_STR_VIA_VT6103 }, 245 { MII_OUI_xxVIA, MII_MODEL_xxVIA_VT6103, MII_STR_xxVIA_VT6103 },
243 { MII_OUI_VIA, MII_MODEL_VIA_VT6103_2, MII_STR_VIA_VT6103_2 }, 246 { MII_OUI_xxVIA, MII_MODEL_xxVIA_VT6103_2, MII_STR_xxVIA_VT6103_2 },
244 { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8601, MII_STR_xxVITESSE_VSC8601 }, 247 { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8601, MII_STR_xxVITESSE_VSC8601 },
245 { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8641, MII_STR_xxVITESSE_VSC8641 }, 248 { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8641, MII_STR_xxVITESSE_VSC8641 },
246 { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8501, MII_STR_xxVITESSE_VSC8501 }, 249 { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8501, MII_STR_xxVITESSE_VSC8501 },
247 { MII_OUI_xxXAQTI, MII_MODEL_xxXAQTI_XMACII, MII_STR_xxXAQTI_XMACII }, 250 { MII_OUI_xxXAQTI, MII_MODEL_xxXAQTI_XMACII, MII_STR_xxXAQTI_XMACII },
248 { 0, 0, NULL } 251 { 0, 0, NULL }
249}; 252};