Pull up the following, requested by msaitoh in ticket #1530: sys/arch/x86/x86/procfs_machdep.c 1.33-1.36 sys/arch/x86/x86/tsc.c 1.40 sys/arch/x86/x86/specialreg.h 1.159-1.161 usr.sbin/cpuctl/arch/i386.c 1.109-1.110 via patch - Print avx512ifma, cqm_mbm_total, cqm_mbm_local, waitpkg, rdpru, Fast Short Rep Mov(fsrm), AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK. - Rename CPUID Fn8000_0007 %edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion. - Print CPUID 0x80000007 %edx on both Intel and AMD. - Remove ci_max_ext_cpuid from usr.sbin/cpuctl/arch/i386.c because it's the same as ci_cpuid_extlevel. - Use unsigned to avoid undefined behavior in procfs_getonefeatreg().diff -r1.98.2.18 -r1.98.2.19 src/sys/arch/x86/include/specialreg.h
(martin)
--- src/sys/arch/x86/include/specialreg.h 2020/01/31 10:53:29 1.98.2.18
+++ src/sys/arch/x86/include/specialreg.h 2020/04/15 14:25:09 1.98.2.19
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: specialreg.h,v 1.98.2.18 2020/01/31 10:53:29 martin Exp $ */ | 1 | /* $NetBSD: specialreg.h,v 1.98.2.19 2020/04/15 14:25:09 martin Exp $ */ | |
2 | 2 | |||
3 | /*- | 3 | /*- | |
4 | * Copyright (c) 1991 The Regents of the University of California. | 4 | * Copyright (c) 1991 The Regents of the University of California. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | 7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | 8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | 9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | 10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | 11 | * notice, this list of conditions and the following disclaimer. | |
12 | * 2. Redistributions in binary form must reproduce the above copyright | 12 | * 2. Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | 13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | 14 | * documentation and/or other materials provided with the distribution. | |
@@ -418,42 +418,46 @@ | @@ -418,42 +418,46 @@ | |||
418 | "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ | 418 | "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ | |
419 | "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ | 419 | "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ | |
420 | "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ | 420 | "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ | |
421 | "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \ | 421 | "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \ | |
422 | "f\21\5MAWAU\0" \ | 422 | "f\21\5MAWAU\0" \ | |
423 | "b\26RDPID\0" \ | 423 | "b\26RDPID\0" \ | |
424 | "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ | 424 | "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ | |
425 | "b\34MOVDIR64B\0" "b\36SGXLC\0" | 425 | "b\34MOVDIR64B\0" "b\36SGXLC\0" | |
426 | 426 | |||
427 | /* %edx */ | 427 | /* %edx */ | |
428 | #define CPUID_SEF_AVX512_4VNNIW __BIT(2) | 428 | #define CPUID_SEF_AVX512_4VNNIW __BIT(2) | |
429 | #define CPUID_SEF_AVX512_4FMAPS __BIT(3) | 429 | #define CPUID_SEF_AVX512_4FMAPS __BIT(3) | |
430 | #define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ | 430 | #define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ | |
431 | #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) | |||
431 | #define CPUID_SEF_MD_CLEAR __BIT(10) | 432 | #define CPUID_SEF_MD_CLEAR __BIT(10) | |
432 | #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ | 433 | #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ | |
434 | #define CPUID_SEF_SERIALIZE __BIT(14) | |||
433 | #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ | 435 | #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ | |
436 | #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ | |||
434 | #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ | 437 | #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ | |
435 | #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ | 438 | #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ | |
436 | #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ | 439 | #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ | |
437 | #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ | 440 | #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ | |
438 | #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ | 441 | #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ | |
439 | #define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ | 442 | #define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ | |
440 | #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ | 443 | #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ | |
441 | 444 | |||
442 | #define CPUID_SEF_FLAGS2 "\20" \ | 445 | #define CPUID_SEF_FLAGS2 "\20" \ | |
443 | "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ | 446 | "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ | |
444 | "\5" "FSREP_MOV" \ | 447 | "\5" "FSREP_MOV" \ | |
445 | "\13" "MD_CLEAR" \ | 448 | "\11" "VP2INTERSECT" "\13" "MD_CLEAR" \ | |
446 | "\16" "TSX_FORCE_ABORT" "\20" "HYBRID" \ | 449 | "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ | |
450 | "\21" "TSXLDTRK" \ | |||
447 | "\25" "CET_IBT" \ | 451 | "\25" "CET_IBT" \ | |
448 | "\33" "IBRS" "\34" "STIBP" \ | 452 | "\33" "IBRS" "\34" "STIBP" \ | |
449 | "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" | 453 | "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" | |
450 | 454 | |||
451 | /* | 455 | /* | |
452 | * Intel CPUID Architectural Performance Monitoring Fn0000000a | 456 | * Intel CPUID Architectural Performance Monitoring Fn0000000a | |
453 | * | 457 | * | |
454 | * See also src/usr.sbin/tprof/arch/tprof_x86.c | 458 | * See also src/usr.sbin/tprof/arch/tprof_x86.c | |
455 | */ | 459 | */ | |
456 | 460 | |||
457 | /* %eax */ | 461 | /* %eax */ | |
458 | #define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ | 462 | #define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ | |
459 | #define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ | 463 | #define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ | |
@@ -636,49 +640,51 @@ | @@ -636,49 +640,51 @@ | |||
636 | 640 | |||
637 | #define CPUID_AMD_FLAGS4 "\20" \ | 641 | #define CPUID_AMD_FLAGS4 "\20" \ | |
638 | "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ | 642 | "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ | |
639 | "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ | 643 | "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ | |
640 | "\11" "3DNOWPREFETCH" \ | 644 | "\11" "3DNOWPREFETCH" \ | |
641 | "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ | 645 | "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ | |
642 | "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ | 646 | "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ | |
643 | "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ | 647 | "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ | |
644 | "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ | 648 | "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ | |
645 | "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ | 649 | "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ | |
646 | "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31" | 650 | "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31" | |
647 | 651 | |||
648 | /* | 652 | /* | |
649 | * AMD Advanced Power Management | 653 | * Advanced Power Management | |
650 | * CPUID Fn8000_0007 %edx | 654 | * CPUID Fn8000_0007 %edx | |
655 | * | |||
656 | * Only ITSC is for both Intel and AMD. Others are only for AMD. | |||
651 | */ | 657 | */ | |
652 | #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ | 658 | #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ | |
653 | #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ | 659 | #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ | |
654 | #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ | 660 | #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ | |
655 | #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ | 661 | #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ | |
656 | #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ | 662 | #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ | |
657 | #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ | 663 | #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ | |
658 | #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ | 664 | #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ | |
659 | #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ | 665 | #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ | |
660 | #define CPUID_APM_TSC 0x00000100 /* TSC invariant */ | 666 | #define CPUID_APM_ITSC 0x00000100 /* invariant TSC */ | |
661 | #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ | 667 | #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ | |
662 | #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ | 668 | #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ | |
663 | #define CPUID_APM_PROCFI 0x00000800 /* Proc Feedback Interface */ | 669 | #define CPUID_APM_PROCFI 0x00000800 /* Proc Feedback Interface */ | |
664 | #define CPUID_APM_PROCPR 0x00001000 /* Proc Power Reporting */ | 670 | #define CPUID_APM_PROCPR 0x00001000 /* Proc Power Reporting */ | |
665 | #define CPUID_APM_CONNSTBY 0x00002000 /* Connected Standby */ | 671 | #define CPUID_APM_CONNSTBY 0x00002000 /* Connected Standby */ | |
666 | #define CPUID_APM_RAPL 0x00004000 /* Running Average Power Limit */ | 672 | #define CPUID_APM_RAPL 0x00004000 /* Running Average Power Limit */ | |
667 | 673 | |||
668 | #define CPUID_APM_FLAGS "\20" \ | 674 | #define CPUID_APM_FLAGS "\20" \ | |
669 | "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ | 675 | "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ | |
670 | "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ | 676 | "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ | |
671 | "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ | 677 | "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ | |
672 | "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" | 678 | "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" | |
673 | 679 | |||
674 | /* | 680 | /* | |
675 | * AMD Processor Capacity Parameters and Extended Features | 681 | * AMD Processor Capacity Parameters and Extended Features | |
676 | * CPUID Fn8000_0008 | 682 | * CPUID Fn8000_0008 | |
677 | * %eax: Long Mode Size Identifiers | 683 | * %eax: Long Mode Size Identifiers | |
678 | * %ebx: Extended Feature Identifiers | 684 | * %ebx: Extended Feature Identifiers | |
679 | * %ecx: Size Identifiers | 685 | * %ecx: Size Identifiers | |
680 | */ | 686 | */ | |
681 | 687 | |||
682 | /* %ebx */ | 688 | /* %ebx */ | |
683 | #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ | 689 | #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ | |
684 | #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ | 690 | #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ |
--- src/sys/arch/x86/x86/procfs_machdep.c 2019/05/29 15:43:26 1.15.2.9
+++ src/sys/arch/x86/x86/procfs_machdep.c 2020/04/15 14:25:09 1.15.2.10
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: procfs_machdep.c,v 1.15.2.9 2019/05/29 15:43:26 martin Exp $ */ | 1 | /* $NetBSD: procfs_machdep.c,v 1.15.2.10 2020/04/15 14:25:09 martin Exp $ */ | |
2 | 2 | |||
3 | /* | 3 | /* | |
4 | * Copyright (c) 2001 Wasabi Systems, Inc. | 4 | * Copyright (c) 2001 Wasabi Systems, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * Written by Frank van der Linden and Jason R. Thorpe for | 7 | * Written by Frank van der Linden and Jason R. Thorpe for | |
8 | * Wasabi Systems, Inc. | 8 | * Wasabi Systems, Inc. | |
9 | * | 9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | 10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | 11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | 12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | 13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer. | 14 | * notice, this list of conditions and the following disclaimer. | |
@@ -32,27 +32,27 @@ | @@ -32,27 +32,27 @@ | |||
32 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 32 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
33 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 33 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
34 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 34 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
35 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 35 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
36 | * POSSIBILITY OF SUCH DAMAGE. | 36 | * POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | 37 | */ | |
38 | 38 | |||
39 | /* | 39 | /* | |
40 | * NOTE: We simply use the primary CPU's cpuid_level and tsc_freq | 40 | * NOTE: We simply use the primary CPU's cpuid_level and tsc_freq | |
41 | * here. Might want to change this later. | 41 | * here. Might want to change this later. | |
42 | */ | 42 | */ | |
43 | 43 | |||
44 | #include <sys/cdefs.h> | 44 | #include <sys/cdefs.h> | |
45 | __KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.15.2.9 2019/05/29 15:43:26 martin Exp $"); | 45 | __KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.15.2.10 2020/04/15 14:25:09 martin Exp $"); | |
46 | 46 | |||
47 | #include <sys/param.h> | 47 | #include <sys/param.h> | |
48 | #include <sys/systm.h> | 48 | #include <sys/systm.h> | |
49 | #include <sys/mount.h> | 49 | #include <sys/mount.h> | |
50 | #include <sys/stat.h> | 50 | #include <sys/stat.h> | |
51 | #include <sys/vnode.h> | 51 | #include <sys/vnode.h> | |
52 | 52 | |||
53 | #include <miscfs/procfs/procfs.h> | 53 | #include <miscfs/procfs/procfs.h> | |
54 | 54 | |||
55 | #include <machine/cpu.h> | 55 | #include <machine/cpu.h> | |
56 | #include <machine/reg.h> | 56 | #include <machine/reg.h> | |
57 | #include <machine/specialreg.h> | 57 | #include <machine/specialreg.h> | |
58 | #include <x86/cputypes.h> | 58 | #include <x86/cputypes.h> | |
@@ -119,86 +119,87 @@ static const char * const x86_features[] | @@ -119,86 +119,87 @@ static const char * const x86_features[] | |||
119 | 119 | |||
120 | { /* (8) Linux mapping */ | 120 | { /* (8) Linux mapping */ | |
121 | "tpr_shadow", "vnmi", "flexpriority", "ept", | 121 | "tpr_shadow", "vnmi", "flexpriority", "ept", | |
122 | "vpid", "npt", "lbrv", "svm_lock", | 122 | "vpid", "npt", "lbrv", "svm_lock", | |
123 | "nrip_save", "tsc_scale", "vmcb_clean", "flushbyasid", | 123 | "nrip_save", "tsc_scale", "vmcb_clean", "flushbyasid", | |
124 | "decodeassists", "pausefilter", "pfthreshold", "vmmcall", | 124 | "decodeassists", "pausefilter", "pfthreshold", "vmmcall", | |
125 | NULL, "ept_ad", NULL, NULL, NULL, NULL, NULL, NULL, | 125 | NULL, "ept_ad", NULL, NULL, NULL, NULL, NULL, NULL, | |
126 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | 126 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | |
127 | 127 | |||
128 | { /* (9) Intel-defined: 00000007 ebx */ | 128 | { /* (9) Intel-defined: 00000007 ebx */ | |
129 | "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep", | 129 | "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep", | |
130 | "bmi2", "erms", "invpcid", "rtm", "cqm", NULL, "mpx", "rdt_a", | 130 | "bmi2", "erms", "invpcid", "rtm", "cqm", NULL, "mpx", "rdt_a", | |
131 | "avx512f", "avx512dq", "rdseed", "adx", | 131 | "avx512f", "avx512dq", "rdseed", "adx", | |
132 | "smap", NULL, NULL, "clflushopt", | 132 | "smap", "avx512ifma", NULL, "clflushopt", | |
133 | "clwb", "intel_pt", "avx512pf", "avx512er", | 133 | "clwb", "intel_pt", "avx512pf", "avx512er", | |
134 | "avx512cd", "sha_ni", "avx512bw", "avx512vl"}, | 134 | "avx512cd", "sha_ni", "avx512bw", "avx512vl"}, | |
135 | 135 | |||
136 | { /* (10) 0x0000000d:1 eax */ | 136 | { /* (10) 0x0000000d:1 eax */ | |
137 | "xsaveopt", "xsavec", "xgetbv1", "xsaves", NULL, NULL, NULL, NULL, | 137 | "xsaveopt", "xsavec", "xgetbv1", "xsaves", NULL, NULL, NULL, NULL, | |
138 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 138 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
139 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 139 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
140 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | 140 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | |
141 | 141 | |||
142 | { /* (11) 0x0000000f:0 edx */ | 142 | { /* (11) 0x0000000f:0 edx */ | |
143 | NULL, "cqm_llc", NULL, NULL, NULL, NULL, NULL, NULL, | 143 | NULL, "cqm_llc", NULL, NULL, NULL, NULL, NULL, NULL, | |
144 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 144 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
145 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 145 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
146 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | 146 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | |
147 | 147 | |||
148 | { /* (12) 0x0000000f:1 edx */ | 148 | { /* (12) 0x0000000f:1 edx */ | |
149 | "cqm_occup_llc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 149 | "cqm_occup_llc", "cqm_mbm_total", "cqm_mbm_local", NULL, | |
150 | NULL, NULL, NULL, NULL, | |||
150 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 151 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
151 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 152 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
152 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | 153 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | |
153 | 154 | |||
154 | { /* (13) AMD 0x80000008 ebx */ | 155 | { /* (13) AMD 0x80000008 ebx */ | |
155 | "clzero", "irperf", "xsaveerptr", NULL, NULL, NULL, NULL, NULL, | 156 | "clzero", "irperf", "xsaveerptr", NULL, "rdpru", NULL, NULL, NULL, | |
156 | NULL, "wbnoinvd", NULL, NULL, NULL, NULL, NULL, NULL, | 157 | NULL, "wbnoinvd", NULL, NULL, NULL, NULL, NULL, NULL, | |
157 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 158 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
158 | NULL, "virt_ssbd", NULL, NULL, NULL, NULL, NULL, NULL}, | 159 | NULL, "virt_ssbd", NULL, NULL, NULL, NULL, NULL, NULL}, | |
159 | 160 | |||
160 | { /* (14) 0x00000006 eax */ | 161 | { /* (14) 0x00000006 eax */ | |
161 | "dtherm", "ida", "arat", NULL, "pln", NULL, "pts", "hwp", | 162 | "dtherm", "ida", "arat", NULL, "pln", NULL, "pts", "hwp", | |
162 | "hwp_notify", "hwp_act_window", "hwp_epp","hwp_pkg_req", | 163 | "hwp_notify", "hwp_act_window", "hwp_epp","hwp_pkg_req", | |
163 | NULL, NULL, NULL, NULL, | 164 | NULL, NULL, NULL, NULL, | |
164 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 165 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
165 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | 166 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | |
166 | 167 | |||
167 | { /* (15) 0x8000000a edx */ | 168 | { /* (15) 0x8000000a edx */ | |
168 | "npt", "lbrv", "svm_lock", "nrip_save", | 169 | "npt", "lbrv", "svm_lock", "nrip_save", | |
169 | "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists", | 170 | "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists", | |
170 | NULL, NULL, "pausefilter", NULL, "pfthreshold", "avic", NULL, | 171 | NULL, NULL, "pausefilter", NULL, "pfthreshold", "avic", NULL, | |
171 | "v_vmsave_vmload", | 172 | "v_vmsave_vmload", | |
172 | "vgif", NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 173 | "vgif", NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
173 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | 174 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | |
174 | 175 | |||
175 | { /* (16) 0x00000007:0 ecx */ | 176 | { /* (16) 0x00000007:0 ecx */ | |
176 | NULL, "avx512vbmi", "umip", "pku", | 177 | NULL, "avx512vbmi", "umip", "pku", | |
177 | "ospke", NULL, "avx512_vbmi2", NULL, | 178 | "ospke", "waitpkg", "avx512_vbmi2", NULL, | |
178 | "gfni", "vaes", "vpclmulqdq", "avx512_vnni", | 179 | "gfni", "vaes", "vpclmulqdq", "avx512_vnni", | |
179 | "avx512_bitalg", "tme", "avx512_vpopcntdq", NULL, | 180 | "avx512_bitalg", "tme", "avx512_vpopcntdq", NULL, | |
180 | "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, | 181 | "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, | |
181 | NULL, "cldemote", NULL, "movdiri", "movdir64b", NULL, NULL, NULL}, | 182 | NULL, "cldemote", NULL, "movdiri", "movdir64b", NULL, NULL, NULL}, | |
182 | 183 | |||
183 | { /* (17) 0x80000007 ebx */ | 184 | { /* (17) 0x80000007 ebx */ | |
184 | "overflow_recov", "succor", NULL, "smca", NULL, NULL, NULL, NULL, | 185 | "overflow_recov", "succor", NULL, "smca", NULL, NULL, NULL, NULL, | |
185 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 186 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
186 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | 187 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
187 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | 188 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, | |
188 | 189 | |||
189 | { /* (18) Intel 0x00000007 edx */ | 190 | { /* (18) Intel 0x00000007 edx */ | |
190 | NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", NULL, NULL, NULL, NULL, | 191 | NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", "fsrm", NULL, NULL, NULL, | |
191 | NULL, NULL, "md_clear", NULL, NULL, NULL, NULL, NULL, | 192 | "vp2intersect", NULL, "md_clear", NULL, NULL, NULL, NULL, NULL, | |
192 | NULL, NULL, "pconfig", NULL, NULL, NULL, NULL, NULL, | 193 | NULL, NULL, "pconfig", NULL, NULL, NULL, NULL, NULL, | |
193 | NULL, NULL, NULL, NULL, | 194 | NULL, NULL, NULL, NULL, | |
194 | "flush_l1d", "arch_capabilities", NULL, "ssbd"}, | 195 | "flush_l1d", "arch_capabilities", NULL, "ssbd"}, | |
195 | }; | 196 | }; | |
196 | 197 | |||
197 | static int procfs_getonecpu(int, struct cpu_info *, char *, size_t *); | 198 | static int procfs_getonecpu(int, struct cpu_info *, char *, size_t *); | |
198 | 199 | |||
199 | /* | 200 | /* | |
200 | * Linux-style /proc/cpuinfo. | 201 | * Linux-style /proc/cpuinfo. | |
201 | * Only used when procfs is mounted with -o linux. | 202 | * Only used when procfs is mounted with -o linux. | |
202 | * | 203 | * | |
203 | * In the multiprocessor case, this should be a loop over all CPUs. | 204 | * In the multiprocessor case, this should be a loop over all CPUs. | |
204 | */ | 205 | */ | |
@@ -225,27 +226,27 @@ procfs_getcpuinfstr(char *bf, size_t *le | @@ -225,27 +226,27 @@ procfs_getcpuinfstr(char *bf, size_t *le | |||
225 | } | 226 | } | |
226 | size = *len; | 227 | size = *len; | |
227 | *len = total; | 228 | *len = total; | |
228 | return size < *len ? -1 : 0; | 229 | return size < *len ? -1 : 0; | |
229 | } | 230 | } | |
230 | 231 | |||
231 | static int | 232 | static int | |
232 | procfs_getonefeatreg(uint32_t reg, const char * const *table, char *p, | 233 | procfs_getonefeatreg(uint32_t reg, const char * const *table, char *p, | |
233 | size_t *left) | 234 | size_t *left) | |
234 | { | 235 | { | |
235 | size_t l; | 236 | size_t l; | |
236 | 237 | |||
237 | for (size_t i = 0; i < 32; i++) { | 238 | for (size_t i = 0; i < 32; i++) { | |
238 | if ((reg & (1 << i)) && table[i]) { | 239 | if ((reg & (1U << i)) && table[i]) { | |
239 | l = snprintf(p, *left, "%s ", table[i]); | 240 | l = snprintf(p, *left, "%s ", table[i]); | |
240 | if (l < *left) { | 241 | if (l < *left) { | |
241 | *left -= l; | 242 | *left -= l; | |
242 | p += l; | 243 | p += l; | |
243 | } else | 244 | } else | |
244 | break; | 245 | break; | |
245 | } | 246 | } | |
246 | } | 247 | } | |
247 | 248 | |||
248 | return 0; /* XXX */ | 249 | return 0; /* XXX */ | |
249 | } | 250 | } | |
250 | 251 | |||
251 | /* | 252 | /* |
--- src/sys/arch/x86/x86/tsc.c 2013/12/18 03:20:19 1.36
+++ src/sys/arch/x86/x86/tsc.c 2020/04/15 14:25:09 1.36.22.1
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: tsc.c,v 1.36 2013/12/18 03:20:19 msaitoh Exp $ */ | 1 | /* $NetBSD: tsc.c,v 1.36.22.1 2020/04/15 14:25:09 martin Exp $ */ | |
2 | 2 | |||
3 | /*- | 3 | /*- | |
4 | * Copyright (c) 2008 The NetBSD Foundation, Inc. | 4 | * Copyright (c) 2008 The NetBSD Foundation, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | 7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | 8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | 9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | 10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | 11 | * notice, this list of conditions and the following disclaimer. | |
12 | * 2. Redistributions in binary form must reproduce the above copyright | 12 | * 2. Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | 13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | 14 | * documentation and/or other materials provided with the distribution. | |
@@ -17,27 +17,27 @@ | @@ -17,27 +17,27 @@ | |||
17 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | 17 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
18 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | 18 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | 19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | |
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
26 | * POSSIBILITY OF SUCH DAMAGE. | 26 | * POSSIBILITY OF SUCH DAMAGE. | |
27 | */ | 27 | */ | |
28 | 28 | |||
29 | #include <sys/cdefs.h> | 29 | #include <sys/cdefs.h> | |
30 | __KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.36 2013/12/18 03:20:19 msaitoh Exp $"); | 30 | __KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.36.22.1 2020/04/15 14:25:09 martin Exp $"); | |
31 | 31 | |||
32 | #include <sys/param.h> | 32 | #include <sys/param.h> | |
33 | #include <sys/systm.h> | 33 | #include <sys/systm.h> | |
34 | #include <sys/time.h> | 34 | #include <sys/time.h> | |
35 | #include <sys/timetc.h> | 35 | #include <sys/timetc.h> | |
36 | #include <sys/lwp.h> | 36 | #include <sys/lwp.h> | |
37 | #include <sys/atomic.h> | 37 | #include <sys/atomic.h> | |
38 | #include <sys/kernel.h> | 38 | #include <sys/kernel.h> | |
39 | #include <sys/cpu.h> | 39 | #include <sys/cpu.h> | |
40 | 40 | |||
41 | #include <machine/cpu_counter.h> | 41 | #include <machine/cpu_counter.h> | |
42 | #include <machine/cpuvar.h> | 42 | #include <machine/cpuvar.h> | |
43 | #include <machine/cpufunc.h> | 43 | #include <machine/cpufunc.h> | |
@@ -122,27 +122,27 @@ tsc_is_invariant(void) | @@ -122,27 +122,27 @@ tsc_is_invariant(void) | |||
122 | */ | 122 | */ | |
123 | } | 123 | } | |
124 | 124 | |||
125 | /* | 125 | /* | |
126 | * The best way to check whether the TSC counter is invariant or not | 126 | * The best way to check whether the TSC counter is invariant or not | |
127 | * is to check CPUID 80000007. | 127 | * is to check CPUID 80000007. | |
128 | */ | 128 | */ | |
129 | family = CPUID_TO_BASEFAMILY(ci->ci_signature); | 129 | family = CPUID_TO_BASEFAMILY(ci->ci_signature); | |
130 | if (((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) | 130 | if (((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) | |
131 | && ((family == 0x06) || (family == 0x0f))) { | 131 | && ((family == 0x06) || (family == 0x0f))) { | |
132 | x86_cpuid(0x80000000, descs); | 132 | x86_cpuid(0x80000000, descs); | |
133 | if (descs[0] >= 0x80000007) { | 133 | if (descs[0] >= 0x80000007) { | |
134 | x86_cpuid(0x80000007, descs); | 134 | x86_cpuid(0x80000007, descs); | |
135 | invariant = (descs[3] & CPUID_APM_TSC) != 0; | 135 | invariant = (descs[3] & CPUID_APM_ITSC) != 0; | |
136 | } | 136 | } | |
137 | } | 137 | } | |
138 | 138 | |||
139 | return invariant; | 139 | return invariant; | |
140 | } | 140 | } | |
141 | 141 | |||
142 | void | 142 | void | |
143 | tsc_tc_init(void) | 143 | tsc_tc_init(void) | |
144 | { | 144 | { | |
145 | struct cpu_info *ci; | 145 | struct cpu_info *ci; | |
146 | bool invariant; | 146 | bool invariant; | |
147 | 147 | |||
148 | if (!cpu_hascounter()) | 148 | if (!cpu_hascounter()) |
--- src/usr.sbin/cpuctl/arch/i386.c 2020/01/31 10:53:29 1.74.6.9
+++ src/usr.sbin/cpuctl/arch/i386.c 2020/04/15 14:25:09 1.74.6.10
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: i386.c,v 1.74.6.9 2020/01/31 10:53:29 martin Exp $ */ | 1 | /* $NetBSD: i386.c,v 1.74.6.10 2020/04/15 14:25:09 martin Exp $ */ | |
2 | 2 | |||
3 | /*- | 3 | /*- | |
4 | * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. | 4 | * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * This code is derived from software contributed to The NetBSD Foundation | 7 | * This code is derived from software contributed to The NetBSD Foundation | |
8 | * by Frank van der Linden, and by Jason R. Thorpe. | 8 | * by Frank van der Linden, and by Jason R. Thorpe. | |
9 | * | 9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | 10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | 11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | 12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | 13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer. | 14 | * notice, this list of conditions and the following disclaimer. | |
@@ -47,27 +47,27 @@ | @@ -47,27 +47,27 @@ | |||
47 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 47 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
48 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | 48 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | |
49 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | 49 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
50 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | 50 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
51 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | 51 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
52 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | 52 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
53 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | 53 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
54 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | 54 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
55 | * SUCH DAMAGE. | 55 | * SUCH DAMAGE. | |
56 | */ | 56 | */ | |
57 | 57 | |||
58 | #include <sys/cdefs.h> | 58 | #include <sys/cdefs.h> | |
59 | #ifndef lint | 59 | #ifndef lint | |
60 | __RCSID("$NetBSD: i386.c,v 1.74.6.9 2020/01/31 10:53:29 martin Exp $"); | 60 | __RCSID("$NetBSD: i386.c,v 1.74.6.10 2020/04/15 14:25:09 martin Exp $"); | |
61 | #endif /* not lint */ | 61 | #endif /* not lint */ | |
62 | 62 | |||
63 | #include <sys/types.h> | 63 | #include <sys/types.h> | |
64 | #include <sys/param.h> | 64 | #include <sys/param.h> | |
65 | #include <sys/bitops.h> | 65 | #include <sys/bitops.h> | |
66 | #include <sys/sysctl.h> | 66 | #include <sys/sysctl.h> | |
67 | #include <sys/ioctl.h> | 67 | #include <sys/ioctl.h> | |
68 | #include <sys/cpuio.h> | 68 | #include <sys/cpuio.h> | |
69 | 69 | |||
70 | #include <errno.h> | 70 | #include <errno.h> | |
71 | #include <string.h> | 71 | #include <string.h> | |
72 | #include <stdio.h> | 72 | #include <stdio.h> | |
73 | #include <stdlib.h> | 73 | #include <stdlib.h> | |
@@ -2202,55 +2202,48 @@ identifycpu(int fd, const char *cpuname) | @@ -2202,55 +2202,48 @@ identifycpu(int fd, const char *cpuname) | |||
2202 | || (cpu_vendor == CPUVENDOR_AMD))) { | 2202 | || (cpu_vendor == CPUVENDOR_AMD))) { | |
2203 | x86_cpuid(6, descs); | 2203 | x86_cpuid(6, descs); | |
2204 | print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); | 2204 | print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); | |
2205 | print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); | 2205 | print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); | |
2206 | } | 2206 | } | |
2207 | if ((ci->ci_cpuid_level >= 7) | 2207 | if ((ci->ci_cpuid_level >= 7) | |
2208 | && ((cpu_vendor == CPUVENDOR_INTEL) | 2208 | && ((cpu_vendor == CPUVENDOR_INTEL) | |
2209 | || (cpu_vendor == CPUVENDOR_AMD))) { | 2209 | || (cpu_vendor == CPUVENDOR_AMD))) { | |
2210 | x86_cpuid(7, descs); | 2210 | x86_cpuid(7, descs); | |
2211 | aprint_verbose("%s: SEF highest subleaf %08x\n", | 2211 | aprint_verbose("%s: SEF highest subleaf %08x\n", | |
2212 | cpuname, descs[0]); | 2212 | cpuname, descs[0]); | |
2213 | } | 2213 | } | |
2214 | 2214 | |||
2215 | if (cpu_vendor == CPUVENDOR_AMD) { | 2215 | if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) | |
2216 | uint32_t ci_max_ext_cpuid; | 2216 | if (ci->ci_cpuid_extlevel >= 0x80000007) | |
2217 | ||||
2218 | x86_cpuid(0x80000000, descs); | |||
2219 | if (descs[0] >= 0x80000000) | |||
2220 | ci_max_ext_cpuid = descs[0]; | |||
2221 | else | |||
2222 | ci_max_ext_cpuid = 0; | |||
2223 | ||||
2224 | if (ci_max_ext_cpuid >= 0x80000007) | |||
2225 | powernow_probe(ci); | 2217 | powernow_probe(ci); | |
2226 | 2218 | |||
2227 | if (ci_max_ext_cpuid >= 0x80000008) { | 2219 | if (cpu_vendor == CPUVENDOR_AMD) { | |
2220 | if (ci->ci_cpuid_extlevel >= 0x80000008) { | |||
2228 | x86_cpuid(0x80000008, descs); | 2221 | x86_cpuid(0x80000008, descs); | |
2229 | print_bits(cpuname, "AMD Extended features", | 2222 | print_bits(cpuname, "AMD Extended features", | |
2230 | CPUID_CAPEX_FLAGS, descs[1]); | 2223 | CPUID_CAPEX_FLAGS, descs[1]); | |
2231 | } | 2224 | } | |
2232 | 2225 | |||
2233 | if ((ci_max_ext_cpuid >= 0x8000000a) | 2226 | if ((ci->ci_cpuid_extlevel >= 0x8000000a) | |
2234 | && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { | 2227 | && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { | |
2235 | x86_cpuid(0x8000000a, descs); | 2228 | x86_cpuid(0x8000000a, descs); | |
2236 | aprint_verbose("%s: SVM Rev. %d\n", cpuname, | 2229 | aprint_verbose("%s: SVM Rev. %d\n", cpuname, | |
2237 | descs[0] & 0xf); | 2230 | descs[0] & 0xf); | |
2238 | aprint_verbose("%s: SVM NASID %d\n", cpuname, | 2231 | aprint_verbose("%s: SVM NASID %d\n", cpuname, | |
2239 | descs[1]); | 2232 | descs[1]); | |
2240 | print_bits(cpuname, "SVM features", | 2233 | print_bits(cpuname, "SVM features", | |
2241 | CPUID_AMD_SVM_FLAGS, descs[3]); | 2234 | CPUID_AMD_SVM_FLAGS, descs[3]); | |
2242 | } | 2235 | } | |
2243 | if (ci_max_ext_cpuid >= 0x8000001f) { | 2236 | if (ci->ci_cpuid_extlevel >= 0x8000001f) { | |
2244 | x86_cpuid(0x8000001f, descs); | 2237 | x86_cpuid(0x8000001f, descs); | |
2245 | print_bits(cpuname, "Encrypted Memory features", | 2238 | print_bits(cpuname, "Encrypted Memory features", | |
2246 | CPUID_AMD_ENCMEM_FLAGS, descs[0]); | 2239 | CPUID_AMD_ENCMEM_FLAGS, descs[0]); | |
2247 | } | 2240 | } | |
2248 | } else if (cpu_vendor == CPUVENDOR_INTEL) { | 2241 | } else if (cpu_vendor == CPUVENDOR_INTEL) { | |
2249 | int32_t bi_index; | 2242 | int32_t bi_index; | |
2250 | 2243 | |||
2251 | for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { | 2244 | for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { | |
2252 | x86_cpuid(bi_index, descs); | 2245 | x86_cpuid(bi_index, descs); | |
2253 | switch (bi_index) { | 2246 | switch (bi_index) { | |
2254 | case 0x0a: | 2247 | case 0x0a: | |
2255 | print_bits(cpuname, "Perfmon-eax", | 2248 | print_bits(cpuname, "Perfmon-eax", | |
2256 | CPUID_PERF_FLAGS0, descs[0]); | 2249 | CPUID_PERF_FLAGS0, descs[0]); | |
@@ -2490,28 +2483,27 @@ x86_print_cache_and_tlb_info(struct cpu_ | @@ -2490,28 +2483,27 @@ x86_print_cache_and_tlb_info(struct cpu_ | |||
2490 | aprint_verbose("\n"); | 2483 | aprint_verbose("\n"); | |
2491 | } | 2484 | } | |
2492 | } | 2485 | } | |
2493 | 2486 | |||
2494 | static void | 2487 | static void | |
2495 | powernow_probe(struct cpu_info *ci) | 2488 | powernow_probe(struct cpu_info *ci) | |
2496 | { | 2489 | { | |
2497 | uint32_t regs[4]; | 2490 | uint32_t regs[4]; | |
2498 | char buf[256]; | 2491 | char buf[256]; | |
2499 | 2492 | |||
2500 | x86_cpuid(0x80000007, regs); | 2493 | x86_cpuid(0x80000007, regs); | |
2501 | 2494 | |||
2502 | snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); | 2495 | snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); | |
2503 | aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", | 2496 | aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); | |
2504 | buf); | |||
2505 | } | 2497 | } | |
2506 | 2498 | |||
2507 | int | 2499 | int | |
2508 | ucodeupdate_check(int fd, struct cpu_ucode *uc) | 2500 | ucodeupdate_check(int fd, struct cpu_ucode *uc) | |
2509 | { | 2501 | { | |
2510 | struct cpu_info ci; | 2502 | struct cpu_info ci; | |
2511 | int loader_version, res; | 2503 | int loader_version, res; | |
2512 | struct cpu_ucode_version versreq; | 2504 | struct cpu_ucode_version versreq; | |
2513 | 2505 | |||
2514 | cpu_probe_base_features(&ci, "unknown"); | 2506 | cpu_probe_base_features(&ci, "unknown"); | |
2515 | 2507 | |||
2516 | if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) | 2508 | if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) | |
2517 | loader_version = CPU_UCODE_LOADER_AMD; | 2509 | loader_version = CPU_UCODE_LOADER_AMD; |