Pull up the following, requested by msaitoh in ticket #1530: sys/arch/x86/x86/procfs_machdep.c 1.33-1.36 sys/arch/x86/x86/tsc.c 1.40 sys/arch/x86/x86/specialreg.h 1.159-1.161 usr.sbin/cpuctl/arch/i386.c 1.109-1.110 via patch - Print avx512ifma, cqm_mbm_total, cqm_mbm_local, waitpkg, rdpru, Fast Short Rep Mov(fsrm), AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK. - Rename CPUID Fn8000_0007 %edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion. - Print CPUID 0x80000007 %edx on both Intel and AMD. - Remove ci_max_ext_cpuid from usr.sbin/cpuctl/arch/i386.c because it's the same as ci_cpuid_extlevel. - Use unsigned to avoid undefined behavior in procfs_getonefeatreg().diff -r1.98.2.18 -r1.98.2.19 src/sys/arch/x86/include/specialreg.h
(martin)
--- src/sys/arch/x86/include/specialreg.h 2020/01/31 10:53:29 1.98.2.18
+++ src/sys/arch/x86/include/specialreg.h 2020/04/15 14:25:09 1.98.2.19
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.98.2.18 2020/01/31 10:53:29 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.98.2.19 2020/04/15 14:25:09 martin Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -428,9 +428,12 @@
#define CPUID_SEF_AVX512_4VNNIW __BIT(2)
#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
#define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */
+#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8)
#define CPUID_SEF_MD_CLEAR __BIT(10)
#define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
+#define CPUID_SEF_SERIALIZE __BIT(14)
#define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */
+#define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */
#define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */
#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
@@ -442,8 +445,9 @@
#define CPUID_SEF_FLAGS2 "\20" \
"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
"\5" "FSREP_MOV" \
- "\13" "MD_CLEAR" \
- "\16" "TSX_FORCE_ABORT" "\20" "HYBRID" \
+ "\11" "VP2INTERSECT" "\13" "MD_CLEAR" \
+ "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \
+ "\21" "TSXLDTRK" \
"\25" "CET_IBT" \
"\33" "IBRS" "\34" "STIBP" \
"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD"
@@ -646,8 +650,10 @@
"\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31"
/*
- * AMD Advanced Power Management
+ * Advanced Power Management
* CPUID Fn8000_0007 %edx
+ *
+ * Only ITSC is for both Intel and AMD. Others are only for AMD.
*/
#define CPUID_APM_TS 0x00000001 /* Temperature Sensor */
#define CPUID_APM_FID 0x00000002 /* Frequency ID control */
@@ -657,7 +663,7 @@
#define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */
#define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */
#define CPUID_APM_HWP 0x00000080 /* HW P-State control */
-#define CPUID_APM_TSC 0x00000100 /* TSC invariant */
+#define CPUID_APM_ITSC 0x00000100 /* invariant TSC */
#define CPUID_APM_CPB 0x00000200 /* Core performance boost */
#define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */
#define CPUID_APM_PROCFI 0x00000800 /* Proc Feedback Interface */
@@ -668,7 +674,7 @@
#define CPUID_APM_FLAGS "\20" \
"\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \
"\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \
- "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \
+ "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \
"\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL"
/*
--- src/sys/arch/x86/x86/procfs_machdep.c 2019/05/29 15:43:26 1.15.2.9
+++ src/sys/arch/x86/x86/procfs_machdep.c 2020/04/15 14:25:09 1.15.2.10
@@ -1,4 +1,4 @@
-/* $NetBSD: procfs_machdep.c,v 1.15.2.9 2019/05/29 15:43:26 martin Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.15.2.10 2020/04/15 14:25:09 martin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.15.2.9 2019/05/29 15:43:26 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.15.2.10 2020/04/15 14:25:09 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -129,7 +129,7 @@
"fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
"bmi2", "erms", "invpcid", "rtm", "cqm", NULL, "mpx", "rdt_a",
"avx512f", "avx512dq", "rdseed", "adx",
- "smap", NULL, NULL, "clflushopt",
+ "smap", "avx512ifma", NULL, "clflushopt",
"clwb", "intel_pt", "avx512pf", "avx512er",
"avx512cd", "sha_ni", "avx512bw", "avx512vl"},
@@ -146,13 +146,14 @@
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (12) 0x0000000f:1 edx */
- "cqm_occup_llc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "cqm_occup_llc", "cqm_mbm_total", "cqm_mbm_local", NULL,
+ NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (13) AMD 0x80000008 ebx */
- "clzero", "irperf", "xsaveerptr", NULL, NULL, NULL, NULL, NULL,
+ "clzero", "irperf", "xsaveerptr", NULL, "rdpru", NULL, NULL, NULL,
NULL, "wbnoinvd", NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, "virt_ssbd", NULL, NULL, NULL, NULL, NULL, NULL},
@@ -174,7 +175,7 @@
{ /* (16) 0x00000007:0 ecx */
NULL, "avx512vbmi", "umip", "pku",
- "ospke", NULL, "avx512_vbmi2", NULL,
+ "ospke", "waitpkg", "avx512_vbmi2", NULL,
"gfni", "vaes", "vpclmulqdq", "avx512_vnni",
"avx512_bitalg", "tme", "avx512_vpopcntdq", NULL,
"la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL,
@@ -187,8 +188,8 @@
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
{ /* (18) Intel 0x00000007 edx */
- NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", NULL, NULL, NULL, NULL,
- NULL, NULL, "md_clear", NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", "fsrm", NULL, NULL, NULL,
+ "vp2intersect", NULL, "md_clear", NULL, NULL, NULL, NULL, NULL,
NULL, NULL, "pconfig", NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
"flush_l1d", "arch_capabilities", NULL, "ssbd"},
@@ -235,7 +236,7 @@
size_t l;
for (size_t i = 0; i < 32; i++) {
- if ((reg & (1 << i)) && table[i]) {
+ if ((reg & (1U << i)) && table[i]) {
l = snprintf(p, *left, "%s ", table[i]);
if (l < *left) {
*left -= l;
--- src/sys/arch/x86/x86/tsc.c 2013/12/18 03:20:19 1.36
+++ src/sys/arch/x86/x86/tsc.c 2020/04/15 14:25:09 1.36.22.1
@@ -1,4 +1,4 @@
-/* $NetBSD: tsc.c,v 1.36 2013/12/18 03:20:19 msaitoh Exp $ */
+/* $NetBSD: tsc.c,v 1.36.22.1 2020/04/15 14:25:09 martin Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.36 2013/12/18 03:20:19 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.36.22.1 2020/04/15 14:25:09 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -132,7 +132,7 @@
x86_cpuid(0x80000000, descs);
if (descs[0] >= 0x80000007) {
x86_cpuid(0x80000007, descs);
- invariant = (descs[3] & CPUID_APM_TSC) != 0;
+ invariant = (descs[3] & CPUID_APM_ITSC) != 0;
}
}
--- src/usr.sbin/cpuctl/arch/i386.c 2020/01/31 10:53:29 1.74.6.9
+++ src/usr.sbin/cpuctl/arch/i386.c 2020/04/15 14:25:09 1.74.6.10
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.74.6.9 2020/01/31 10:53:29 martin Exp $ */
+/* $NetBSD: i386.c,v 1.74.6.10 2020/04/15 14:25:09 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74.6.9 2020/01/31 10:53:29 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.10 2020/04/15 14:25:09 martin Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -2212,25 +2212,18 @@
cpuname, descs[0]);
}
- if (cpu_vendor == CPUVENDOR_AMD) {
- uint32_t ci_max_ext_cpuid;
-
- x86_cpuid(0x80000000, descs);
- if (descs[0] >= 0x80000000)
- ci_max_ext_cpuid = descs[0];
- else
- ci_max_ext_cpuid = 0;
-
- if (ci_max_ext_cpuid >= 0x80000007)
+ if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
+ if (ci->ci_cpuid_extlevel >= 0x80000007)
powernow_probe(ci);
- if (ci_max_ext_cpuid >= 0x80000008) {
+ if (cpu_vendor == CPUVENDOR_AMD) {
+ if (ci->ci_cpuid_extlevel >= 0x80000008) {
x86_cpuid(0x80000008, descs);
print_bits(cpuname, "AMD Extended features",
CPUID_CAPEX_FLAGS, descs[1]);
}
- if ((ci_max_ext_cpuid >= 0x8000000a)
+ if ((ci->ci_cpuid_extlevel >= 0x8000000a)
&& (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
x86_cpuid(0x8000000a, descs);
aprint_verbose("%s: SVM Rev. %d\n", cpuname,
@@ -2240,7 +2233,7 @@
print_bits(cpuname, "SVM features",
CPUID_AMD_SVM_FLAGS, descs[3]);
}
- if (ci_max_ext_cpuid >= 0x8000001f) {
+ if (ci->ci_cpuid_extlevel >= 0x8000001f) {
x86_cpuid(0x8000001f, descs);
print_bits(cpuname, "Encrypted Memory features",
CPUID_AMD_ENCMEM_FLAGS, descs[0]);
@@ -2500,8 +2493,7 @@
x86_cpuid(0x80000007, regs);
snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]);
- aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n",
- buf);
+ aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf);
}
int