 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_ixl.c,v 1.67 2020/06/11 02:39:30 thorpej Exp $	*/
+/*	$NetBSD: if_ixl.c,v 1.68 2020/07/16 01:20:38 yamaguchi Exp $	*/
 /*
  * Copyright (c) 2013-2015, Intel Corporation
  * All rights reserved.
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
+ *
  *  1. Redistributions of source code must retain the above copyright notice,
  *     this list of conditions and the following disclaimer.
+ *
  *  2. Redistributions in binary form must reproduce the above copyright
  *     notice, this list of conditions and the following disclaimer in the
 @@ -64,27 +64,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ixl.c,v 1.67 2020/06/11 02:39:30 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ixl.c,v 1.68 2020/07/16 01:20:38 yamaguchi Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #include "opt_if_ixl.h"
 #endif
 #include <sys/param.h>
 #include <sys/types.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/evcnt.h>
 #include <sys/interrupt.h>
 @@ -754,27 +754,28 @@ do {							\
 #define IXL_STATS_INTERVAL_MSEC	10000
 #endif
 #ifndef IXL_QUEUE_NUM
 #define IXL_QUEUE_NUM		0
 #endif
 static bool		 ixl_param_nomsix = false;
 static int		 ixl_param_stats_interval = IXL_STATS_INTERVAL_MSEC;
 static int		 ixl_param_nqps_limit = IXL_QUEUE_NUM;
 static unsigned int	 ixl_param_tx_ndescs = 1024;
 static unsigned int	 ixl_param_rx_ndescs = 1024;
 static enum i40e_mac_type
-    ixl_mactype(pci_product_id_t);
+	    ixl_mactype(pci_product_id_t);
 static void	ixl_pci_csr_setup(pci_chipset_tag_t, pcitag_t);
 static void	ixl_clear_hw(struct ixl_softc *);
 static int	ixl_pf_reset(struct ixl_softc *);
 static int	ixl_dmamem_alloc(struct ixl_softc *, struct ixl_dmamem *,
 		    bus_size_t, bus_size_t);
 static void	ixl_dmamem_free(struct ixl_softc *, struct ixl_dmamem *);
 static int	ixl_arq_fill(struct ixl_softc *);
 static void	ixl_arq_unfill(struct ixl_softc *);
 static int	ixl_atq_poll(struct ixl_softc *, struct ixl_aq_desc *,
 		    unsigned int);
 static void	ixl_atq_set(struct ixl_atq *,
 @@ -1097,26 +1098,28 @@ ixl_attach(device_t parent, device_t sel
 	int tries, rv, link;
 	sc = device_private(self);
 	sc->sc_dev = self;
 	ifp = &sc->sc_ec.ec_if;
 	sc->sc_pa = *pa;
 	sc->sc_dmat = (pci_dma64_available(pa)) ?
 	    pa->pa_dmat64 : pa->pa_dmat;
 	sc->sc_aq_regs = &ixl_pf_aq_regs;
 	sc->sc_mac_type = ixl_mactype(PCI_PRODUCT(pa->pa_id));
 	ixl_pci_csr_setup(pa->pa_pc, pa->pa_tag);
 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IXL_PCIREG);
 	if (pci_mapreg_map(pa, IXL_PCIREG, memtype, 0,
 	    &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) {
 		aprint_error(": unable to map registers\n");
 		return;
+	}
 	mutex_init(&sc->sc_cfg_lock, MUTEX_DEFAULT, IPL_SOFTNET);
 	firstq = ixl_rd(sc, I40E_PFLAN_QALLOC);
 	firstq &= I40E_PFLAN_QALLOC_FIRSTQ_MASK;
 	firstq >>= I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
 	sc->sc_base_queue = firstq;
 @@ -1933,26 +1936,37 @@ ixl_mactype(pci_product_id_t id)
 	case PCI_PRODUCT_INTEL_X722_KX:
 	case PCI_PRODUCT_INTEL_X722_QSFP:
 	case PCI_PRODUCT_INTEL_X722_SFP:
 	case PCI_PRODUCT_INTEL_X722_1G_BASET:
 	case PCI_PRODUCT_INTEL_X722_10G_BASET:
 	case PCI_PRODUCT_INTEL_X722_I_SFP:
 		return I40E_MAC_X722;
+	}
 	return I40E_MAC_GENERIC;
+}
 static void
 ixl_pci_csr_setup(pci_chipset_tag_t pc, pcitag_t tag)
+{
 	pcireg_t csr;
 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
 	csr |= (PCI_COMMAND_MASTER_ENABLE |
 	    PCI_COMMAND_MEM_ENABLE);
 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
+}
 static inline void *
 ixl_hmc_kva(struct ixl_softc *sc, enum ixl_hmc_types type, unsigned int i)
+{
 	uint8_t *kva = IXL_DMA_KVA(&sc->sc_hmc_pd);
 	struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type];
 	if (i >= e->hmc_count)
 		return NULL;
 	kva += e->hmc_base;
 	kva += i * e->hmc_size;
 	return kva;