Wed Sep 2 01:33:27 2020 UTC ()
Octeon CN70XX CPUs have a COP0 config5 register.
XXX: The presense of these are defined by the MIPS architecture, should probe.


(simonb)
diff -r1.299 -r1.300 src/sys/arch/mips/mips/mips_machdep.c
cvs diff -r1.299 -r1.300 src/sys/arch/mips/mips/mips_machdep.c (expand / switch to unified diff)

--- src/sys/arch/mips/mips/mips_machdep.c 2020/08/17 03:22:13 1.299
+++ src/sys/arch/mips/mips/mips_machdep.c 2020/09/02 01:33:27 1.300
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: mips_machdep.c,v 1.299 2020/08/17 03:22:13 mrg Exp $ */ 1/* $NetBSD: mips_machdep.c,v 1.300 2020/09/02 01:33:27 simonb Exp $ */
2 2
3/* 3/*
4 * Copyright 2002 Wasabi Systems, Inc. 4 * Copyright 2002 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Simon Burge for Wasabi Systems, Inc. 7 * Written by Simon Burge for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -101,27 +101,27 @@ @@ -101,27 +101,27 @@
101 * Copyright 1996 The Board of Trustees of The Leland Stanford 101 * Copyright 1996 The Board of Trustees of The Leland Stanford
102 * Junior University. All Rights Reserved. 102 * Junior University. All Rights Reserved.
103 * 103 *
104 * Permission to use, copy, modify, and distribute this 104 * Permission to use, copy, modify, and distribute this
105 * software and its documentation for any purpose and without 105 * software and its documentation for any purpose and without
106 * fee is hereby granted, provided that the above copyright 106 * fee is hereby granted, provided that the above copyright
107 * notice appear in all copies. Stanford University 107 * notice appear in all copies. Stanford University
108 * makes no representations about the suitability of this 108 * makes no representations about the suitability of this
109 * software for any purpose. It is provided "as is" without 109 * software for any purpose. It is provided "as is" without
110 * express or implied warranty. 110 * express or implied warranty.
111 */ 111 */
112 112
113#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 113#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
114__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.299 2020/08/17 03:22:13 mrg Exp $"); 114__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.300 2020/09/02 01:33:27 simonb Exp $");
115 115
116#define __INTR_PRIVATE 116#define __INTR_PRIVATE
117#include "opt_cputype.h" 117#include "opt_cputype.h"
118#include "opt_compat_netbsd32.h" 118#include "opt_compat_netbsd32.h"
119#include "opt_multiprocessor.h" 119#include "opt_multiprocessor.h"
120 120
121#include <sys/param.h> 121#include <sys/param.h>
122#include <sys/systm.h> 122#include <sys/systm.h>
123#include <sys/proc.h> 123#include <sys/proc.h>
124#include <sys/intr.h> 124#include <sys/intr.h>
125#include <sys/exec.h> 125#include <sys/exec.h>
126#include <sys/reboot.h> 126#include <sys/reboot.h>
127#include <sys/mount.h> /* fsid_t for syscallargs */ 127#include <sys/mount.h> /* fsid_t for syscallargs */
@@ -662,30 +662,30 @@ static const struct pridtab cputab[] = { @@ -662,30 +662,30 @@ static const struct pridtab cputab[] = {
662 0, 662 0,
663 "CN30xx" }, 663 "CN30xx" },
664 664
665 { MIPS_PRID_CID_CAVIUM, MIPS_CN50XX, -1, -1, -1, 0, 665 { MIPS_PRID_CID_CAVIUM, MIPS_CN50XX, -1, -1, -1, 0,
666 MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR, 666 MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
667 MIPS_CP0FL_USE | 667 MIPS_CP0FL_USE |
668 MIPS_CP0FL_EBASE | MIPS_CP0FL_CONFIG | 668 MIPS_CP0FL_EBASE | MIPS_CP0FL_CONFIG |
669 MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | MIPS_CP0FL_CONFIG3, 669 MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | MIPS_CP0FL_CONFIG3,
670 0, 670 0,
671 "CN50xx" }, 671 "CN50xx" },
672 672
673 { MIPS_PRID_CID_CAVIUM, MIPS_CN70XX, -1, -1, -1, 0, 673 { MIPS_PRID_CID_CAVIUM, MIPS_CN70XX, -1, -1, -1, 0,
674 MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR, 674 MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
675 MIPS_CP0FL_USE | 675 MIPS_CP0FL_USE | MIPS_CP0FL_EBASE |
676 MIPS_CP0FL_EBASE | MIPS_CP0FL_CONFIG | 676 MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
677 MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | MIPS_CP0FL_CONFIG3 | 677 MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG4 | MIPS_CP0FL_CONFIG5 |
678 MIPS_CP0FL_CONFIG4 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7, 678 MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
679 0, 679 0,
680 "CN70xx/CN71xx" }, 680 "CN70xx/CN71xx" },
681 681
682 /* Microsoft Research' extensible MIPS */ 682 /* Microsoft Research' extensible MIPS */
683 { MIPS_PRID_CID_MICROSOFT, MIPS_eMIPS, 1, -1, CPU_ARCH_MIPS1, 64, 683 { MIPS_PRID_CID_MICROSOFT, MIPS_eMIPS, 1, -1, CPU_ARCH_MIPS1, 64,
684 CPU_MIPS_NO_WAIT, 0, 0, "eMIPS CPU" }, 684 CPU_MIPS_NO_WAIT, 0, 0, "eMIPS CPU" },
685 685
686 /* Ingenic XBurst */ 686 /* Ingenic XBurst */
687 { MIPS_PRID_CID_INGENIC, MIPS_XBURST, -1, -1, -1, 0, 687 { MIPS_PRID_CID_INGENIC, MIPS_XBURST, -1, -1, -1, 0,
688 MIPS32_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_DOUBLE_COUNT, 688 MIPS32_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_DOUBLE_COUNT,
689 0, 0, "XBurst" }, 689 0, 0, "XBurst" },
690 690
691 { 0, 0, 0, 0, 0, 0, 691 { 0, 0, 0, 0, 0, 0,