Wed Sep 2 01:33:27 2020 UTC ()
Octeon CN70XX CPUs have a COP0 config5 register.
XXX: The presense of these are defined by the MIPS architecture, should probe.


(simonb)
diff -r1.299 -r1.300 src/sys/arch/mips/mips/mips_machdep.c

cvs diff -r1.299 -r1.300 src/sys/arch/mips/mips/mips_machdep.c (expand / switch to context diff)
--- src/sys/arch/mips/mips/mips_machdep.c 2020/08/17 03:22:13 1.299
+++ src/sys/arch/mips/mips/mips_machdep.c 2020/09/02 01:33:27 1.300
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_machdep.c,v 1.299 2020/08/17 03:22:13 mrg Exp $	*/
+/*	$NetBSD: mips_machdep.c,v 1.300 2020/09/02 01:33:27 simonb Exp $	*/
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -111,7 +111,7 @@
  */
 
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.299 2020/08/17 03:22:13 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.300 2020/09/02 01:33:27 simonb Exp $");
 
 #define __INTR_PRIVATE
 #include "opt_cputype.h"
@@ -672,10 +672,10 @@
 
 	{ MIPS_PRID_CID_CAVIUM, MIPS_CN70XX, -1, -1, -1, 0,
 	  MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
-	  MIPS_CP0FL_USE |
-	  MIPS_CP0FL_EBASE | MIPS_CP0FL_CONFIG |
-	  MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | MIPS_CP0FL_CONFIG3 |
-	  MIPS_CP0FL_CONFIG4 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
+	  MIPS_CP0FL_USE | MIPS_CP0FL_EBASE |
+	  MIPS_CP0FL_CONFIG  | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
+	  MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG4 | MIPS_CP0FL_CONFIG5 |
+	  MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
 	  0,
 	  "CN70xx/CN71xx"	},