Tue Mar 30 02:27:00 2021 UTC ()
According to "PPC405GP Embedded Processor User窶冱 Manual",
405GP has 16KB instruction cache, not 8KB.


(rin)
diff -r1.36 -r1.37 src/sys/arch/powerpc/ibm4xx/cpu.c
cvs diff -r1.36 -r1.37 src/sys/arch/powerpc/ibm4xx/cpu.c (expand / switch to unified diff)

--- src/sys/arch/powerpc/ibm4xx/cpu.c 2021/03/05 07:11:24 1.36
+++ src/sys/arch/powerpc/ibm4xx/cpu.c 2021/03/30 02:27:00 1.37
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpu.c,v 1.36 2021/03/05 07:11:24 rin Exp $ */ 1/* $NetBSD: cpu.c,v 1.37 2021/03/30 02:27:00 rin Exp $ */
2 2
3/* 3/*
4 * Copyright 2001 Wasabi Systems, Inc. 4 * Copyright 2001 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -26,27 +26,27 @@ @@ -26,27 +26,27 @@
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE. 35 * POSSIBILITY OF SUCH DAMAGE.
36 */ 36 */
37 37
38#include <sys/cdefs.h> 38#include <sys/cdefs.h>
39__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.36 2021/03/05 07:11:24 rin Exp $"); 39__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.37 2021/03/30 02:27:00 rin Exp $");
40 40
41#include <sys/param.h> 41#include <sys/param.h>
42#include <sys/systm.h> 42#include <sys/systm.h>
43#include <sys/device.h> 43#include <sys/device.h>
44#include <sys/evcnt.h> 44#include <sys/evcnt.h>
45#include <sys/cpu.h> 45#include <sys/cpu.h>
46 46
47#include <uvm/uvm_extern.h> 47#include <uvm/uvm_extern.h>
48 48
49#include <prop/proplib.h> 49#include <prop/proplib.h>
50 50
51#include <powerpc/ibm4xx/cpu.h> 51#include <powerpc/ibm4xx/cpu.h>
52#include <powerpc/ibm4xx/dev/plbvar.h> 52#include <powerpc/ibm4xx/dev/plbvar.h>
@@ -166,27 +166,27 @@ static const struct cputab models[] = { @@ -166,27 +166,27 @@ static const struct cputab models[] = {
166 .ci = { 166 .ci = {
167 .dcache_size = 8192, 167 .dcache_size = 8192,
168 .dcache_line_size = 16, 168 .dcache_line_size = 16,
169 .icache_size = 16384, 169 .icache_size = 16384,
170 .icache_line_size = 16, 170 .icache_line_size = 16,
171 } 171 }
172 }, { 172 }, {
173 .version = PVR_405GP,  173 .version = PVR_405GP,
174 .mask = 0xffff0000, 174 .mask = 0xffff0000,
175 .name = "405GP", 175 .name = "405GP",
176 .ci = { 176 .ci = {
177 .dcache_size = 8192, 177 .dcache_size = 8192,
178 .dcache_line_size = 32, 178 .dcache_line_size = 32,
179 .icache_size = 8192, 179 .icache_size = 16384,
180 .icache_line_size = 32, 180 .icache_line_size = 32,
181 } 181 }
182 }, { 182 }, {
183 .version = PVR_405GPR,  183 .version = PVR_405GPR,
184 .mask = 0xffff0000, 184 .mask = 0xffff0000,
185 .name = "405GPr", 185 .name = "405GPr",
186 .ci = { 186 .ci = {
187 .dcache_size = 16384, 187 .dcache_size = 16384,
188 .dcache_line_size = 32, 188 .dcache_line_size = 32,
189 .icache_size = 16384, 189 .icache_size = 16384,
190 .icache_line_size = 32, 190 .icache_line_size = 32,
191 } 191 }
192 }, { 192 }, {