Tue Mar 30 02:27:00 2021 UTC ()
According to "PPC405GP Embedded Processor User窶冱 Manual",
405GP has 16KB instruction cache, not 8KB.


(rin)
diff -r1.36 -r1.37 src/sys/arch/powerpc/ibm4xx/cpu.c

cvs diff -r1.36 -r1.37 src/sys/arch/powerpc/ibm4xx/cpu.c (expand / switch to context diff)
--- src/sys/arch/powerpc/ibm4xx/cpu.c 2021/03/05 07:11:24 1.36
+++ src/sys/arch/powerpc/ibm4xx/cpu.c 2021/03/30 02:27:00 1.37
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.c,v 1.36 2021/03/05 07:11:24 rin Exp $	*/
+/*	$NetBSD: cpu.c,v 1.37 2021/03/30 02:27:00 rin Exp $	*/
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.36 2021/03/05 07:11:24 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.37 2021/03/30 02:27:00 rin Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -176,7 +176,7 @@
 		.ci = {
 			.dcache_size = 8192,
 			.dcache_line_size = 32,
-			.icache_size = 8192,
+			.icache_size = 16384,
 			.icache_line_size = 32,
 		}
 	}, {