 @@ -1,14 +1,14 @@
-/*	$NetBSD: xhci.c,v 1.138 2021/01/05 18:00:21 skrll Exp $	*/
+/*	$NetBSD: xhci.c,v 1.139 2021/05/23 11:49:45 riastradh Exp $	*/
 /*
  * Copyright (c) 2013 Jonathan A. Kollasch
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -24,27 +24,27 @@
  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * USB rev 2.0 and rev 3.1 specification
  *  http://www.usb.org/developers/docs/
  * xHCI rev 1.1 specification
  *  http://www.intel.com/technology/usb/spec.htm
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.138 2021/01/05 18:00:21 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.139 2021/05/23 11:49:45 riastradh Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_usb.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <sys/device.h>
 #include <sys/select.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
 @@ -378,47 +378,45 @@ xhci_op_write_8(const struct xhci_softc
 static inline uint32_t
 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
+}
 static inline void
 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset,
     uint32_t value)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
+}
 #if 0 /* unused */
 static inline uint64_t
 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	uint64_t value;
 	if (XHCI_HCC_AC64(sc->sc_hcc)) {
 #ifdef XHCI_USE_BUS_SPACE_8
 		value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset);
 #else
 		value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
 		value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh,
 		    offset + 4) << 32;
 #endif
 	} else {
 		value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
+	}
 	return value;
+}
 #endif /* unused */
 static inline void
 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset,
     uint64_t value)
+{
 	if (XHCI_HCC_AC64(sc->sc_hcc)) {
 #ifdef XHCI_USE_BUS_SPACE_8
 		bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value);
 #else
 		bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0,
 		    (value >> 0) & 0xffffffff);
 		bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4,
 		    (value >> 32) & 0xffffffff);
 @@ -688,35 +686,377 @@ xhci_activate(device_t self, enum devact
+{
 	struct xhci_softc * const sc = device_private(self);
 	switch (act) {
 	case DVACT_DEACTIVATE:
 		sc->sc_dying = true;
 		return 0;
 	default:
 		return EOPNOTSUPP;
+	}
+}
 bool
-xhci_suspend(device_t dv, const pmf_qual_t *qual)
+xhci_suspend(device_t self, const pmf_qual_t *qual)
+{
-	return false;
+	struct xhci_softc * const sc = device_private(self);
 	size_t i, j, bn;
 	int port;
 	uint32_t v;
 	XHCIHIST_FUNC(); XHCIHIST_CALLED();
 	/*
 	 * First, suspend all the ports:
+	 *
 	 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.15:
 	 * Suspend-Resume, pp. 276-283
 	 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=276
 	 */
 	for (bn = 0; bn < 2; bn++) {
 		for (i = 1; i <= sc->sc_rhportcount[bn]; i++) {
 			/* 4.15.1: Port Suspend.  */
 			port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i));
 			/*
 			 * `System software places individual ports
 			 *  into suspend mode by writing a ``3'' into
 			 *  the appropriate PORTSC register Port Link
 			 *  State (PLS) field (refer to Section 5.4.8).
 			 *  Software should only set the PLS field to
 			 *  ``3'' when the port is in the Enabled
 			 *  state.'
+			 *
 			 * `Software should not attempt to suspend a
 			 *  port unless the port reports that it is in
 			 *  the enabled (PED = ``1''; PLS < ``3'')
 			 *  state (refer to Section 5.4.8 for more
 			 *  information about PED and PLS).'
 			 */
 			v = xhci_op_read_4(sc, port);
 			if (((v & XHCI_PS_PED) == 0) ||
 			    XHCI_PS_PLS_GET(v) >= XHCI_PS_PLS_U3)
 				continue;
 			v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR);
 			v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU3);
 			xhci_op_write_4(sc, port, v);
 			/*
 			 * `When the PLS field is written with U3
 			 *  (``3''), the status of the PLS bit will not
 			 *  change to the target U state U3 until the
 			 *  suspend signaling has completed to the
 			 *  attached device (which may be as long as
 			 *  10ms.).'
+			 *
 			 * `Software is required to wait for U3
 			 *  transitions to complete before it puts the
 			 *  xHC into a low power state, and before
 			 *  resuming the port.'
+			 *
 			 * XXX Take advantage of the technique to
 			 * reduce polling on host controllers that
 			 * support the U3C capability.
 			 */
 			for (j = 0; j < XHCI_WAIT_PLS_U3; j++) {
 				v = xhci_op_read_4(sc, port);
 				if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U3)
 					break;
 				usb_delay_ms(&sc->sc_bus, 1);
+			}
 			if (j == XHCI_WAIT_PLS_U3) {
 				device_printf(self,
 				    "suspend timeout on bus %zu port %zu\n",
 				    bn, i);
 				return false;
+			}
+		}
+	}
 	/*
 	 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2:
 	 * xHCI Power Management, p. 342
 	 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=342
 	 */
 	/*
 	 * `1. Stop all USB activity by issuing Stop Endpoint Commands
 	 *     for Busy endpoints in the Running state.  If the Force
 	 *     Save Context Capability (FSC = ``0'') is not supported,
 	 *     then Stop Endpoint Commands shall be issued for all Idle
 	 *     endpoints in the Running state as well.  The Stop
 	 *     Endpoint Command causes the xHC to update the respective
 	 *     Endpoint or Stream Contexts in system memory, e.g. the
 	 *     TR Dequeue Pointer, DCS, etc. fields.  Refer to
 	 *     Implementation Note "0".'
+	 *
 	 * XXX Not entirely sure if this is necessary for us; also it
 	 * probably has to happen before suspending the ports.
 	 */
 	/*
 	 * `2. Ensure that the Command Ring is in the Stopped state
 	 *     (CRR = ``0'') or Idle (i.e. the Command Transfer Ring is
 	 *     empty), and all Command Completion Events associated
 	 *     with them have been received.'
+	 *
 	 * XXX
 	 */
 	/* `3. Stop the controller by setting Run/Stop (R/S) = ``0''.'  */
 	xhci_op_write_4(sc, XHCI_USBCMD,
 	    xhci_op_read_4(sc, XHCI_USBCMD) & ~XHCI_CMD_RS);
 	/*
 	 * `4. Read the Operational Runtime, and VTIO registers in the
 	 *     following order: USBCMD, DNCTRL, DCBAAP, CONFIG, ERSTSZ,
 	 *     ERSTBA, ERDP, IMAN, IMOD, and VTIO and save their
 	 *     state.'
+	 *
 	 * (We don't use VTIO here (XXX for now?).)
 	 */
 	sc->sc_regs.usbcmd = xhci_op_read_4(sc, XHCI_USBCMD);
 	sc->sc_regs.dnctrl = xhci_op_read_4(sc, XHCI_DNCTRL);
 	sc->sc_regs.dcbaap = xhci_op_read_8(sc, XHCI_DCBAAP);
 	sc->sc_regs.config = xhci_op_read_4(sc, XHCI_CONFIG);
 	sc->sc_regs.erstsz0 = xhci_rt_read_4(sc, XHCI_ERSTSZ(0));
 	sc->sc_regs.erstba0 = xhci_rt_read_8(sc, XHCI_ERSTBA(0));
 	sc->sc_regs.erdp0 = xhci_rt_read_8(sc, XHCI_ERDP(0));
 	sc->sc_regs.iman0 = xhci_rt_read_4(sc, XHCI_IMAN(0));
 	sc->sc_regs.imod0 = xhci_rt_read_4(sc, XHCI_IMOD(0));
 	/*
 	 * `5. Set the Controller Save State (CSS) flag in the USBCMD
 	 *     register (5.4.1)...'
 	 */
 	xhci_op_write_4(sc, XHCI_USBCMD,
 	    xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CSS);
 	/*
 	 *    `...and wait for the Save State Status (SSS) flag in the
 	 *     USBSTS register (5.4.2) to transition to ``0''.'
 	 */
 	for (i = 0; i < XHCI_WAIT_SSS; i++) {
 		if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SSS) == 0)
 			break;
 		usb_delay_ms(&sc->sc_bus, 1);
+	}
 	if (i >= XHCI_WAIT_SSS) {
 		device_printf(self, "suspend timeout, USBSTS.SSS\n");
 		/*
 		 * Just optimistically go on and check SRE anyway --
 		 * what's the worst that could happen?
 		 */
+	}
 	/*
 	 * `Note: After a Save or Restore operation completes, the
 	 *  Save/Restore Error (SRE) flag in the USBSTS register should
 	 *  be checked to ensure that the operation completed
 	 *  successfully.'
 	 */
 	if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) {
 		device_printf(self, "suspend error, USBSTS.SRE\n");
 		return false;
+	}
 	return true;
+}
 bool
-xhci_resume(device_t dv, const pmf_qual_t *qual)
+xhci_resume(device_t self, const pmf_qual_t *qual)
+{
-	return false;
+	struct xhci_softc * const sc = device_private(self);
 	size_t i, j, bn, dci;
 	int port;
 	uint32_t v;
 	XHCIHIST_FUNC(); XHCIHIST_CALLED();
 	/*
 	 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2:
 	 * xHCI Power Management, p. 343
 	 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=343
 	 */
 	/*
 	 * `4. Restore the Operational Runtime, and VTIO registers with
 	 *     their previously saved state in the following order:
 	 *     DNCTRL, DCBAAP, CONFIG, ERSTSZ, ERSTBA, ERDP, IMAN,
 	 *     IMOD, and VTIO.'
+	 *
 	 * (We don't use VTIO here (for now?).)
 	 */
 	xhci_op_write_4(sc, XHCI_USBCMD, sc->sc_regs.usbcmd);
 	xhci_op_write_4(sc, XHCI_DNCTRL, sc->sc_regs.dnctrl);
 	xhci_op_write_8(sc, XHCI_DCBAAP, sc->sc_regs.dcbaap);
 	xhci_op_write_4(sc, XHCI_CONFIG, sc->sc_regs.config);
 	xhci_rt_write_4(sc, XHCI_ERSTSZ(0), sc->sc_regs.erstsz0);
 	xhci_rt_write_8(sc, XHCI_ERSTBA(0), sc->sc_regs.erstba0);
 	xhci_rt_write_8(sc, XHCI_ERDP(0), sc->sc_regs.erdp0);
 	xhci_rt_write_4(sc, XHCI_IMAN(0), sc->sc_regs.iman0);
 	xhci_rt_write_4(sc, XHCI_IMOD(0), sc->sc_regs.imod0);
 	memset(&sc->sc_regs, 0, sizeof(sc->sc_regs)); /* paranoia */
 	/*
 	 * `5. Set the Controller Restore State (CRS) flag in the
 	 *     USBCMD register (5.4.1) to ``1''...'
 	 */
 	xhci_op_write_4(sc, XHCI_USBCMD,
 	    xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CRS);
 	/*
 	 *    `...and wait for the Restore State Status (RSS) in the
 	 *     USBSTS register (5.4.2) to transition to ``0''.'
 	 */
 	for (i = 0; i < XHCI_WAIT_RSS; i++) {
 		if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_RSS) == 0)
 			break;
 		usb_delay_ms(&sc->sc_bus, 1);
+	}
 	if (i >= XHCI_WAIT_RSS) {
 		device_printf(self, "suspend timeout, USBSTS.RSS\n");
 		return false;
+	}
 	/*
 	 * `6. Reinitialize the Command Ring, i.e. so its Cycle bits
 	 *     are consistent with the RCS values to be written to the
 	 *     CRCR.'
+	 *
 	 * XXX Hope just zeroing it is good enough!
 	 */
 	xhci_host_dequeue(sc->sc_cr);
 	/*
 	 * `7. Write the CRCR with the address and RCS value of the
 	 *     reinitialized Command Ring.  Note that this write will
 	 *     cause the Command Ring to restart at the address
 	 *     specified by the CRCR.'
 	 */
 	xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) |
 	    sc->sc_cr->xr_cs);
 	/*
 	 * `8. Enable the controller by setting Run/Stop (R/S) =
 	 *     ``1''.'
 	 */
 	xhci_op_write_4(sc, XHCI_USBCMD,
 	    xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_RS);
 	/*
 	 * `9. Software shall walk the USB topology and initialize each
 	 *     of the xHC PORTSC, PORTPMSC, and PORTLI registers, and
 	 *     external hub ports attached to USB devices.'
+	 *
 	 * This follows the procedure in 4.15 `Suspend-Resume', 4.15.2
 	 * `Port Resume', 4.15.2.1 `Host Initiated'.
+	 *
 	 * XXX We should maybe batch up initiating the state
 	 * transitions, and then wait for them to complete all at once.
 	 */
 	for (bn = 0; bn < 2; bn++) {
 		for (i = 1; i <= sc->sc_rhportcount[bn]; i++) {
 			port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i));
 			/* `When a port is in the U3 state: ...' */
 			v = xhci_op_read_4(sc, port);
 			if (XHCI_PS_PLS_GET(v) != XHCI_PS_PLS_U3)
 				continue;
 			/*
 			 * `For a USB2 protocol port, software shall
 			 *  write a ``15'' (Resume) to the PLS field to
 			 *  initiate resume signaling.  The port shall
 			 *  transition to the Resume substate and the
 			 *  xHC shall transmit the resume signaling
 			 *  within 1ms (T_URSM).  Software shall ensure
 			 *  that resume is signaled for at least 20ms
 			 *  (T_DRSMDN).  Software shall start timing
 			 *  T_DRSMDN from the write of ``15'' (Resume)
 			 *  to PLS.'
 			 */
 			if (bn == 1) {
 				KASSERT(sc->sc_bus2.ub_revision == USBREV_2_0);
 				v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR);
 				v |= XHCI_PS_LWS;
 				v |= XHCI_PS_PLS_SET(XHCI_PS_PLS_SETRESUME);
 				xhci_op_write_4(sc, port, v);
 				usb_delay_ms(&sc->sc_bus, 20);
 			} else {
 				KASSERT(sc->sc_bus.ub_revision > USBREV_2_0);
+			}
 			/*
 			 * `For a USB3 protocol port [and a USB2
 			 *  protocol port after transitioning to
 			 *  Resume], software shall write a ``0'' (U0)
 			 *  to the PLS field...'
 			 */
 			v = xhci_op_read_4(sc, port);
 			v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR);
 			v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU0);
 			xhci_op_write_4(sc, port, v);
 			for (j = 0; j < XHCI_WAIT_PLS_U0; j++) {
 				v = xhci_op_read_4(sc, port);
 				if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U0)
 					break;
 				usb_delay_ms(&sc->sc_bus, 1);
+			}
 			if (j == XHCI_WAIT_PLS_U0) {
 				device_printf(self,
 				    "resume timeout on bus %zu port %zu\n",
 				    bn, i);
 				return false;
+			}
+		}
+	}
 	/*
 	 * `10. Restart each of the previously Running endpoints by
 	 *      ringing their doorbells.'
 	 */
 	for (i = 0; i < sc->sc_maxslots; i++) {
 		struct xhci_slot *xs = &sc->sc_slots[i];
 		/* Skip if the slot is not in use.  */
 		if (xs->xs_idx == 0)
 			continue;
 		for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
 			/* Skip if the endpoint is not Running.  */
 			if (xhci_get_epstate(sc, xs, dci) !=
 			    XHCI_EPSTATE_RUNNING)
 				continue;
 			/* Ring the doorbell.  */
 			xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
+		}
+	}
 	/*
 	 * `Note: After a Save or Restore operation completes, the
 	 *  Save/Restore Error (SRE) flag in the USBSTS register should
 	 *  be checked to ensure that the operation completed
 	 *  successfully.'
 	 */
 	if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) {
 		device_printf(self, "resume error, USBSTS.SRE\n");
 		return false;
+	}
 	return true;
+}
 bool
 xhci_shutdown(device_t self, int flags)
+{
 	return false;
+}
 static int
 xhci_hc_reset(struct xhci_softc * const sc)
+{
 	uint32_t usbcmd, usbsts;
 	int i;
 @@ -762,27 +1102,26 @@ xhci_hc_reset(struct xhci_softc * const
 		if ((usbsts & XHCI_STS_CNR) == 0)
 			break;
 		usb_delay_ms(&sc->sc_bus, 1);
+	}
 	if (i >= XHCI_WAIT_CNR) {
 		aprint_error_dev(sc->sc_dev,
 		    "controller not ready timeout after reset\n");
 		return EIO;
+	}
 	return 0;
+}
 /* 7.2 xHCI Support Protocol Capability */
 static void
 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp)
+{
 	XHCIHIST_FUNC(); XHCIHIST_CALLED();
 	/* XXX Cache this lot */
 	const uint32_t w0 = xhci_read_4(sc, ecp);
 	const uint32_t w4 = xhci_read_4(sc, ecp + 4);
 	const uint32_t w8 = xhci_read_4(sc, ecp + 8);
 	const uint32_t wc = xhci_read_4(sc, ecp + 0xc);

 @@ -1,14 +1,14 @@
-/* $NetBSD: xhcireg.h,v 1.18 2020/06/06 08:56:30 skrll Exp $ */
+/* $NetBSD: xhcireg.h,v 1.19 2021/05/23 11:49:45 riastradh Exp $ */
 /*-
  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
 @@ -122,26 +122,30 @@
 #define	 XHCI_CMD_HSEE		__BIT(3)	/* RW Host System Error Enable */
 #define	 XHCI_CMD_LHCRST	__BIT(7)	/* RO/RW Light Host Controller Reset */
 #define	 XHCI_CMD_CSS		__BIT(8)	/* RW Controller Save State */
 #define	 XHCI_CMD_CRS		__BIT(9)	/* RW Controller Restore State */
 #define	 XHCI_CMD_EWE		__BIT(10)	/* RW Enable Wrap Event */
 #define	 XHCI_CMD_EU3S		__BIT(11)	/* RW Enable U3 MFINDEX Stop */
 #define	 XHCI_CMD_CME		__BIT(13)	/* RW CEM Enable */
 #define	 XHCI_CMD_ETE		__BIT(14)	/* RW Extended TBC Enable */
 #define	 XHCI_CMD_TSC_EN	__BIT(15)	/* RW Extended TBC TRB Status Enable */
 #define	 XHCI_CMD_VTIOE		__BIT(16)	/* RW VTIO Enable */
 #define	XHCI_WAIT_CNR		100		/* in 1ms */
 #define	XHCI_WAIT_HCRST		100		/* in 1ms */
 #define	XHCI_WAIT_RSS		100		/* in 1ms */
 #define	XHCI_WAIT_SSS		100		/* in 1ms */
 #define	XHCI_WAIT_PLS_U0	100		/* in 1ms */
 #define	XHCI_WAIT_PLS_U3	10		/* in 1ms */
 #define	XHCI_USBSTS		0x04	/* XHCI status */
 #define	 XHCI_STS_HCH		__BIT(0)	/* RO - Host Controller Halted */
 #define	 XHCI_STS_RSVDZ0	__BIT(1)	/* RsvdZ - 1:1 */
 #define	 XHCI_STS_HSE		__BIT(2)	/* RW - Host System Error */
 #define	 XHCI_STS_EINT		__BIT(3)	/* RW - Event Interrupt */
 #define	 XHCI_STS_PCD		__BIT(4)	/* RW - Port Change Detect */
 #define	 XHCI_STS_RSVDZ1	__BITS(7, 5)	/* RsvdZ - 7:5 */
 #define	 XHCI_STS_SSS		__BIT(8)	/* RO - Save State Status */
 #define	 XHCI_STS_RSS		__BIT(9)	/* RO - Restore State Status */
 #define	 XHCI_STS_SRE		__BIT(10)	/* RW - Save/Restore Error */
 #define	 XHCI_STS_CNR		__BIT(11)	/* RO - Controller Not Ready */
 #define	 XHCI_STS_HCE		__BIT(12)	/* RO - Host Controller Error */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: xhcivar.h,v 1.17 2020/08/21 20:46:03 jakllsch Exp $	*/
+/*	$NetBSD: xhcivar.h,v 1.18 2021/05/23 11:49:45 riastradh Exp $	*/
 /*
  * Copyright (c) 2013 Jonathan A. Kollasch
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -127,26 +127,38 @@ struct xhci_softc {
 	struct xhci_soft_trb sc_result_trb;
 	bool sc_resultpending;
 	bool sc_dying;
 	void (*sc_vendor_init)(struct xhci_softc *);
 	int (*sc_vendor_port_status)(struct xhci_softc *, uint32_t, int);
 	int sc_quirks;
 #define XHCI_QUIRK_INTEL	__BIT(0) /* Intel xhci chip */
 #define XHCI_DEFERRED_START	__BIT(1)
 	uint32_t sc_hcc;		/* copy of HCCPARAMS1 */
 	uint32_t sc_hcc2;		/* copy of HCCPARAMS2 */
 	struct xhci_registers {
 		uint32_t	usbcmd;
 		uint32_t	dnctrl;
 		uint64_t	dcbaap;
 		uint32_t	config;
 		uint32_t	erstsz0;
 		uint64_t	erstba0;
 		uint64_t	erdp0;
 		uint32_t	iman0;
 		uint32_t	imod0;
 	} sc_regs;
 };
 int	xhci_init(struct xhci_softc *);
 void	xhci_start(struct xhci_softc *);
 int	xhci_intr(void *);
 int	xhci_detach(struct xhci_softc *, int);
 int	xhci_activate(device_t, enum devact);
 void	xhci_childdet(device_t, device_t);
 bool	xhci_suspend(device_t, const pmf_qual_t *);
 bool	xhci_resume(device_t, const pmf_qual_t *);
 bool	xhci_shutdown(device_t, int);
 #define XHCI_TRANSFER_RING_TRBS 256