Thu May 27 06:11:20 2021 UTC ()
fix build error with options ARMV85_BTI


(ryo)
diff -r1.4 -r1.5 src/sys/arch/aarch64/aarch64/procfs_machdep.c
diff -r1.19 -r1.20 src/sys/arch/aarch64/include/cpufunc.h
cvs diff -r1.4 -r1.5 src/sys/arch/aarch64/aarch64/procfs_machdep.c (expand / switch to unified diff)

--- src/sys/arch/aarch64/aarch64/procfs_machdep.c 2020/10/01 07:31:27 1.4
+++ src/sys/arch/aarch64/aarch64/procfs_machdep.c 2021/05/27 06:11:20 1.5
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: procfs_machdep.c,v 1.4 2020/10/01 07:31:27 skrll Exp $ */ 1/* $NetBSD: procfs_machdep.c,v 1.5 2021/05/27 06:11:20 ryo Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2020 Ryo Shimizu <ryo@nerv.org> 4 * Copyright (c) 2020 Ryo Shimizu <ryo@nerv.org>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -17,36 +17,36 @@ @@ -17,36 +17,36 @@
17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE. 26 * POSSIBILITY OF SUCH DAMAGE.
27 */ 27 */
28 28
29#include <sys/cdefs.h> 29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.4 2020/10/01 07:31:27 skrll Exp $"); 30__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.5 2021/05/27 06:11:20 ryo Exp $");
31 31
32#include <sys/param.h> 32#include <sys/param.h>
33#include <sys/cpu.h> 33#include <sys/cpu.h>
34#include <sys/systm.h> 34#include <sys/systm.h>
35 35
36#include <miscfs/procfs/procfs.h> 36#include <miscfs/procfs/procfs.h>
37 37
38#include <aarch64/armreg.h> 38#include <aarch64/armreg.h>
39 39#include <aarch64/cpufunc.h>
40 40
41/* use variables named 'buf', 'left', 'total' */ 41/* use variables named 'buf', 'left', 'total' */
42#define FORWARD_BUF(_len) \ 42#define FORWARD_BUF(_len) \
43 do { \ 43 do { \
44 total += _len; \ 44 total += _len; \
45 if (_len < left) { \ 45 if (_len < left) { \
46 buf += _len; \ 46 buf += _len; \
47 left -= _len; \ 47 left -= _len; \
48 } else { \ 48 } else { \
49 buf += left; \ 49 buf += left; \
50 left = 0; \ 50 left = 0; \
51 } \ 51 } \
52 } while (0 /*CONSTCOND*/) 52 } while (0 /*CONSTCOND*/)
cvs diff -r1.19 -r1.20 src/sys/arch/aarch64/include/cpufunc.h (expand / switch to unified diff)

--- src/sys/arch/aarch64/include/cpufunc.h 2020/12/04 08:29:11 1.19
+++ src/sys/arch/aarch64/include/cpufunc.h 2021/05/27 06:11:20 1.20
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpufunc.h,v 1.19 2020/12/04 08:29:11 skrll Exp $ */ 1/* $NetBSD: cpufunc.h,v 1.20 2021/05/27 06:11:20 ryo Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org> 4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -53,26 +53,27 @@ struct aarch64_cache_info { @@ -53,26 +53,27 @@ struct aarch64_cache_info {
53#define CACHE_CACHEABLE_ICACHE 1 /* instruction cache only */ 53#define CACHE_CACHEABLE_ICACHE 1 /* instruction cache only */
54#define CACHE_CACHEABLE_DCACHE 2 /* data cache only */ 54#define CACHE_CACHEABLE_DCACHE 2 /* data cache only */
55#define CACHE_CACHEABLE_IDCACHE 3 /* instruction and data caches */ 55#define CACHE_CACHEABLE_IDCACHE 3 /* instruction and data caches */
56#define CACHE_CACHEABLE_UNIFIED 4 /* unified cache */ 56#define CACHE_CACHEABLE_UNIFIED 4 /* unified cache */
57 struct aarch64_cache_unit icache; 57 struct aarch64_cache_unit icache;
58 struct aarch64_cache_unit dcache; 58 struct aarch64_cache_unit dcache;
59}; 59};
60 60
61#define MAX_CACHE_LEVEL 8 /* ARMv8 has maximum 8 level cache */ 61#define MAX_CACHE_LEVEL 8 /* ARMv8 has maximum 8 level cache */
62extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */ 62extern u_int aarch64_cache_vindexsize; /* cachesize/way (VIVT/VIPT) */
63extern u_int aarch64_cache_prefer_mask; 63extern u_int aarch64_cache_prefer_mask;
64extern u_int cputype; /* compat arm */ 64extern u_int cputype; /* compat arm */
65 65
 66extern int aarch64_bti_enabled;
66extern int aarch64_pan_enabled; 67extern int aarch64_pan_enabled;
67extern int aarch64_pac_enabled; 68extern int aarch64_pac_enabled;
68 69
69void aarch64_pan_init(int); 70void aarch64_pan_init(int);
70int aarch64_pac_init(int); 71int aarch64_pac_init(int);
71 72
72int set_cpufuncs(void); 73int set_cpufuncs(void);
73void aarch64_getcacheinfo(int); 74void aarch64_getcacheinfo(int);
74void aarch64_printcacheinfo(device_t); 75void aarch64_printcacheinfo(device_t);
75 76
76void aarch64_dcache_wbinv_all(void); 77void aarch64_dcache_wbinv_all(void);
77void aarch64_dcache_inv_all(void); 78void aarch64_dcache_inv_all(void);
78void aarch64_dcache_wb_all(void); 79void aarch64_dcache_wb_all(void);