 @@ -1,14 +1,14 @@
-/* $NetBSD: locore.h,v 1.118 2021/05/12 03:53:37 simonb Exp $ */
+/* $NetBSD: locore.h,v 1.119 2021/05/27 15:00:02 simonb Exp $ */
 /*
  * This file should not be included by MI code!!!
  */
 /*
  * Copyright 1996 The Board of Trustees of The Leland Stanford
  * Junior University. All Rights Reserved.
+ *
  * Permission to use, copy, modify, and distribute this
  * software and its documentation for any purpose and without
  * fee is hereby granted, provided that the above copyright
  * notice appear in all copies.  Stanford University
 @@ -337,28 +337,26 @@ struct trapframe;
 void	trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *);
 void	ast(void);
 void	mips_fpu_trap(vaddr_t, struct trapframe *);
 void	mips_fpu_intr(vaddr_t, struct trapframe *);
 vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool);
 void	mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *);
 void	mips_emul_fp(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_swc0(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_special(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_special3(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_swc1(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_lb(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_lbu(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_lh(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_lhu(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_lw(uint32_t, struct trapframe *, uint32_t);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: mips_emul.c,v 1.28 2021/05/27 13:32:54 simonb Exp $ */
+/*	$NetBSD: mips_emul.c,v 1.29 2021/05/27 15:00:02 simonb Exp $ */
 /*
  * Copyright (c) 1999 Shuichiro URATA.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
 @@ -17,46 +17,49 @@
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.28 2021/05/27 13:32:54 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.29 2021/05/27 15:00:02 simonb Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/cpu.h>
 #include <sys/proc.h>
 #include <mips/locore.h>
 #include <mips/mips_opcode.h>
 #include <mips/reg.h>
 #include <mips/regnum.h>			/* symbolic register indices */
 #include <mips/pcb.h>
 #include <mips/vmparam.h>			/* for VM_MAX_ADDRESS */
 #include <mips/trap.h>
 static inline void	send_sigsegv(intptr_t, uint32_t, struct trapframe *,
 			    uint32_t);
 static inline void	update_pc(struct trapframe *, uint32_t);
 static void	mips_emul_ll(uint32_t, struct trapframe *, uint32_t);
 static void	mips_emul_sc(uint32_t, struct trapframe *, uint32_t);
 /*
  * MIPS2 LL instruction emulation state
  */
 struct {
 	struct lwp *lwp;
 	vaddr_t addr;
 	uint32_t value;
 } llstate;
 /*
  * Analyse 'next' PC address taking account of branch/jump instructions
  */
 vaddr_t
 @@ -188,31 +191,31 @@ mips_emul_inst(uint32_t status, uint32_t
 	uint32_t inst;
 	ksiginfo_t ksi;
 	int code = ILL_ILLOPC;
 	/*
 	 *  Fetch the instruction.
 	 */
 	if (cause & MIPS_CR_BR_DELAY)
 		inst = mips_ufetch32((uint32_t *)opc+1);
 	else
 		inst = mips_ufetch32((uint32_t *)opc);
 	switch (((InstFmt)inst).FRType.op) {
-	case OP_LWC0:
+	case OP_LL:
-		mips_emul_lwc0(inst, tf, cause);
+		mips_emul_ll(inst, tf, cause);
 		break;
-	case OP_SWC0:
+	case OP_SC:
-		mips_emul_swc0(inst, tf, cause);
+		mips_emul_sc(inst, tf, cause);
 		break;
 	case OP_SPECIAL:
 		mips_emul_special(inst, tf, cause);
 		break;
 	case OP_SPECIAL3:
 		mips_emul_special3(inst, tf, cause);
 		break;
 	case OP_COP1:
 #if defined(FPEMUL)
 		mips_emul_fp(inst, tf, cause);
 		break;
 #endif
 	case OP_LWC1:
 @@ -279,27 +282,27 @@ update_pc(struct trapframe *tf, uint32_t
 	if (cause & MIPS_CR_BR_DELAY)
 		tf->tf_regs[_R_PC] =
 		    mips_emul_branch(tf, tf->tf_regs[_R_PC],
 			PCB_FSR(curpcb), 0);
 	else
 		tf->tf_regs[_R_PC] += 4;
+}
 /*
  * MIPS2 LL instruction
  */
 void
-mips_emul_lwc0(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_ll(uint32_t inst, struct trapframe *tf, uint32_t cause)
+{
 	intptr_t	vaddr;
 	int16_t		offset;
 	void		*t;
 	offset = inst & 0xFFFF;
 	vaddr = tf->tf_regs[(inst>>21)&0x1F] + offset;
 	/* segment and alignment check */
 	if (vaddr < 0 || (vaddr & 3)) {
 		send_sigsegv(vaddr, T_ADDR_ERR_LD, tf, cause);
 		return;
+	}
 @@ -312,27 +315,27 @@ mips_emul_lwc0(uint32_t inst, struct tra
+	}
 	llstate.lwp = curlwp;
 	llstate.addr = vaddr;
 	llstate.value = *((uint32_t *)t);
 	update_pc(tf, cause);
+}
 /*
  * MIPS2 SC instruction
  */
 void
-mips_emul_swc0(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_sc(uint32_t inst, struct trapframe *tf, uint32_t cause)
+{
 	intptr_t	vaddr;
 	uint32_t	value;
 	int16_t		offset;
 	mips_reg_t	*t;
 	offset = inst & 0xFFFF;
 	vaddr = tf->tf_regs[(inst>>21)&0x1F] + offset;
 	/* segment and alignment check */
 	if (vaddr < 0 || (vaddr & 3)) {
 		send_sigsegv(vaddr, T_ADDR_ERR_LD, tf, cause);
 		return;