Thu May 27 15:00:02 2021 UTC ()
Rename the unhelpfully named mips_emul_lwc0() and mips_emul_swc0() to
mips_emul_ll() and mips_emul_sc(); make these static to mips_emul.c.


(simonb)
diff -r1.118 -r1.119 src/sys/arch/mips/include/locore.h
diff -r1.28 -r1.29 src/sys/arch/mips/mips/mips_emul.c
cvs diff -r1.118 -r1.119 src/sys/arch/mips/include/locore.h (expand / switch to context diff)
--- src/sys/arch/mips/include/locore.h 2021/05/12 03:53:37 1.118
+++ src/sys/arch/mips/include/locore.h 2021/05/27 15:00:02 1.119
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.118 2021/05/12 03:53:37 simonb Exp $ */
+/* $NetBSD: locore.h,v 1.119 2021/05/27 15:00:02 simonb Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -347,8 +347,6 @@
 void	mips_emul_fp(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t);
 
-void	mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t);
-void	mips_emul_swc0(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_special(uint32_t, struct trapframe *, uint32_t);
 void	mips_emul_special3(uint32_t, struct trapframe *, uint32_t);
cvs diff -r1.28 -r1.29 src/sys/arch/mips/mips/mips_emul.c (expand / switch to context diff)
--- src/sys/arch/mips/mips/mips_emul.c 2021/05/27 13:32:54 1.28
+++ src/sys/arch/mips/mips/mips_emul.c 2021/05/27 15:00:02 1.29
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_emul.c,v 1.28 2021/05/27 13:32:54 simonb Exp $ */
+/*	$NetBSD: mips_emul.c,v 1.29 2021/05/27 15:00:02 simonb Exp $ */
 
 /*
  * Copyright (c) 1999 Shuichiro URATA.  All rights reserved.
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.28 2021/05/27 13:32:54 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.29 2021/05/27 15:00:02 simonb Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -47,6 +47,9 @@
 			    uint32_t);
 static inline void	update_pc(struct trapframe *, uint32_t);
 
+static void	mips_emul_ll(uint32_t, struct trapframe *, uint32_t);
+static void	mips_emul_sc(uint32_t, struct trapframe *, uint32_t);
+
 /*
  * MIPS2 LL instruction emulation state
  */
@@ -198,11 +201,11 @@
 		inst = mips_ufetch32((uint32_t *)opc);
 
 	switch (((InstFmt)inst).FRType.op) {
-	case OP_LWC0:
-		mips_emul_lwc0(inst, tf, cause);
+	case OP_LL:
+		mips_emul_ll(inst, tf, cause);
 		break;
-	case OP_SWC0:
-		mips_emul_swc0(inst, tf, cause);
+	case OP_SC:
+		mips_emul_sc(inst, tf, cause);
 		break;
 	case OP_SPECIAL:
 		mips_emul_special(inst, tf, cause);
@@ -289,7 +292,7 @@
  * MIPS2 LL instruction
  */
 void
-mips_emul_lwc0(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_ll(uint32_t inst, struct trapframe *tf, uint32_t cause)
 {
 	intptr_t	vaddr;
 	int16_t		offset;
@@ -322,7 +325,7 @@
  * MIPS2 SC instruction
  */
 void
-mips_emul_swc0(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_sc(uint32_t inst, struct trapframe *tf, uint32_t cause)
 {
 	intptr_t	vaddr;
 	uint32_t	value;