Thu Apr 6 04:44:09 2023 UTC ()
Regen.


(msaitoh)
diff -r1.1460 -r1.1461 src/sys/dev/pci/pcidevs.h
diff -r1.1459 -r1.1460 src/sys/dev/pci/pcidevs_data.h
cvs diff -r1.1460 -r1.1461 src/sys/dev/pci/pcidevs.h (expand / switch to unified diff)

--- src/sys/dev/pci/pcidevs.h 2023/02/14 14:43:16 1.1460
+++ src/sys/dev/pci/pcidevs.h 2023/04/06 04:44:09 1.1461
@@ -1,20 +1,20 @@ @@ -1,20 +1,20 @@
1/* $NetBSD: pcidevs.h,v 1.1460 2023/02/14 14:43:16 msaitoh Exp $ */ 1/* $NetBSD: pcidevs.h,v 1.1461 2023/04/06 04:44:09 msaitoh Exp $ */
2 2
3/* 3/*
4 * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT. 4 * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
5 * 5 *
6 * generated from: 6 * generated from:
7 * NetBSD: pcidevs,v 1.1479 2023/02/14 14:42:46 msaitoh Exp 7 * NetBSD: pcidevs,v 1.1480 2023/04/06 04:43:43 msaitoh Exp
8 */ 8 */
9 9
10/* 10/*
11 * Copyright (c) 1995, 1996 Christopher G. Demetriou 11 * Copyright (c) 1995, 1996 Christopher G. Demetriou
12 * All rights reserved. 12 * All rights reserved.
13 * 13 *
14 * Redistribution and use in source and binary forms, with or without 14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions 15 * modification, are permitted provided that the following conditions
16 * are met: 16 * are met:
17 * 1. Redistributions of source code must retain the above copyright 17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer. 18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright 19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the 20 * notice, this list of conditions and the following disclaimer in the
@@ -6213,27 +6213,27 @@ @@ -6213,27 +6213,27 @@
6213#define PCI_PRODUCT_INTEL_APL_UART_2 0x5ac0 /* Apollo Lake UART 2 */ 6213#define PCI_PRODUCT_INTEL_APL_UART_2 0x5ac0 /* Apollo Lake UART 2 */
6214#define PCI_PRODUCT_INTEL_APL_SPI_0 0x5ac2 /* Apollo Lake SPI 0 */ 6214#define PCI_PRODUCT_INTEL_APL_SPI_0 0x5ac2 /* Apollo Lake SPI 0 */
6215#define PCI_PRODUCT_INTEL_APL_SPI_1 0x5ac4 /* Apollo Lake SPI 1 */ 6215#define PCI_PRODUCT_INTEL_APL_SPI_1 0x5ac4 /* Apollo Lake SPI 1 */
6216#define PCI_PRODUCT_INTEL_APL_SPI_2 0x5ac6 /* Apollo Lake SPI 2 */ 6216#define PCI_PRODUCT_INTEL_APL_SPI_2 0x5ac6 /* Apollo Lake SPI 2 */
6217#define PCI_PRODUCT_INTEL_APL_SD 0x5aca /* Apollo Lake SD Card */ 6217#define PCI_PRODUCT_INTEL_APL_SD 0x5aca /* Apollo Lake SD Card */
6218#define PCI_PRODUCT_INTEL_APL_EMMC 0x5acc /* Apollo Lake eMMC */ 6218#define PCI_PRODUCT_INTEL_APL_EMMC 0x5acc /* Apollo Lake eMMC */
6219#define PCI_PRODUCT_INTEL_APL_SMB 0x5ad4 /* Apollo Lake SMBus */ 6219#define PCI_PRODUCT_INTEL_APL_SMB 0x5ad4 /* Apollo Lake SMBus */
6220#define PCI_PRODUCT_INTEL_APL_PCIE_B0 0x5ad6 /* Apollo Lake PCIe B0 */ 6220#define PCI_PRODUCT_INTEL_APL_PCIE_B0 0x5ad6 /* Apollo Lake PCIe B0 */
6221#define PCI_PRODUCT_INTEL_APL_PCIE_B1 0x5ad7 /* Apollo Lake PCIe B1 */ 6221#define PCI_PRODUCT_INTEL_APL_PCIE_B1 0x5ad7 /* Apollo Lake PCIe B1 */
6222#define PCI_PRODUCT_INTEL_APL_PCIE_A0 0x5ad8 /* Apollo Lake PCIe A0 */ 6222#define PCI_PRODUCT_INTEL_APL_PCIE_A0 0x5ad8 /* Apollo Lake PCIe A0 */
6223#define PCI_PRODUCT_INTEL_APL_PCIE_A1 0x5ad9 /* Apollo Lake PCIe A1 */ 6223#define PCI_PRODUCT_INTEL_APL_PCIE_A1 0x5ad9 /* Apollo Lake PCIe A1 */
6224#define PCI_PRODUCT_INTEL_APL_PCIE_A2 0x5ada /* Apollo Lake PCIe A2 */ 6224#define PCI_PRODUCT_INTEL_APL_PCIE_A2 0x5ada /* Apollo Lake PCIe A2 */
6225#define PCI_PRODUCT_INTEL_APL_PCIE_A3 0x5adb /* Apollo Lake PCIe A3 */ 6225#define PCI_PRODUCT_INTEL_APL_PCIE_A3 0x5adb /* Apollo Lake PCIe A3 */
6226#define PCI_PRODUCT_INTEL_APL_SATA 0x5ae0 /* Apollo Lake SATA */ 6226#define PCI_PRODUCT_INTEL_APL_SATA 0x5ae3 /* Apollo Lake SATA */
6227#define PCI_PRODUCT_INTEL_APL_LPC 0x5ae8 /* Apollo Lake LPC */ 6227#define PCI_PRODUCT_INTEL_APL_LPC 0x5ae8 /* Apollo Lake LPC */
6228#define PCI_PRODUCT_INTEL_APL_SSRAM 0x5aec /* Apollo Lake Shared SRAM */ 6228#define PCI_PRODUCT_INTEL_APL_SSRAM 0x5aec /* Apollo Lake Shared SRAM */
6229#define PCI_PRODUCT_INTEL_APL_UART_3 0x5aee /* Apollo Lake UART 3 */ 6229#define PCI_PRODUCT_INTEL_APL_UART_3 0x5aee /* Apollo Lake UART 3 */
6230#define PCI_PRODUCT_INTEL_APL_HB 0x5af0 /* Apollo Lake Host Bridge */ 6230#define PCI_PRODUCT_INTEL_APL_HB 0x5af0 /* Apollo Lake Host Bridge */
6231#define PCI_PRODUCT_INTEL_XEOND_HB_DMI2 0x6f00 /* Core i7-6xxxK/Xeon-D Host Bridge (DMI2) */ 6231#define PCI_PRODUCT_INTEL_XEOND_HB_DMI2 0x6f00 /* Core i7-6xxxK/Xeon-D Host Bridge (DMI2) */
6232#define PCI_PRODUCT_INTEL_XEOND_HB_PCIE 0x6f01 /* Xeon-D Host Bridge (PCIe) */ 6232#define PCI_PRODUCT_INTEL_XEOND_HB_PCIE 0x6f01 /* Xeon-D Host Bridge (PCIe) */
6233#define PCI_PRODUCT_INTEL_XEOND_PCIE_1 0x6f02 /* Xeon-D PCIe Root Port (x8 or x4 max) */ 6233#define PCI_PRODUCT_INTEL_XEOND_PCIE_1 0x6f02 /* Xeon-D PCIe Root Port (x8 or x4 max) */
6234#define PCI_PRODUCT_INTEL_XEOND_PCIE_2 0x6f03 /* Xeon-D PCIe Root Port (x8 or x4 max) */ 6234#define PCI_PRODUCT_INTEL_XEOND_PCIE_2 0x6f03 /* Xeon-D PCIe Root Port (x8 or x4 max) */
6235#define PCI_PRODUCT_INTEL_XEOND_PCIE_3 0x6f04 /* Core i7-6xxxK/Xeon-D PCIe Root Port */ 6235#define PCI_PRODUCT_INTEL_XEOND_PCIE_3 0x6f04 /* Core i7-6xxxK/Xeon-D PCIe Root Port */
6236#define PCI_PRODUCT_INTEL_COREI76K_PCIE_2 0x6f05 /* Core i7-6xxxK PCIe Root Port */ 6236#define PCI_PRODUCT_INTEL_COREI76K_PCIE_2 0x6f05 /* Core i7-6xxxK PCIe Root Port */
6237#define PCI_PRODUCT_INTEL_XEOND_PCIE_5 0x6f06 /* Core i7-6xxxK/Xeon-D PCIe Root Port */ 6237#define PCI_PRODUCT_INTEL_XEOND_PCIE_5 0x6f06 /* Core i7-6xxxK/Xeon-D PCIe Root Port */
6238#define PCI_PRODUCT_INTEL_COREI76K_PCIE_4 0x6f07 /* Core i7-6xxxK PCIe Root Port */ 6238#define PCI_PRODUCT_INTEL_COREI76K_PCIE_4 0x6f07 /* Core i7-6xxxK PCIe Root Port */
6239#define PCI_PRODUCT_INTEL_XEOND_PCIE_7 0x6f08 /* Core i7-6xxxK/Xeon-D PCIe Root Port (x16, x8 or x4 max) */ 6239#define PCI_PRODUCT_INTEL_XEOND_PCIE_7 0x6f08 /* Core i7-6xxxK/Xeon-D PCIe Root Port (x16, x8 or x4 max) */
cvs diff -r1.1459 -r1.1460 src/sys/dev/pci/pcidevs_data.h (expand / switch to unified diff)

--- src/sys/dev/pci/pcidevs_data.h 2023/02/14 14:43:15 1.1459
+++ src/sys/dev/pci/pcidevs_data.h 2023/04/06 04:44:08 1.1460
@@ -1,20 +1,20 @@ @@ -1,20 +1,20 @@
1/* $NetBSD: pcidevs_data.h,v 1.1459 2023/02/14 14:43:15 msaitoh Exp $ */ 1/* $NetBSD: pcidevs_data.h,v 1.1460 2023/04/06 04:44:08 msaitoh Exp $ */
2 2
3/* 3/*
4 * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT. 4 * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
5 * 5 *
6 * generated from: 6 * generated from:
7 * NetBSD: pcidevs,v 1.1479 2023/02/14 14:42:46 msaitoh Exp 7 * NetBSD: pcidevs,v 1.1480 2023/04/06 04:43:43 msaitoh Exp
8 */ 8 */
9 9
10/* 10/*
11 * Copyright (c) 1995, 1996 Christopher G. Demetriou 11 * Copyright (c) 1995, 1996 Christopher G. Demetriou
12 * All rights reserved. 12 * All rights reserved.
13 * 13 *
14 * Redistribution and use in source and binary forms, with or without 14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions 15 * modification, are permitted provided that the following conditions
16 * are met: 16 * are met:
17 * 1. Redistributions of source code must retain the above copyright 17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer. 18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright 19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the 20 * notice, this list of conditions and the following disclaimer in the