Thu Apr 6 04:44:09 2023 UTC ()
Regen.


(msaitoh)
diff -r1.1460 -r1.1461 src/sys/dev/pci/pcidevs.h
diff -r1.1459 -r1.1460 src/sys/dev/pci/pcidevs_data.h

cvs diff -r1.1460 -r1.1461 src/sys/dev/pci/pcidevs.h (expand / switch to context diff)
--- src/sys/dev/pci/pcidevs.h 2023/02/14 14:43:16 1.1460
+++ src/sys/dev/pci/pcidevs.h 2023/04/06 04:44:09 1.1461
@@ -1,10 +1,10 @@
-/*	$NetBSD: pcidevs.h,v 1.1460 2023/02/14 14:43:16 msaitoh Exp $	*/
+/*	$NetBSD: pcidevs.h,v 1.1461 2023/04/06 04:44:09 msaitoh Exp $	*/
 
 /*
  * THIS FILE IS AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *	NetBSD: pcidevs,v 1.1479 2023/02/14 14:42:46 msaitoh Exp
+ *	NetBSD: pcidevs,v 1.1480 2023/04/06 04:43:43 msaitoh Exp
  */
 
 /*
@@ -6223,7 +6223,7 @@
 #define	PCI_PRODUCT_INTEL_APL_PCIE_A1	0x5ad9		/* Apollo Lake PCIe A1 */
 #define	PCI_PRODUCT_INTEL_APL_PCIE_A2	0x5ada		/* Apollo Lake PCIe A2 */
 #define	PCI_PRODUCT_INTEL_APL_PCIE_A3	0x5adb		/* Apollo Lake PCIe A3 */
-#define	PCI_PRODUCT_INTEL_APL_SATA	0x5ae0		/* Apollo Lake SATA */
+#define	PCI_PRODUCT_INTEL_APL_SATA	0x5ae3		/* Apollo Lake SATA */
 #define	PCI_PRODUCT_INTEL_APL_LPC	0x5ae8		/* Apollo Lake LPC */
 #define	PCI_PRODUCT_INTEL_APL_SSRAM	0x5aec		/* Apollo Lake Shared SRAM */
 #define	PCI_PRODUCT_INTEL_APL_UART_3	0x5aee		/* Apollo Lake UART 3 */

cvs diff -r1.1459 -r1.1460 src/sys/dev/pci/pcidevs_data.h (expand / switch to context diff)
--- src/sys/dev/pci/pcidevs_data.h 2023/02/14 14:43:15 1.1459
+++ src/sys/dev/pci/pcidevs_data.h 2023/04/06 04:44:08 1.1460
@@ -1,10 +1,10 @@
-/*	$NetBSD: pcidevs_data.h,v 1.1459 2023/02/14 14:43:15 msaitoh Exp $	*/
+/*	$NetBSD: pcidevs_data.h,v 1.1460 2023/04/06 04:44:08 msaitoh Exp $	*/
 
 /*
  * THIS FILE IS AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *	NetBSD: pcidevs,v 1.1479 2023/02/14 14:42:46 msaitoh Exp
+ *	NetBSD: pcidevs,v 1.1480 2023/04/06 04:43:43 msaitoh Exp
  */
 
 /*