Tue Apr 11 02:44:06 2023 UTC ()
Add CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.


(msaitoh)
diff -r1.204 -r1.205 src/sys/arch/x86/include/specialreg.h
cvs diff -r1.204 -r1.205 src/sys/arch/x86/include/specialreg.h (expand / switch to unified diff)

--- src/sys/arch/x86/include/specialreg.h 2023/03/25 21:47:10 1.204
+++ src/sys/arch/x86/include/specialreg.h 2023/04/11 02:44:06 1.205
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: specialreg.h,v 1.204 2023/03/25 21:47:10 andvar Exp $ */ 1/* $NetBSD: specialreg.h,v 1.205 2023/04/11 02:44:06 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -456,41 +456,42 @@ @@ -456,41 +456,42 @@
456#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 456#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */
457#define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */ 457#define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */
458#define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */ 458#define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */
459#define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */ 459#define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */
460#define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */ 460#define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */
461#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */ 461#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */
462#define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */ 462#define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */
463#define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */ 463#define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */
464#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */ 464#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */
465#define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */ 465#define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */
466#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ 466#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
467#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 467#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
468#define CPUID_SEF_KL __BIT(23) /* Key Locker */ 468#define CPUID_SEF_KL __BIT(23) /* Key Locker */
 469#define CPUID_SEF_BUS_LOCK_DETECT __BIT(24) /* OS bus-lock detection */
469#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ 470#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
470#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ 471#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
471#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ 472#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
472#define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */ 473#define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */
473#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 474#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
474#define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */ 475#define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */
475 476
476#define CPUID_SEF_FLAGS1 "\177\20" \ 477#define CPUID_SEF_FLAGS1 "\177\20" \
477 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ 478 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
478 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ 479 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
479 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ 480 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
480 "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \ 481 "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \
481 "b\20LA57\0" \ 482 "b\20LA57\0" \
482 "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ 483 "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
483 "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ 484 "b\30\BUS_LOCK_DETECT" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
484 "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0" 485 "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0"
485 486
486/* %ecx = 0, %edx */ 487/* %ecx = 0, %edx */
487#define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */ 488#define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */
488#define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */ 489#define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */
489#define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */ 490#define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */
490#define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */ 491#define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */
491#define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */ 492#define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */
492#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */ 493#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */
493#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ 494#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */
494#define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */ 495#define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */
495#define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */ 496#define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */
496#define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ 497#define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */