 @@ -1,14 +1,14 @@
-/* $NetBSD: coretemp.c,v 1.36.4.1 2020/07/15 14:02:36 martin Exp $ */
+/* $NetBSD: coretemp.c,v 1.36.4.2 2023/07/29 11:01:14 martin Exp $ */
 /*-
  * Copyright (c) 2011 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jukka Ruohonen.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
+ *
  * 1. Redistributions of source code must retain the above copyright
 @@ -51,27 +51,27 @@
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
+ *
  * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.4 2007/10/15 20:00:21 netchild Exp $
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.36.4.1 2020/07/15 14:02:36 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.36.4.2 2023/07/29 11:01:14 martin Exp $");
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/cpu.h>
 #include <sys/module.h>
 #include <sys/xcall.h>
 #include <dev/sysmon/sysmonvar.h>
 #include <machine/cpuvar.h>
 #include <machine/cpufunc.h>
 #include <machine/cputypes.h>
 #include <machine/specialreg.h>
 @@ -92,26 +92,30 @@ __KERNEL_RCSID(0, "$NetBSD: coretemp.c,v
 #define MSR_THERM_INTR_HITEMP		__BIT(0)
 #define MSR_THERM_INTR_LOTEMPT		__BIT(1)
 #define MSR_THERM_INTR_PROCHOT		__BIT(2)
 #define MSR_THERM_INTR_FORCPR		__BIT(3)
 #define MSR_THERM_INTR_OVERHEAT		__BIT(4)
 #define MSR_THERM_INTR_TRIP1_VAL	__BITS(8, 14)
 #define MSR_THERM_INTR_TRIP1		__BIT(15)
 #define MSR_THERM_INTR_TRIP2_VAL	__BITS(16, 22)
 #define MSR_THERM_INTR_TRIP2		__BIT(23)
 #define MSR_TEMP_TARGET_READOUT		__BITS(16, 23)
 #define TJMAX_DEFAULT		100
 #define TJMAX_LIMIT_LOW		60
 #define TJMAX_LIMIT_HIGH	120
 static int	coretemp_match(device_t, cfdata_t, void *);
 static void	coretemp_attach(device_t, device_t, void *);
 static int	coretemp_detach(device_t, int);
 static int	coretemp_quirks(struct cpu_info *);
 static void	coretemp_tjmax(device_t);
 static void	coretemp_refresh(struct sysmon_envsys *, envsys_data_t *);
 static void	coretemp_refresh_xcall(void *, void *);
 struct coretemp_softc {
 	device_t		 sc_dev;
 	struct cpu_info		*sc_ci;
 	struct sysmon_envsys	*sc_sme;
 	envsys_data_t		 sc_sensor;
 @@ -249,36 +253,35 @@ coretemp_quirks(struct cpu_info *ci)
 		if (msr < 0x39)
 			return 0;
+	}
 	return 1;
+}
 void
 coretemp_tjmax(device_t self)
+{
 	struct coretemp_softc *sc = device_private(self);
 	struct cpu_info *ci = sc->sc_ci;
 	uint32_t model, stepping;
 	uint64_t msr;
 	uint32_t model, stepping;
 	int tjmax;
 	model = CPUID_TO_MODEL(ci->ci_signature);
 	stepping = CPUID_TO_STEPPING(ci->ci_signature);
-	/*
+	/* Set the initial value. */
-	 * Use 100C as the initial value.
+	sc->sc_tjmax = TJMAX_DEFAULT;
 	 */
 	sc->sc_tjmax = 100;
 	if ((model == 0x0f && stepping >= 2) || (model == 0x0e)) {
 		/*
 		 * Check MSR_IA32_PLATFORM_ID(0x17) bit 28. It's not documented
 		 * in the datasheet, but the following page describes the
 		 * detail:
 		 *   http://software.intel.com/en-us/articles/
 		 *     mobile-intel-core2-processor-detection-table/
 		 *   Was: http://softwarecommunity.intel.com/Wiki/Mobility/
 		 *     720.htm
 		 */
 		if (rdmsr_safe(MSR_IA32_PLATFORM_ID, &msr) != 0)
 			goto notee;
 @@ -294,57 +297,57 @@ coretemp_tjmax(device_t self)
+		}
 	} else if (model == 0x17 && stepping == 0x06) {
 		/* The mobile Penryn family. */
 		sc->sc_tjmax = 105;
 		return;
 	} else if (model == 0x1c) {
 		if (stepping == 0x0a) {
 			/* 45nm Atom D400, N400 and D500 series */
 			sc->sc_tjmax = 100;
 		} else
 			sc->sc_tjmax = 90;
 	} else {
 notee:
-		/*
+		/* Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET. */
-		 * Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET,
+		if (rdmsr_safe(MSR_TEMPERATURE_TARGET, &msr) == EFAULT) {
-		 * but only consider the interval [70, 110] C as valid.
+			aprint_error_dev(sc->sc_dev,
-		 * It is not fully known which CPU models have the MSR.
+			    "Failed to read TEMPERATURE_TARGET MSR. "
-		 */
+			    "Use the default (%d)\n", sc->sc_tjmax);
 		if (rdmsr_safe(MSR_TEMPERATURE_TARGET, &msr) == EFAULT)
 			return;
 		msr = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);
 		if (msr >= 70 && msr <= 110) {
 			sc->sc_tjmax = msr;
 			return;
+		}
 		tjmax = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);
 		if ((tjmax < TJMAX_LIMIT_LOW) || (tjmax > TJMAX_LIMIT_HIGH))
 			aprint_error_dev(sc->sc_dev,
 			    "WARNING: Tjmax(%d) might exceeded the limit.\n",
 			    tjmax);
 		sc->sc_tjmax = tjmax;
+	}
+}
 static void
 coretemp_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
+{
 	struct coretemp_softc *sc = sme->sme_cookie;
 	uint64_t xc;
 	xc = xc_unicast(0, coretemp_refresh_xcall, sc, edata, sc->sc_ci);
 	xc_wait(xc);
+}
 static void
 coretemp_refresh_xcall(void *arg0, void *arg1)
+{
-        struct coretemp_softc *sc = arg0;
+	struct coretemp_softc *sc = arg0;
 	envsys_data_t *edata = arg1;
 	uint64_t msr;
 	msr = rdmsr(MSR_THERM_STATUS);
 	if ((msr & MSR_THERM_STATUS_VALID) == 0)
 		edata->state = ENVSYS_SINVALID;
 	else {
 		/*
 		 * The temperature is computed by
 		 * subtracting the reading by Tj(max).
 		 */
 		edata->value_cur = sc->sc_tjmax;