Sat Jul 29 11:01:15 2023 UTC ()
Pull up following revision(s) (requested by msaitoh in ticket #254):

	sys/arch/x86/x86/coretemp.c: revision 1.38-1.39 (patch)

coretemp(4): Change limits of Tjmax.
 - Change the lower limit from 70 to 60. At least, some BIOSes can change
   the value down to 62.
 - Change the upper limit from 110 to 120. At least, some BIOSes can change
   the value up to 115.
 - Print error message when rdmsr(TEMPERATURE_TARGET) failed.
 - When Tjmax exceeded the limit, print warning message and use the value
   as it is.
 - KNF.


(martin)
diff -r1.36.4.1 -r1.36.4.2 src/sys/arch/x86/x86/coretemp.c

cvs diff -r1.36.4.1 -r1.36.4.2 src/sys/arch/x86/x86/coretemp.c (expand / switch to context diff)
--- src/sys/arch/x86/x86/coretemp.c 2020/07/15 14:02:36 1.36.4.1
+++ src/sys/arch/x86/x86/coretemp.c 2023/07/29 11:01:14 1.36.4.2
@@ -1,4 +1,4 @@
-/* $NetBSD: coretemp.c,v 1.36.4.1 2020/07/15 14:02:36 martin Exp $ */
+/* $NetBSD: coretemp.c,v 1.36.4.2 2023/07/29 11:01:14 martin Exp $ */
 
 /*-
  * Copyright (c) 2011 The NetBSD Foundation, Inc.
@@ -61,7 +61,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.36.4.1 2020/07/15 14:02:36 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.36.4.2 2023/07/29 11:01:14 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -102,6 +102,10 @@
 
 #define MSR_TEMP_TARGET_READOUT		__BITS(16, 23)
 
+#define TJMAX_DEFAULT		100
+#define TJMAX_LIMIT_LOW		60
+#define TJMAX_LIMIT_HIGH	120
+
 static int	coretemp_match(device_t, cfdata_t, void *);
 static void	coretemp_attach(device_t, device_t, void *);
 static int	coretemp_detach(device_t, int);
@@ -259,16 +263,15 @@
 {
 	struct coretemp_softc *sc = device_private(self);
 	struct cpu_info *ci = sc->sc_ci;
-	uint32_t model, stepping;
 	uint64_t msr;
+	uint32_t model, stepping;
+	int tjmax;
 
 	model = CPUID_TO_MODEL(ci->ci_signature);
 	stepping = CPUID_TO_STEPPING(ci->ci_signature);
 
-	/*
-	 * Use 100C as the initial value.
-	 */
-	sc->sc_tjmax = 100;
+	/* Set the initial value. */
+	sc->sc_tjmax = TJMAX_DEFAULT;
 
 	if ((model == 0x0f && stepping >= 2) || (model == 0x0e)) {
 		/*
@@ -304,20 +307,20 @@
 			sc->sc_tjmax = 90;
 	} else {
 notee:
-		/*
-		 * Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET,
-		 * but only consider the interval [70, 110] C as valid.
-		 * It is not fully known which CPU models have the MSR.
-		 */
-		if (rdmsr_safe(MSR_TEMPERATURE_TARGET, &msr) == EFAULT)
+		/* Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET. */
+		if (rdmsr_safe(MSR_TEMPERATURE_TARGET, &msr) == EFAULT) {
+			aprint_error_dev(sc->sc_dev,
+			    "Failed to read TEMPERATURE_TARGET MSR. "
+			    "Use the default (%d)\n", sc->sc_tjmax);
 			return;
-
-		msr = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);
-
-		if (msr >= 70 && msr <= 110) {
-			sc->sc_tjmax = msr;
-			return;
 		}
+
+		tjmax = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);
+		if ((tjmax < TJMAX_LIMIT_LOW) || (tjmax > TJMAX_LIMIT_HIGH))
+			aprint_error_dev(sc->sc_dev,
+			    "WARNING: Tjmax(%d) might exceeded the limit.\n",
+			    tjmax);
+		sc->sc_tjmax = tjmax;
 	}
 }
 
@@ -334,7 +337,7 @@
 static void
 coretemp_refresh_xcall(void *arg0, void *arg1)
 {
-        struct coretemp_softc *sc = arg0;
+	struct coretemp_softc *sc = arg0;
 	envsys_data_t *edata = arg1;
 	uint64_t msr;